1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot Marvell 37xx SoC pinctrl driver
5 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
7 * This driver is based on the Linux driver version, which is:
8 * Copyright (C) 2017 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
15 * Copyright (C) 2016 Endless Mobile, Inc.
16 * https://spdx.org/licenses
23 #include <asm/global_data.h>
24 #include <dm/device-internal.h>
25 #include <dm/device_compat.h>
26 #include <dm/devres.h>
28 #include <dm/pinctrl.h>
34 #include <asm/system.h>
36 #include <linux/bitops.h>
37 #include <linux/libfdt.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 #define INPUT_VAL 0x10
43 #define OUTPUT_VAL 0x18
44 #define OUTPUT_CTL 0x20
45 #define SELECTION 0x30
49 #define IRQ_STATUS 0x10
53 #define GPIO_PER_REG 32
56 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
57 * The pins of a pinmux groups are composed of one or two groups of contiguous
59 * @name: Name of the pin group, used to lookup the group.
60 * @start_pins: Index of the first pin of the main range of pins belonging to
62 * @npins: Number of pins included in the first range
63 * @reg_mask: Bit mask matching the group in the selection register
64 * @extra_pins: Index of the first pin of the optional second range of pins
65 * belonging to the group
66 * @npins: Number of pins included in the second optional range
67 * @funcs: A list of pinmux functions that can be selected for this group.
69 struct armada_37xx_pin_group {
71 unsigned int start_pin;
75 unsigned int extra_pin;
76 unsigned int extra_npins;
77 const char *funcs[NB_FUNCS];
80 struct armada_37xx_pin_data {
83 struct armada_37xx_pin_group *groups;
87 struct armada_37xx_pmx_func {
93 struct armada_37xx_pinctrl {
95 const struct armada_37xx_pin_data *data;
97 struct pinctrl_dev *pctl_dev;
98 struct armada_37xx_pmx_func *funcs;
102 #define PIN_GRP_GPIO_0(_name, _start, _nr) \
105 .start_pin = _start, \
112 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
115 .start_pin = _start, \
119 .funcs = {_func1, "gpio"} \
122 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
125 .start_pin = _start, \
128 .val = {_val1, _val2}, \
129 .funcs = {_func1, "gpio"} \
132 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
135 .start_pin = _start, \
138 .val = {_v1, _v2, _v3}, \
139 .funcs = {_f1, _f2, "gpio"} \
142 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
146 .start_pin = _start, \
150 .extra_pin = _start2, \
151 .extra_npins = _nr2, \
152 .funcs = {_f1, _f2} \
155 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
156 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
157 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
158 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
159 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
161 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
163 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
165 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
167 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
168 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
169 PIN_GRP_GPIO_0("gpio1_5", 5, 1),
170 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
171 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
172 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
173 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
174 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
175 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
176 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
177 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
178 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
179 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
180 18, 2, "gpio", "uart"),
183 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
184 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
185 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
186 PIN_GRP_GPIO_0("gpio2_2", 2, 1),
187 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
188 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
189 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
190 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
191 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
192 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
193 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"),
194 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12),
196 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13),
198 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
202 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
205 .groups = armada_37xx_nb_groups,
206 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
209 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
212 .groups = armada_37xx_sb_groups,
213 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
216 static inline void armada_37xx_update_reg(unsigned int *reg,
217 unsigned int *offset)
219 /* We never have more than 2 registers */
220 if (*offset >= GPIO_PER_REG) {
221 *offset -= GPIO_PER_REG;
226 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
231 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
232 if (!strcmp(grp->funcs[f], func))
238 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
240 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
242 return info->data->ngroups;
245 static const char *armada_37xx_pmx_dummy_name = "_dummy";
247 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
250 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
252 if (!info->data->groups[selector].name)
253 return armada_37xx_pmx_dummy_name;
255 return info->data->groups[selector].name;
258 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
260 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
265 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
268 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
270 return info->funcs[selector].name;
273 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
275 struct armada_37xx_pin_group *grp,
278 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
279 unsigned int reg = SELECTION;
280 unsigned int mask = grp->reg_mask;
281 int func, val, old_func;
283 dev_dbg(info->dev, "enable function %s group %s\n",
286 func = armada_37xx_get_func_reg(grp, name);
291 val = grp->val[func];
293 if (warn_on_change && val != (readl(info->base + reg) & mask)) {
294 for (old_func = 0; (old_func < NB_FUNCS) && grp->funcs[old_func]; old_func++) {
295 if (grp->val[old_func] == val)
298 dev_warn(info->dev, "Warning: Changing MPPs %u-%u function from %s to %s...\n",
299 grp->start_pin, grp->start_pin + grp->npins - 1,
300 ((old_func < NB_FUNCS && grp->funcs[old_func]) ?
301 grp->funcs[old_func] : "unknown"),
305 clrsetbits_le32(info->base + reg, mask, val);
310 static int armada_37xx_pmx_group_set(struct udevice *dev,
311 unsigned group_selector,
312 unsigned func_selector)
314 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
315 struct armada_37xx_pin_group *grp = &info->data->groups[group_selector];
316 const char *name = info->funcs[func_selector].name;
318 return armada_37xx_pmx_set_by_name(dev, name, grp, false);
321 static int armada_37xx_pmx_gpio_request_enable(struct udevice *dev, unsigned int selector)
323 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
327 /* Find all groups where is requested selector pin and set each group to gpio function */
328 for (n = 0; n < info->data->ngroups; n++) {
329 struct armada_37xx_pin_group *grp = &info->data->groups[n];
331 if ((selector >= grp->start_pin && selector < grp->start_pin + grp->npins) ||
332 (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins)) {
333 ret = armada_37xx_pmx_set_by_name(dev, "gpio", grp, true);
342 static int armada_37xx_pmx_gpio_disable_free(struct udevice *dev, unsigned int selector)
348 static int armada_37xx_pmx_get_pins_count(struct udevice *dev)
350 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
352 return info->data->nr_pins;
355 static const char *armada_37xx_pmx_get_pin_name(struct udevice *dev, unsigned int selector)
357 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
358 static char buf[sizeof("MPPx_XX")];
360 sprintf(buf, "MPP%c_%u", info->data->name[4], selector);
364 static int armada_37xx_pmx_get_pin_muxing(struct udevice *dev, unsigned int selector,
367 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
371 * First check if selected pin is in some extra pin group.
372 * Function in extra pin group is active only when it is not gpio.
374 for (n = 0; n < info->data->ngroups; n++) {
375 struct armada_37xx_pin_group *grp = &info->data->groups[n];
377 if (selector >= grp->extra_pin && selector < grp->extra_pin + grp->extra_npins) {
378 unsigned int reg = SELECTION;
379 unsigned int mask = grp->reg_mask;
382 val = (readl(info->base + reg) & mask);
384 for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
385 if (grp->val[f] == val) {
386 if (strcmp(grp->funcs[f], "gpio") != 0) {
387 strlcpy(buf, grp->funcs[f], size);
396 /* If pin is not active in some extra pin group then check regular groups. */
397 for (n = 0; n < info->data->ngroups; n++) {
398 struct armada_37xx_pin_group *grp = &info->data->groups[n];
400 if (selector >= grp->start_pin && selector < grp->start_pin + grp->npins) {
401 unsigned int reg = SELECTION;
402 unsigned int mask = grp->reg_mask;
405 val = (readl(info->base + reg) & mask);
407 for (f = 0; f < NB_FUNCS && grp->funcs[f]; f++) {
408 if (grp->val[f] == val) {
410 * In more cases group name consist of
411 * function name followed by function
412 * number. So if function name is just
413 * prefix of group name, show group name.
415 if (strncmp(grp->name, grp->funcs[f],
416 strlen(grp->funcs[f])) == 0)
417 strlcpy(buf, grp->name, size);
419 strlcpy(buf, grp->funcs[f], size);
424 strlcpy(buf, "unknown", size);
429 strlcpy(buf, "unknown", size);
434 * armada_37xx_add_function() - Add a new function to the list
435 * @funcs: array of function to add the new one
436 * @funcsize: size of the remaining space for the function
437 * @name: name of the function to add
439 * If it is a new function then create it by adding its name else
440 * increment the number of group associated to this function.
442 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
443 int *funcsize, const char *name)
450 while (funcs->ngroups) {
451 /* function already there */
452 if (strcmp(funcs->name, name) == 0) {
461 /* append new unique function */
470 * armada_37xx_fill_group() - complete the group array
471 * @info: info driver instance
473 * Based on the data available from the armada_37xx_pin_group array
474 * completes the last member of the struct for each function: the list
475 * of the groups associated to this function.
478 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
480 int n, num = 0, funcsize = info->data->nr_pins;
482 for (n = 0; n < info->data->ngroups; n++) {
483 struct armada_37xx_pin_group *grp = &info->data->groups[n];
486 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
488 /* check for unique functions and count groups */
489 ret = armada_37xx_add_function(info->funcs, &funcsize,
491 if (ret == -EOVERFLOW)
493 "More functions than pins(%d)\n",
494 info->data->nr_pins);
507 * armada_37xx_fill_funcs() - complete the funcs array
508 * @info: info driver instance
510 * Based on the data available from the armada_37xx_pin_group array
511 * completes the last two member of the struct for each group:
512 * - the list of the pins included in the group
513 * - the list of pinmux functions that can be selected for this group
516 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
518 struct armada_37xx_pmx_func *funcs = info->funcs;
521 for (n = 0; n < info->nfuncs; n++) {
522 const char *name = funcs[n].name;
526 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
527 sizeof(*(funcs[n].groups)),
529 if (!funcs[n].groups)
532 groups = funcs[n].groups;
534 for (g = 0; g < info->data->ngroups; g++) {
535 struct armada_37xx_pin_group *gp = &info->data->groups[g];
538 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
539 if (strcmp(gp->funcs[f], name) == 0) {
549 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
551 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
552 unsigned int reg = INPUT_VAL;
553 unsigned int val, mask;
555 armada_37xx_update_reg(®, &offset);
558 val = readl(info->base + reg);
560 return (val & mask) != 0;
563 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
566 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
567 unsigned int reg = OUTPUT_VAL;
568 unsigned int mask, val;
570 armada_37xx_update_reg(®, &offset);
572 val = value ? mask : 0;
574 clrsetbits_le32(info->base + reg, mask, val);
579 static int armada_37xx_gpio_get_direction(struct udevice *dev,
582 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
583 unsigned int reg = OUTPUT_EN;
584 unsigned int val, mask;
586 armada_37xx_update_reg(®, &offset);
588 val = readl(info->base + reg);
596 static int armada_37xx_gpio_direction_input(struct udevice *dev,
599 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
600 unsigned int reg = OUTPUT_EN;
603 armada_37xx_update_reg(®, &offset);
606 clrbits_le32(info->base + reg, mask);
611 static int armada_37xx_gpio_direction_output(struct udevice *dev,
612 unsigned int offset, int value)
614 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
615 unsigned int reg = OUTPUT_EN;
618 armada_37xx_update_reg(®, &offset);
621 setbits_le32(info->base + reg, mask);
623 /* And set the requested value */
624 return armada_37xx_gpio_set(dev, offset, value);
627 static int armada_37xx_gpio_probe(struct udevice *dev)
629 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
630 struct gpio_dev_priv *uc_priv;
632 uc_priv = dev_get_uclass_priv(dev);
633 uc_priv->bank_name = info->data->name;
634 uc_priv->gpio_count = info->data->nr_pins;
639 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
640 .request = pinctrl_gpio_request,
641 .rfree = pinctrl_gpio_free,
642 .set_value = armada_37xx_gpio_set,
643 .get_value = armada_37xx_gpio_get,
644 .get_function = armada_37xx_gpio_get_direction,
645 .direction_input = armada_37xx_gpio_direction_input,
646 .direction_output = armada_37xx_gpio_direction_output,
649 static struct driver armada_37xx_gpio_driver = {
650 .name = "armada-37xx-gpio",
652 .probe = armada_37xx_gpio_probe,
653 .ops = &armada_37xx_gpio_ops,
656 static int armada_37xx_gpiochip_register(struct udevice *parent,
657 struct armada_37xx_pinctrl *info)
659 const void *blob = gd->fdt_blob;
660 int node = dev_of_offset(parent);
661 struct uclass_driver *drv;
667 /* FIXME: Should not need to lookup GPIO uclass */
668 drv = lists_uclass_lookup(UCLASS_GPIO);
670 puts("Cannot find GPIO driver\n");
674 /* FIXME: Use livtree and check the result of device_bind() below */
675 fdt_for_each_subnode(subnode, blob, node) {
676 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
684 name = calloc(1, 32);
685 sprintf(name, "armada-37xx-gpio");
687 /* Create child device UCLASS_GPIO and bind it */
688 device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
689 offset_to_ofnode(subnode), &dev);
694 static const struct pinctrl_ops armada_37xx_pinctrl_ops = {
695 .get_pins_count = armada_37xx_pmx_get_pins_count,
696 .get_pin_name = armada_37xx_pmx_get_pin_name,
697 .get_pin_muxing = armada_37xx_pmx_get_pin_muxing,
698 .get_groups_count = armada_37xx_pmx_get_groups_count,
699 .get_group_name = armada_37xx_pmx_get_group_name,
700 .get_functions_count = armada_37xx_pmx_get_funcs_count,
701 .get_function_name = armada_37xx_pmx_get_func_name,
702 .pinmux_group_set = armada_37xx_pmx_group_set,
703 .gpio_request_enable = armada_37xx_pmx_gpio_request_enable,
704 .gpio_disable_free = armada_37xx_pmx_gpio_disable_free,
705 .set_state = pinctrl_generic_set_state,
708 static int armada_37xx_pinctrl_probe(struct udevice *dev)
710 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
711 const struct armada_37xx_pin_data *pin_data;
714 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
715 pin_data = info->data;
717 info->base = dev_read_addr_ptr(dev);
719 pr_err("unable to find regmap\n");
724 * we allocate functions for number of pins and hope there are
725 * fewer unique functions than pins available
727 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
728 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
733 ret = armada_37xx_fill_group(info);
737 ret = armada_37xx_fill_func(info);
741 ret = armada_37xx_gpiochip_register(dev, info);
748 static int armada_37xx_pinctrl_bind(struct udevice *dev)
751 * Make sure that the pinctrl driver gets probed after binding
752 * as on A37XX the pinctrl driver is the one that is also
753 * registering the GPIO one during probe, so if its not probed
754 * GPIO-s are not registered as well.
756 dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
761 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
763 .compatible = "marvell,armada3710-sb-pinctrl",
764 .data = (ulong)&armada_37xx_pin_sb,
767 .compatible = "marvell,armada3710-nb-pinctrl",
768 .data = (ulong)&armada_37xx_pin_nb,
773 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
774 .name = "armada-37xx-pinctrl",
775 .id = UCLASS_PINCTRL,
776 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
777 .probe = armada_37xx_pinctrl_probe,
778 .bind = armada_37xx_pinctrl_bind,
779 .priv_auto = sizeof(struct armada_37xx_pinctrl),
780 .ops = &armada_37xx_pinctrl_ops,