1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot Marvell 37xx SoC pinctrl driver
5 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
7 * This driver is based on the Linux driver version, which is:
8 * Copyright (C) 2017 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
15 * Copyright (C) 2016 Endless Mobile, Inc.
16 * https://spdx.org/licenses
23 #include <asm/global_data.h>
24 #include <dm/device-internal.h>
25 #include <dm/device_compat.h>
26 #include <dm/devres.h>
28 #include <dm/pinctrl.h>
34 #include <asm/system.h>
36 #include <linux/bitops.h>
37 #include <linux/libfdt.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 #define INPUT_VAL 0x10
43 #define OUTPUT_VAL 0x18
44 #define OUTPUT_CTL 0x20
45 #define SELECTION 0x30
49 #define IRQ_STATUS 0x10
53 #define GPIO_PER_REG 32
56 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
57 * The pins of a pinmux groups are composed of one or two groups of contiguous
59 * @name: Name of the pin group, used to lookup the group.
60 * @start_pins: Index of the first pin of the main range of pins belonging to
62 * @npins: Number of pins included in the first range
63 * @reg_mask: Bit mask matching the group in the selection register
64 * @extra_pins: Index of the first pin of the optional second range of pins
65 * belonging to the group
66 * @npins: Number of pins included in the second optional range
67 * @funcs: A list of pinmux functions that can be selected for this group.
69 struct armada_37xx_pin_group {
71 unsigned int start_pin;
75 unsigned int extra_pin;
76 unsigned int extra_npins;
77 const char *funcs[NB_FUNCS];
80 struct armada_37xx_pin_data {
83 struct armada_37xx_pin_group *groups;
87 struct armada_37xx_pmx_func {
93 struct armada_37xx_pinctrl {
95 const struct armada_37xx_pin_data *data;
97 struct pinctrl_dev *pctl_dev;
98 struct armada_37xx_pmx_func *funcs;
102 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
105 .start_pin = _start, \
109 .funcs = {_func1, _func2} \
112 #define PIN_GRP_GPIO_0(_name, _start, _nr) \
115 .start_pin = _start, \
122 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
125 .start_pin = _start, \
129 .funcs = {_func1, "gpio"} \
132 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
135 .start_pin = _start, \
138 .val = {_val1, _val2}, \
139 .funcs = {_func1, "gpio"} \
142 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
145 .start_pin = _start, \
148 .val = {_v1, _v2, _v3}, \
149 .funcs = {_f1, _f2, "gpio"} \
152 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
156 .start_pin = _start, \
160 .extra_pin = _start2, \
161 .extra_npins = _nr2, \
162 .funcs = {_f1, _f2} \
165 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
166 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
167 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
168 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
169 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
171 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
173 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
175 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
177 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
178 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
179 PIN_GRP_GPIO_0("gpio1_5", 5, 1),
180 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
181 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
182 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
183 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
184 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
185 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
186 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
187 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
188 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
189 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
190 18, 2, "gpio", "uart"),
193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
194 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
195 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
196 PIN_GRP_GPIO_0("gpio2_2", 2, 1),
197 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
198 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
199 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
200 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
201 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
202 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
203 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
204 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
205 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
206 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
210 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
213 .groups = armada_37xx_nb_groups,
214 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
217 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
220 .groups = armada_37xx_sb_groups,
221 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
224 static inline void armada_37xx_update_reg(unsigned int *reg,
225 unsigned int *offset)
227 /* We never have more than 2 registers */
228 if (*offset >= GPIO_PER_REG) {
229 *offset -= GPIO_PER_REG;
234 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
239 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
240 if (!strcmp(grp->funcs[f], func))
246 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
248 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
250 return info->data->ngroups;
253 static const char *armada_37xx_pmx_dummy_name = "_dummy";
255 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
258 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
260 if (!info->data->groups[selector].name)
261 return armada_37xx_pmx_dummy_name;
263 return info->data->groups[selector].name;
266 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
268 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
273 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
276 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
278 return info->funcs[selector].name;
281 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
283 struct armada_37xx_pin_group *grp)
285 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
286 unsigned int reg = SELECTION;
287 unsigned int mask = grp->reg_mask;
290 dev_dbg(info->dev, "enable function %s group %s\n",
293 func = armada_37xx_get_func_reg(grp, name);
298 val = grp->val[func];
300 clrsetbits_le32(info->base + reg, mask, val);
305 static int armada_37xx_pmx_group_set(struct udevice *dev,
306 unsigned group_selector,
307 unsigned func_selector)
309 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
310 struct armada_37xx_pin_group *grp = &info->data->groups[group_selector];
311 const char *name = info->funcs[func_selector].name;
313 return armada_37xx_pmx_set_by_name(dev, name, grp);
317 * armada_37xx_add_function() - Add a new function to the list
318 * @funcs: array of function to add the new one
319 * @funcsize: size of the remaining space for the function
320 * @name: name of the function to add
322 * If it is a new function then create it by adding its name else
323 * increment the number of group associated to this function.
325 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
326 int *funcsize, const char *name)
333 while (funcs->ngroups) {
334 /* function already there */
335 if (strcmp(funcs->name, name) == 0) {
344 /* append new unique function */
353 * armada_37xx_fill_group() - complete the group array
354 * @info: info driver instance
356 * Based on the data available from the armada_37xx_pin_group array
357 * completes the last member of the struct for each function: the list
358 * of the groups associated to this function.
361 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
363 int n, num = 0, funcsize = info->data->nr_pins;
365 for (n = 0; n < info->data->ngroups; n++) {
366 struct armada_37xx_pin_group *grp = &info->data->groups[n];
369 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
371 /* check for unique functions and count groups */
372 ret = armada_37xx_add_function(info->funcs, &funcsize,
374 if (ret == -EOVERFLOW)
376 "More functions than pins(%d)\n",
377 info->data->nr_pins);
390 * armada_37xx_fill_funcs() - complete the funcs array
391 * @info: info driver instance
393 * Based on the data available from the armada_37xx_pin_group array
394 * completes the last two member of the struct for each group:
395 * - the list of the pins included in the group
396 * - the list of pinmux functions that can be selected for this group
399 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
401 struct armada_37xx_pmx_func *funcs = info->funcs;
404 for (n = 0; n < info->nfuncs; n++) {
405 const char *name = funcs[n].name;
409 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
410 sizeof(*(funcs[n].groups)),
412 if (!funcs[n].groups)
415 groups = funcs[n].groups;
417 for (g = 0; g < info->data->ngroups; g++) {
418 struct armada_37xx_pin_group *gp = &info->data->groups[g];
421 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
422 if (strcmp(gp->funcs[f], name) == 0) {
432 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
434 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
435 unsigned int reg = INPUT_VAL;
436 unsigned int val, mask;
438 armada_37xx_update_reg(®, &offset);
441 val = readl(info->base + reg);
443 return (val & mask) != 0;
446 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
449 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
450 unsigned int reg = OUTPUT_VAL;
451 unsigned int mask, val;
453 armada_37xx_update_reg(®, &offset);
455 val = value ? mask : 0;
457 clrsetbits_le32(info->base + reg, mask, val);
462 static int armada_37xx_gpio_get_direction(struct udevice *dev,
465 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
466 unsigned int reg = OUTPUT_EN;
467 unsigned int val, mask;
469 armada_37xx_update_reg(®, &offset);
471 val = readl(info->base + reg);
479 static int armada_37xx_gpio_direction_input(struct udevice *dev,
482 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
483 unsigned int reg = OUTPUT_EN;
486 armada_37xx_update_reg(®, &offset);
489 clrbits_le32(info->base + reg, mask);
494 static int armada_37xx_gpio_direction_output(struct udevice *dev,
495 unsigned int offset, int value)
497 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
498 unsigned int reg = OUTPUT_EN;
501 armada_37xx_update_reg(®, &offset);
504 setbits_le32(info->base + reg, mask);
506 /* And set the requested value */
507 return armada_37xx_gpio_set(dev, offset, value);
510 static int armada_37xx_gpio_probe(struct udevice *dev)
512 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
513 struct gpio_dev_priv *uc_priv;
515 uc_priv = dev_get_uclass_priv(dev);
516 uc_priv->bank_name = info->data->name;
517 uc_priv->gpio_count = info->data->nr_pins;
522 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
523 .set_value = armada_37xx_gpio_set,
524 .get_value = armada_37xx_gpio_get,
525 .get_function = armada_37xx_gpio_get_direction,
526 .direction_input = armada_37xx_gpio_direction_input,
527 .direction_output = armada_37xx_gpio_direction_output,
530 static struct driver armada_37xx_gpio_driver = {
531 .name = "armada-37xx-gpio",
533 .probe = armada_37xx_gpio_probe,
534 .ops = &armada_37xx_gpio_ops,
537 static int armada_37xx_gpiochip_register(struct udevice *parent,
538 struct armada_37xx_pinctrl *info)
540 const void *blob = gd->fdt_blob;
541 int node = dev_of_offset(parent);
542 struct uclass_driver *drv;
548 /* FIXME: Should not need to lookup GPIO uclass */
549 drv = lists_uclass_lookup(UCLASS_GPIO);
551 puts("Cannot find GPIO driver\n");
555 /* FIXME: Use livtree and check the result of device_bind() below */
556 fdt_for_each_subnode(subnode, blob, node) {
557 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
565 name = calloc(1, 32);
566 sprintf(name, "armada-37xx-gpio");
568 /* Create child device UCLASS_GPIO and bind it */
569 device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
570 offset_to_ofnode(subnode), &dev);
575 static const struct pinctrl_ops armada_37xx_pinctrl_ops = {
576 .get_groups_count = armada_37xx_pmx_get_groups_count,
577 .get_group_name = armada_37xx_pmx_get_group_name,
578 .get_functions_count = armada_37xx_pmx_get_funcs_count,
579 .get_function_name = armada_37xx_pmx_get_func_name,
580 .pinmux_group_set = armada_37xx_pmx_group_set,
581 .set_state = pinctrl_generic_set_state,
584 static int armada_37xx_pinctrl_probe(struct udevice *dev)
586 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
587 const struct armada_37xx_pin_data *pin_data;
590 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
591 pin_data = info->data;
593 info->base = dev_read_addr_ptr(dev);
595 pr_err("unable to find regmap\n");
600 * we allocate functions for number of pins and hope there are
601 * fewer unique functions than pins available
603 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
604 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
609 ret = armada_37xx_fill_group(info);
613 ret = armada_37xx_fill_func(info);
617 ret = armada_37xx_gpiochip_register(dev, info);
624 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
626 .compatible = "marvell,armada3710-sb-pinctrl",
627 .data = (ulong)&armada_37xx_pin_sb,
630 .compatible = "marvell,armada3710-nb-pinctrl",
631 .data = (ulong)&armada_37xx_pin_nb,
636 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
637 .name = "armada-37xx-pinctrl",
638 .id = UCLASS_PINCTRL,
639 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
640 .probe = armada_37xx_pinctrl_probe,
641 .priv_auto = sizeof(struct armada_37xx_pinctrl),
642 .ops = &armada_37xx_pinctrl_ops,