2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pin: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @val: Value to write to the registers for a given function
53 * @extra_pin: Index of the first pin of the optional second range of pins
54 * belonging to the group
55 * @extra_npins:Number of pins included in the second optional range
56 * @funcs: A list of pinmux functions that can be selected for this group.
57 * @pins: List of the pins included in the group
59 struct armada_37xx_pin_group {
61 unsigned int start_pin;
65 unsigned int extra_pin;
66 unsigned int extra_npins;
67 const char *funcs[NB_FUNCS];
71 struct armada_37xx_pin_data {
74 struct armada_37xx_pin_group *groups;
78 struct armada_37xx_pmx_func {
84 struct armada_37xx_pm_state {
96 struct armada_37xx_pinctrl {
97 struct regmap *regmap;
99 const struct armada_37xx_pin_data *data;
101 struct gpio_chip gpio_chip;
102 struct irq_chip irq_chip;
104 struct pinctrl_desc pctl;
105 struct pinctrl_dev *pctl_dev;
106 struct armada_37xx_pin_group *groups;
107 unsigned int ngroups;
108 struct armada_37xx_pmx_func *funcs;
110 struct armada_37xx_pm_state pm;
113 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
116 .start_pin = _start, \
120 .funcs = {_func1, _func2} \
123 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
126 .start_pin = _start, \
130 .funcs = {_func1, "gpio"} \
133 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
136 .start_pin = _start, \
139 .val = {_val1, _val2}, \
140 .funcs = {_func1, "gpio"} \
143 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
146 .start_pin = _start, \
149 .val = {_v1, _v2, _v3}, \
150 .funcs = {_f1, _f2, "gpio"} \
153 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
157 .start_pin = _start, \
161 .extra_pin = _start2, \
162 .extra_npins = _nr2, \
163 .funcs = {_f1, _f2} \
166 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
167 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
168 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
169 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
170 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
172 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
174 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
176 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
178 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
179 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
180 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
181 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
182 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
183 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
184 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
185 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
186 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
187 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
188 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
189 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
190 18, 2, "gpio", "uart"),
193 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
194 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
195 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
196 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
197 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
198 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
199 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */
200 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
201 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
202 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
203 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
204 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
205 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
209 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
212 .groups = armada_37xx_nb_groups,
213 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
216 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
219 .groups = armada_37xx_sb_groups,
220 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
223 static inline void armada_37xx_update_reg(unsigned int *reg,
224 unsigned int *offset)
226 /* We never have more than 2 registers */
227 if (*offset >= GPIO_PER_REG) {
228 *offset -= GPIO_PER_REG;
233 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
234 struct armada_37xx_pinctrl *info, int pin, int *grp)
236 while (*grp < info->ngroups) {
237 struct armada_37xx_pin_group *group = &info->groups[*grp];
241 for (j = 0; j < (group->npins + group->extra_npins); j++)
242 if (group->pins[j] == pin)
248 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
249 unsigned int selector, unsigned long *config)
254 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
255 unsigned int selector, unsigned long *configs,
256 unsigned int num_configs)
261 static const struct pinconf_ops armada_37xx_pinconf_ops = {
263 .pin_config_group_get = armada_37xx_pin_config_group_get,
264 .pin_config_group_set = armada_37xx_pin_config_group_set,
267 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
269 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
271 return info->ngroups;
274 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
277 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
279 return info->groups[group].name;
282 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
283 unsigned int selector,
284 const unsigned int **pins,
287 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
289 if (selector >= info->ngroups)
292 *pins = info->groups[selector].pins;
293 *npins = info->groups[selector].npins +
294 info->groups[selector].extra_npins;
299 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
300 .get_groups_count = armada_37xx_get_groups_count,
301 .get_group_name = armada_37xx_get_group_name,
302 .get_group_pins = armada_37xx_get_group_pins,
303 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
304 .dt_free_map = pinctrl_utils_free_map,
308 * Pinmux_ops handling
311 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
313 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
319 unsigned int selector)
321 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
323 return info->funcs[selector].name;
326 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
327 unsigned int selector,
328 const char * const **groups,
329 unsigned int * const num_groups)
331 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
333 *groups = info->funcs[selector].groups;
334 *num_groups = info->funcs[selector].ngroups;
339 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
341 struct armada_37xx_pin_group *grp)
343 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
344 struct device *dev = info->dev;
345 unsigned int reg = SELECTION;
346 unsigned int mask = grp->reg_mask;
349 dev_dbg(dev, "enable function %s group %s\n", name, grp->name);
351 func = match_string(grp->funcs, NB_FUNCS, name);
355 val = grp->val[func];
357 regmap_update_bits(info->regmap, reg, mask, val);
362 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
363 unsigned int selector,
367 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
368 struct armada_37xx_pin_group *grp = &info->groups[group];
369 const char *name = info->funcs[selector].name;
371 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
374 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
377 int offset = irqd_to_hwirq(d);
379 armada_37xx_update_reg(reg, &offset);
382 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
385 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
386 unsigned int reg = OUTPUT_EN;
389 armada_37xx_update_reg(®, &offset);
392 return regmap_update_bits(info->regmap, reg, mask, 0);
395 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
398 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
399 unsigned int reg = OUTPUT_EN;
400 unsigned int val, mask;
402 armada_37xx_update_reg(®, &offset);
404 regmap_read(info->regmap, reg, &val);
407 return GPIO_LINE_DIRECTION_OUT;
409 return GPIO_LINE_DIRECTION_IN;
412 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
413 unsigned int offset, int value)
415 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
416 unsigned int reg = OUTPUT_EN;
417 unsigned int mask, val, ret;
419 armada_37xx_update_reg(®, &offset);
422 ret = regmap_update_bits(info->regmap, reg, mask, mask);
428 val = value ? mask : 0;
429 regmap_update_bits(info->regmap, reg, mask, val);
434 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
436 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
437 unsigned int reg = INPUT_VAL;
438 unsigned int val, mask;
440 armada_37xx_update_reg(®, &offset);
443 regmap_read(info->regmap, reg, &val);
445 return (val & mask) != 0;
448 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
451 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
452 unsigned int reg = OUTPUT_VAL;
453 unsigned int mask, val;
455 armada_37xx_update_reg(®, &offset);
457 val = value ? mask : 0;
459 regmap_update_bits(info->regmap, reg, mask, val);
462 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
463 struct pinctrl_gpio_range *range,
464 unsigned int offset, bool input)
466 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467 struct gpio_chip *chip = range->gc;
469 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
470 offset, range->name, offset, input ? "input" : "output");
473 armada_37xx_gpio_direction_input(chip, offset);
475 armada_37xx_gpio_direction_output(chip, offset, 0);
480 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
481 struct pinctrl_gpio_range *range,
484 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
485 struct armada_37xx_pin_group *group;
488 dev_dbg(info->dev, "requesting gpio %d\n", offset);
490 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
491 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
496 static const struct pinmux_ops armada_37xx_pmx_ops = {
497 .get_functions_count = armada_37xx_pmx_get_funcs_count,
498 .get_function_name = armada_37xx_pmx_get_func_name,
499 .get_function_groups = armada_37xx_pmx_get_groups,
500 .set_mux = armada_37xx_pmx_set,
501 .gpio_request_enable = armada_37xx_gpio_request_enable,
502 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
505 static const struct gpio_chip armada_37xx_gpiolib_chip = {
506 .request = gpiochip_generic_request,
507 .free = gpiochip_generic_free,
508 .set = armada_37xx_gpio_set,
509 .get = armada_37xx_gpio_get,
510 .get_direction = armada_37xx_gpio_get_direction,
511 .direction_input = armada_37xx_gpio_direction_input,
512 .direction_output = armada_37xx_gpio_direction_output,
513 .owner = THIS_MODULE,
516 static void armada_37xx_irq_ack(struct irq_data *d)
518 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
519 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
520 u32 reg = IRQ_STATUS;
523 armada_37xx_irq_update_reg(®, d);
524 spin_lock_irqsave(&info->irq_lock, flags);
525 writel(d->mask, info->base + reg);
526 spin_unlock_irqrestore(&info->irq_lock, flags);
529 static void armada_37xx_irq_mask(struct irq_data *d)
531 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
532 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
533 u32 val, reg = IRQ_EN;
536 armada_37xx_irq_update_reg(®, d);
537 spin_lock_irqsave(&info->irq_lock, flags);
538 val = readl(info->base + reg);
539 writel(val & ~d->mask, info->base + reg);
540 spin_unlock_irqrestore(&info->irq_lock, flags);
543 static void armada_37xx_irq_unmask(struct irq_data *d)
545 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
546 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
547 u32 val, reg = IRQ_EN;
550 armada_37xx_irq_update_reg(®, d);
551 spin_lock_irqsave(&info->irq_lock, flags);
552 val = readl(info->base + reg);
553 writel(val | d->mask, info->base + reg);
554 spin_unlock_irqrestore(&info->irq_lock, flags);
557 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
559 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
560 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
561 u32 val, reg = IRQ_WKUP;
564 armada_37xx_irq_update_reg(®, d);
565 spin_lock_irqsave(&info->irq_lock, flags);
566 val = readl(info->base + reg);
568 val |= (BIT(d->hwirq % GPIO_PER_REG));
570 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
571 writel(val, info->base + reg);
572 spin_unlock_irqrestore(&info->irq_lock, flags);
577 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
579 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
580 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
581 u32 val, reg = IRQ_POL;
584 spin_lock_irqsave(&info->irq_lock, flags);
585 armada_37xx_irq_update_reg(®, d);
586 val = readl(info->base + reg);
588 case IRQ_TYPE_EDGE_RISING:
589 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
591 case IRQ_TYPE_EDGE_FALLING:
592 val |= (BIT(d->hwirq % GPIO_PER_REG));
594 case IRQ_TYPE_EDGE_BOTH: {
595 u32 in_val, in_reg = INPUT_VAL;
597 armada_37xx_irq_update_reg(&in_reg, d);
598 regmap_read(info->regmap, in_reg, &in_val);
600 /* Set initial polarity based on current input level. */
601 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
602 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
604 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
608 spin_unlock_irqrestore(&info->irq_lock, flags);
611 writel(val, info->base + reg);
612 spin_unlock_irqrestore(&info->irq_lock, flags);
617 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
620 u32 reg_idx = pin_idx / GPIO_PER_REG;
621 u32 bit_num = pin_idx % GPIO_PER_REG;
625 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
627 spin_lock_irqsave(&info->irq_lock, flags);
628 p = readl(info->base + IRQ_POL + 4 * reg_idx);
629 if ((p ^ l) & (1 << bit_num)) {
631 * For the gpios which are used for both-edge irqs, when their
632 * interrupts happen, their input levels are changed,
633 * yet their interrupt polarities are kept in old values, we
634 * should synchronize their interrupt polarities; for example,
635 * at first a gpio's input level is low and its interrupt
636 * polarity control is "Detect rising edge", then the gpio has
637 * a interrupt , its level turns to high, we should change its
638 * polarity control to "Detect falling edge" correspondingly.
641 writel(p, info->base + IRQ_POL + 4 * reg_idx);
648 spin_unlock_irqrestore(&info->irq_lock, flags);
652 static void armada_37xx_irq_handler(struct irq_desc *desc)
654 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
655 struct irq_chip *chip = irq_desc_get_chip(desc);
656 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
657 struct irq_domain *d = gc->irq.domain;
660 chained_irq_enter(chip, desc);
661 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
665 spin_lock_irqsave(&info->irq_lock, flags);
666 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
667 /* Manage only the interrupt that was enabled */
668 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
669 spin_unlock_irqrestore(&info->irq_lock, flags);
671 u32 hwirq = ffs(status) - 1;
672 u32 virq = irq_find_mapping(d, hwirq +
674 u32 t = irq_get_trigger_type(virq);
676 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
677 /* Swap polarity (race with GPIO line) */
678 if (armada_37xx_edge_both_irq_swap_pol(info,
679 hwirq + i * GPIO_PER_REG)) {
681 * For spurious irq, which gpio level
682 * is not as expected after incoming
683 * edge, just ack the gpio irq.
692 generic_handle_irq(virq);
695 /* Update status in case a new IRQ appears */
696 spin_lock_irqsave(&info->irq_lock, flags);
697 status = readl_relaxed(info->base +
699 /* Manage only the interrupt that was enabled */
700 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
701 spin_unlock_irqrestore(&info->irq_lock, flags);
704 chained_irq_exit(chip, desc);
707 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
710 * The mask field is a "precomputed bitmask for accessing the
711 * chip registers" which was introduced for the generic
712 * irqchip framework. As we don't use this framework, we can
713 * reuse this field for our own usage.
715 d->mask = BIT(d->hwirq % GPIO_PER_REG);
717 armada_37xx_irq_unmask(d);
722 static int armada_37xx_irqchip_register(struct platform_device *pdev,
723 struct armada_37xx_pinctrl *info)
725 struct gpio_chip *gc = &info->gpio_chip;
726 struct irq_chip *irqchip = &info->irq_chip;
727 struct gpio_irq_chip *girq = &gc->irq;
728 struct device *dev = &pdev->dev;
729 struct device_node *np;
730 int ret = -ENODEV, i, nr_irq_parent;
732 /* Check if we have at least one gpio-controller child node */
733 for_each_child_of_node(dev->of_node, np) {
734 if (of_property_read_bool(np, "gpio-controller")) {
740 return dev_err_probe(dev, ret, "no gpio-controller child node\n");
742 nr_irq_parent = of_irq_count(np);
743 spin_lock_init(&info->irq_lock);
745 if (!nr_irq_parent) {
746 dev_err(dev, "invalid or no IRQ\n");
750 info->base = devm_platform_ioremap_resource(pdev, 1);
751 if (IS_ERR(info->base))
752 return PTR_ERR(info->base);
754 irqchip->irq_ack = armada_37xx_irq_ack;
755 irqchip->irq_mask = armada_37xx_irq_mask;
756 irqchip->irq_unmask = armada_37xx_irq_unmask;
757 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
758 irqchip->irq_set_type = armada_37xx_irq_set_type;
759 irqchip->irq_startup = armada_37xx_irq_startup;
760 irqchip->name = info->data->name;
761 girq->chip = irqchip;
762 girq->parent_handler = armada_37xx_irq_handler;
764 * Many interrupts are connected to the parent interrupt
765 * controller. But we do not take advantage of this and use
766 * the chained irq with all of them.
768 girq->num_parents = nr_irq_parent;
769 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL);
772 for (i = 0; i < nr_irq_parent; i++) {
773 int irq = irq_of_parse_and_map(np, i);
777 girq->parents[i] = irq;
779 girq->default_type = IRQ_TYPE_NONE;
780 girq->handler = handle_edge_irq;
785 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
786 struct armada_37xx_pinctrl *info)
788 struct device *dev = &pdev->dev;
789 struct device_node *np;
790 struct gpio_chip *gc;
793 for_each_child_of_node(dev->of_node, np) {
794 if (of_find_property(np, "gpio-controller", NULL)) {
802 info->gpio_chip = armada_37xx_gpiolib_chip;
804 gc = &info->gpio_chip;
805 gc->ngpio = info->data->nr_pins;
809 gc->label = info->data->name;
811 ret = armada_37xx_irqchip_register(pdev, info);
815 return devm_gpiochip_add_data(dev, gc, info);
819 * armada_37xx_add_function() - Add a new function to the list
820 * @funcs: array of function to add the new one
821 * @funcsize: size of the remaining space for the function
822 * @name: name of the function to add
824 * If it is a new function then create it by adding its name else
825 * increment the number of group associated to this function.
827 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
828 int *funcsize, const char *name)
835 while (funcs->ngroups) {
836 /* function already there */
837 if (strcmp(funcs->name, name) == 0) {
846 /* append new unique function */
855 * armada_37xx_fill_group() - complete the group array
856 * @info: info driver instance
858 * Based on the data available from the armada_37xx_pin_group array
859 * completes the last member of the struct for each function: the list
860 * of the groups associated to this function.
863 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
865 int n, num = 0, funcsize = info->data->nr_pins;
866 struct device *dev = info->dev;
868 for (n = 0; n < info->ngroups; n++) {
869 struct armada_37xx_pin_group *grp = &info->groups[n];
872 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins,
878 for (i = 0; i < grp->npins; i++)
879 grp->pins[i] = grp->start_pin + i;
881 for (j = 0; j < grp->extra_npins; j++)
882 grp->pins[i+j] = grp->extra_pin + j;
884 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
886 /* check for unique functions and count groups */
887 ret = armada_37xx_add_function(info->funcs, &funcsize,
889 if (ret == -EOVERFLOW)
890 dev_err(dev, "More functions than pins(%d)\n",
891 info->data->nr_pins);
904 * armada_37xx_fill_funcs() - complete the funcs array
905 * @info: info driver instance
907 * Based on the data available from the armada_37xx_pin_group array
908 * completes the last two member of the struct for each group:
909 * - the list of the pins included in the group
910 * - the list of pinmux functions that can be selected for this group
913 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
915 struct armada_37xx_pmx_func *funcs = info->funcs;
916 struct device *dev = info->dev;
919 for (n = 0; n < info->nfuncs; n++) {
920 const char *name = funcs[n].name;
924 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups,
925 sizeof(*(funcs[n].groups)),
927 if (!funcs[n].groups)
930 groups = funcs[n].groups;
932 for (g = 0; g < info->ngroups; g++) {
933 struct armada_37xx_pin_group *gp = &info->groups[g];
936 f = match_string(gp->funcs, NB_FUNCS, name);
947 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
948 struct armada_37xx_pinctrl *info)
950 const struct armada_37xx_pin_data *pin_data = info->data;
951 struct pinctrl_desc *ctrldesc = &info->pctl;
952 struct pinctrl_pin_desc *pindesc, *pdesc;
953 struct device *dev = &pdev->dev;
956 info->groups = pin_data->groups;
957 info->ngroups = pin_data->ngroups;
959 ctrldesc->name = "armada_37xx-pinctrl";
960 ctrldesc->owner = THIS_MODULE;
961 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
962 ctrldesc->pmxops = &armada_37xx_pmx_ops;
963 ctrldesc->confops = &armada_37xx_pinconf_ops;
965 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL);
969 ctrldesc->pins = pindesc;
970 ctrldesc->npins = pin_data->nr_pins;
973 for (pin = 0; pin < pin_data->nr_pins; pin++) {
975 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
976 pin_data->name, pin);
981 * we allocate functions for number of pins and hope there are
982 * fewer unique functions than pins available
984 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL);
988 ret = armada_37xx_fill_group(info);
992 ret = armada_37xx_fill_func(info);
996 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info);
997 if (IS_ERR(info->pctl_dev))
998 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n");
1003 #if defined(CONFIG_PM)
1004 static int armada_3700_pinctrl_suspend(struct device *dev)
1006 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1008 /* Save GPIO state */
1009 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1010 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1011 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1012 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1013 &info->pm.out_val_h);
1015 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1016 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1017 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1018 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1020 /* Save pinctrl state */
1021 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1026 static int armada_3700_pinctrl_resume(struct device *dev)
1028 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1029 struct gpio_chip *gc;
1030 struct irq_domain *d;
1033 /* Restore GPIO state */
1034 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1035 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1037 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1038 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1039 info->pm.out_val_h);
1042 * Input levels may change during suspend, which is not monitored at
1043 * that time. GPIOs used for both-edge IRQs may not be synchronized
1044 * anymore with their polarities (rising/falling edge) and must be
1045 * re-configured manually.
1047 gc = &info->gpio_chip;
1049 for (i = 0; i < gc->ngpio; i++) {
1050 u32 irq_bit = BIT(i % GPIO_PER_REG);
1051 u32 mask, *irq_pol, input_reg, virq, type, level;
1053 if (i < GPIO_PER_REG) {
1054 mask = info->pm.irq_en_l;
1055 irq_pol = &info->pm.irq_pol_l;
1056 input_reg = INPUT_VAL;
1058 mask = info->pm.irq_en_h;
1059 irq_pol = &info->pm.irq_pol_h;
1060 input_reg = INPUT_VAL + sizeof(u32);
1063 if (!(mask & irq_bit))
1066 virq = irq_find_mapping(d, i);
1067 type = irq_get_trigger_type(virq);
1070 * Synchronize level and polarity for both-edge irqs:
1071 * - a high input level expects a falling edge,
1072 * - a low input level exepects a rising edge.
1074 if ((type & IRQ_TYPE_SENSE_MASK) ==
1075 IRQ_TYPE_EDGE_BOTH) {
1076 regmap_read(info->regmap, input_reg, &level);
1077 if ((*irq_pol ^ level) & irq_bit)
1078 *irq_pol ^= irq_bit;
1082 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1083 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1084 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1085 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1087 /* Restore pinctrl state */
1088 regmap_write(info->regmap, SELECTION, info->pm.selection);
1094 * Since pinctrl is an infrastructure module, its resume should be issued prior
1095 * to other IO drivers.
1097 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1098 .suspend_noirq = armada_3700_pinctrl_suspend,
1099 .resume_noirq = armada_3700_pinctrl_resume,
1102 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1104 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1105 #endif /* CONFIG_PM */
1107 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1109 .compatible = "marvell,armada3710-sb-pinctrl",
1110 .data = &armada_37xx_pin_sb,
1113 .compatible = "marvell,armada3710-nb-pinctrl",
1114 .data = &armada_37xx_pin_nb,
1119 static const struct regmap_config armada_37xx_pinctrl_regmap_config = {
1123 .use_raw_spinlock = true,
1126 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1128 struct armada_37xx_pinctrl *info;
1129 struct device *dev = &pdev->dev;
1130 struct regmap *regmap;
1134 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1136 dev_err(dev, "failed to ioremap base address: %pe\n", base);
1137 return PTR_ERR(base);
1140 regmap = devm_regmap_init_mmio(dev, base,
1141 &armada_37xx_pinctrl_regmap_config);
1142 if (IS_ERR(regmap)) {
1143 dev_err(dev, "failed to create regmap: %pe\n", regmap);
1144 return PTR_ERR(regmap);
1147 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1152 info->regmap = regmap;
1153 info->data = of_device_get_match_data(dev);
1155 ret = armada_37xx_pinctrl_register(pdev, info);
1159 ret = armada_37xx_gpiochip_register(pdev, info);
1163 platform_set_drvdata(pdev, info);
1168 static struct platform_driver armada_37xx_pinctrl_driver = {
1170 .name = "armada-37xx-pinctrl",
1171 .of_match_table = armada_37xx_pinctrl_of_match,
1172 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1176 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1177 armada_37xx_pinctrl_probe);