1 // SPDX-License-Identifier: GPL-2.0+
3 * U-Boot Marvell 37xx SoC pinctrl driver
5 * Copyright (C) 2017 Stefan Roese <sr@denx.de>
7 * This driver is based on the Linux driver version, which is:
8 * Copyright (C) 2017 Marvell
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 * Additionally parts are derived from the Meson U-Boot pinctrl driver,
13 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
14 * Based on code from Linux kernel:
15 * Copyright (C) 2016 Endless Mobile, Inc.
16 * https://spdx.org/licenses
23 #include <asm/global_data.h>
24 #include <dm/device-internal.h>
25 #include <dm/device_compat.h>
26 #include <dm/devres.h>
28 #include <dm/pinctrl.h>
34 #include <asm/system.h>
36 #include <linux/bitops.h>
37 #include <linux/libfdt.h>
39 DECLARE_GLOBAL_DATA_PTR;
42 #define INPUT_VAL 0x10
43 #define OUTPUT_VAL 0x18
44 #define OUTPUT_CTL 0x20
45 #define SELECTION 0x30
49 #define IRQ_STATUS 0x10
53 #define GPIO_PER_REG 32
56 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
57 * The pins of a pinmux groups are composed of one or two groups of contiguous
59 * @name: Name of the pin group, used to lookup the group.
60 * @start_pins: Index of the first pin of the main range of pins belonging to
62 * @npins: Number of pins included in the first range
63 * @reg_mask: Bit mask matching the group in the selection register
64 * @extra_pins: Index of the first pin of the optional second range of pins
65 * belonging to the group
66 * @npins: Number of pins included in the second optional range
67 * @funcs: A list of pinmux functions that can be selected for this group.
68 * @pins: List of the pins included in the group
70 struct armada_37xx_pin_group {
72 unsigned int start_pin;
76 unsigned int extra_pin;
77 unsigned int extra_npins;
78 const char *funcs[NB_FUNCS];
82 struct armada_37xx_pin_data {
85 struct armada_37xx_pin_group *groups;
89 struct armada_37xx_pmx_func {
95 struct armada_37xx_pinctrl {
97 const struct armada_37xx_pin_data *data;
99 struct pinctrl_dev *pctl_dev;
100 struct armada_37xx_pin_group *groups;
101 unsigned int ngroups;
102 struct armada_37xx_pmx_func *funcs;
106 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
109 .start_pin = _start, \
113 .funcs = {_func1, _func2} \
116 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
119 .start_pin = _start, \
123 .funcs = {_func1, "gpio"} \
126 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
129 .start_pin = _start, \
132 .val = {_val1, _val2}, \
133 .funcs = {_func1, "gpio"} \
136 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
139 .start_pin = _start, \
142 .val = {_v1, _v2, _v3}, \
143 .funcs = {_f1, _f2, "gpio"} \
146 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
150 .start_pin = _start, \
154 .extra_pin = _start2, \
155 .extra_npins = _nr2, \
156 .funcs = {_f1, _f2} \
159 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
160 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
161 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
162 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
163 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3),
165 PIN_GRP_GPIO_3("pwm1", 11, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4),
167 PIN_GRP_GPIO_3("pwm2", 11, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5),
169 PIN_GRP_GPIO_3("pwm3", 11, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6),
171 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
172 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
173 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
174 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
175 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
176 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
177 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
178 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
179 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
180 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
181 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
182 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
183 18, 2, "gpio", "uart"),
186 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
187 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
188 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
189 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
190 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
191 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
192 PIN_GRP_GPIO("pcie1", 3, 3, BIT(5) | BIT(9) | BIT(10), "pcie"),
193 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
194 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
195 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
196 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
200 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
203 .groups = armada_37xx_nb_groups,
204 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
207 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
210 .groups = armada_37xx_sb_groups,
211 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
214 static inline void armada_37xx_update_reg(unsigned int *reg,
215 unsigned int *offset)
217 /* We never have more than 2 registers */
218 if (*offset >= GPIO_PER_REG) {
219 *offset -= GPIO_PER_REG;
224 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
229 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++)
230 if (!strcmp(grp->funcs[f], func))
236 static int armada_37xx_pmx_get_groups_count(struct udevice *dev)
238 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
240 return info->ngroups;
243 static const char *armada_37xx_pmx_dummy_name = "_dummy";
245 static const char *armada_37xx_pmx_get_group_name(struct udevice *dev,
248 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
250 if (!info->groups[selector].name)
251 return armada_37xx_pmx_dummy_name;
253 return info->groups[selector].name;
256 static int armada_37xx_pmx_get_funcs_count(struct udevice *dev)
258 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
263 static const char *armada_37xx_pmx_get_func_name(struct udevice *dev,
266 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
268 return info->funcs[selector].name;
271 static int armada_37xx_pmx_set_by_name(struct udevice *dev,
273 struct armada_37xx_pin_group *grp)
275 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
276 unsigned int reg = SELECTION;
277 unsigned int mask = grp->reg_mask;
280 dev_dbg(info->dev, "enable function %s group %s\n",
283 func = armada_37xx_get_func_reg(grp, name);
288 val = grp->val[func];
290 clrsetbits_le32(info->base + reg, mask, val);
295 static int armada_37xx_pmx_group_set(struct udevice *dev,
296 unsigned group_selector,
297 unsigned func_selector)
299 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
300 struct armada_37xx_pin_group *grp = &info->groups[group_selector];
301 const char *name = info->funcs[func_selector].name;
303 return armada_37xx_pmx_set_by_name(dev, name, grp);
307 * armada_37xx_add_function() - Add a new function to the list
308 * @funcs: array of function to add the new one
309 * @funcsize: size of the remaining space for the function
310 * @name: name of the function to add
312 * If it is a new function then create it by adding its name else
313 * increment the number of group associated to this function.
315 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
316 int *funcsize, const char *name)
323 while (funcs->ngroups) {
324 /* function already there */
325 if (strcmp(funcs->name, name) == 0) {
334 /* append new unique function */
343 * armada_37xx_fill_group() - complete the group array
344 * @info: info driver instance
346 * Based on the data available from the armada_37xx_pin_group array
347 * completes the last member of the struct for each function: the list
348 * of the groups associated to this function.
351 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
353 int n, num = 0, funcsize = info->data->nr_pins;
355 for (n = 0; n < info->ngroups; n++) {
356 struct armada_37xx_pin_group *grp = &info->groups[n];
359 grp->pins = devm_kzalloc(info->dev,
360 (grp->npins + grp->extra_npins) *
361 sizeof(*grp->pins), GFP_KERNEL);
365 for (i = 0; i < grp->npins; i++)
366 grp->pins[i] = grp->start_pin + i;
368 for (j = 0; j < grp->extra_npins; j++)
369 grp->pins[i+j] = grp->extra_pin + j;
371 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
373 /* check for unique functions and count groups */
374 ret = armada_37xx_add_function(info->funcs, &funcsize,
376 if (ret == -EOVERFLOW)
378 "More functions than pins(%d)\n",
379 info->data->nr_pins);
392 * armada_37xx_fill_funcs() - complete the funcs array
393 * @info: info driver instance
395 * Based on the data available from the armada_37xx_pin_group array
396 * completes the last two member of the struct for each group:
397 * - the list of the pins included in the group
398 * - the list of pinmux functions that can be selected for this group
401 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
403 struct armada_37xx_pmx_func *funcs = info->funcs;
406 for (n = 0; n < info->nfuncs; n++) {
407 const char *name = funcs[n].name;
411 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
412 sizeof(*(funcs[n].groups)),
414 if (!funcs[n].groups)
417 groups = funcs[n].groups;
419 for (g = 0; g < info->ngroups; g++) {
420 struct armada_37xx_pin_group *gp = &info->groups[g];
423 for (f = 0; (f < NB_FUNCS) && gp->funcs[f]; f++) {
424 if (strcmp(gp->funcs[f], name) == 0) {
434 static int armada_37xx_gpio_get(struct udevice *dev, unsigned int offset)
436 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
437 unsigned int reg = INPUT_VAL;
438 unsigned int val, mask;
440 armada_37xx_update_reg(®, &offset);
443 val = readl(info->base + reg);
445 return (val & mask) != 0;
448 static int armada_37xx_gpio_set(struct udevice *dev, unsigned int offset,
451 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
452 unsigned int reg = OUTPUT_VAL;
453 unsigned int mask, val;
455 armada_37xx_update_reg(®, &offset);
457 val = value ? mask : 0;
459 clrsetbits_le32(info->base + reg, mask, val);
464 static int armada_37xx_gpio_get_direction(struct udevice *dev,
467 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
468 unsigned int reg = OUTPUT_EN;
469 unsigned int val, mask;
471 armada_37xx_update_reg(®, &offset);
473 val = readl(info->base + reg);
481 static int armada_37xx_gpio_direction_input(struct udevice *dev,
484 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
485 unsigned int reg = OUTPUT_EN;
488 armada_37xx_update_reg(®, &offset);
491 clrbits_le32(info->base + reg, mask);
496 static int armada_37xx_gpio_direction_output(struct udevice *dev,
497 unsigned int offset, int value)
499 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
500 unsigned int reg = OUTPUT_EN;
503 armada_37xx_update_reg(®, &offset);
506 setbits_le32(info->base + reg, mask);
508 /* And set the requested value */
509 return armada_37xx_gpio_set(dev, offset, value);
512 static int armada_37xx_gpio_probe(struct udevice *dev)
514 struct armada_37xx_pinctrl *info = dev_get_priv(dev->parent);
515 struct gpio_dev_priv *uc_priv;
517 uc_priv = dev_get_uclass_priv(dev);
518 uc_priv->bank_name = info->data->name;
519 uc_priv->gpio_count = info->data->nr_pins;
524 static const struct dm_gpio_ops armada_37xx_gpio_ops = {
525 .set_value = armada_37xx_gpio_set,
526 .get_value = armada_37xx_gpio_get,
527 .get_function = armada_37xx_gpio_get_direction,
528 .direction_input = armada_37xx_gpio_direction_input,
529 .direction_output = armada_37xx_gpio_direction_output,
532 static struct driver armada_37xx_gpio_driver = {
533 .name = "armada-37xx-gpio",
535 .probe = armada_37xx_gpio_probe,
536 .ops = &armada_37xx_gpio_ops,
539 static int armada_37xx_gpiochip_register(struct udevice *parent,
540 struct armada_37xx_pinctrl *info)
542 const void *blob = gd->fdt_blob;
543 int node = dev_of_offset(parent);
544 struct uclass_driver *drv;
550 /* FIXME: Should not need to lookup GPIO uclass */
551 drv = lists_uclass_lookup(UCLASS_GPIO);
553 puts("Cannot find GPIO driver\n");
557 /* FIXME: Use livtree and check the result of device_bind() below */
558 fdt_for_each_subnode(subnode, blob, node) {
559 if (fdtdec_get_bool(blob, subnode, "gpio-controller")) {
567 name = calloc(1, 32);
568 sprintf(name, "armada-37xx-gpio");
570 /* Create child device UCLASS_GPIO and bind it */
571 device_bind(parent, &armada_37xx_gpio_driver, name, NULL,
572 offset_to_ofnode(subnode), &dev);
577 const struct pinctrl_ops armada_37xx_pinctrl_ops = {
578 .get_groups_count = armada_37xx_pmx_get_groups_count,
579 .get_group_name = armada_37xx_pmx_get_group_name,
580 .get_functions_count = armada_37xx_pmx_get_funcs_count,
581 .get_function_name = armada_37xx_pmx_get_func_name,
582 .pinmux_group_set = armada_37xx_pmx_group_set,
583 .set_state = pinctrl_generic_set_state,
586 int armada_37xx_pinctrl_probe(struct udevice *dev)
588 struct armada_37xx_pinctrl *info = dev_get_priv(dev);
589 const struct armada_37xx_pin_data *pin_data;
592 info->data = (struct armada_37xx_pin_data *)dev_get_driver_data(dev);
593 pin_data = info->data;
595 info->base = dev_read_addr_ptr(dev);
597 pr_err("unable to find regmap\n");
601 info->groups = pin_data->groups;
602 info->ngroups = pin_data->ngroups;
605 * we allocate functions for number of pins and hope there are
606 * fewer unique functions than pins available
608 info->funcs = devm_kzalloc(info->dev, pin_data->nr_pins *
609 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
614 ret = armada_37xx_fill_group(info);
618 ret = armada_37xx_fill_func(info);
622 ret = armada_37xx_gpiochip_register(dev, info);
629 static const struct udevice_id armada_37xx_pinctrl_of_match[] = {
631 .compatible = "marvell,armada3710-sb-pinctrl",
632 .data = (ulong)&armada_37xx_pin_sb,
635 .compatible = "marvell,armada3710-nb-pinctrl",
636 .data = (ulong)&armada_37xx_pin_nb,
641 U_BOOT_DRIVER(armada_37xx_pinctrl) = {
642 .name = "armada-37xx-pinctrl",
643 .id = UCLASS_PINCTRL,
644 .of_match = of_match_ptr(armada_37xx_pinctrl_of_match),
645 .probe = armada_37xx_pinctrl_probe,
646 .priv_auto = sizeof(struct armada_37xx_pinctrl),
647 .ops = &armada_37xx_pinctrl_ops,