1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Microsemi SoCs pinctrl driver
5 * Author: <horatiu.vultur@microchip.com>
6 * Copyright (c) 2018 Microsemi Corporation
12 #include <dm/device-internal.h>
14 #include <dm/pinctrl.h>
20 #include <asm/system.h>
21 #include "mscc-common.h"
69 static char * const jr2_function_names[] = {
72 [FUNC_IRQ0_IN] = "irq0_in",
73 [FUNC_IRQ0_OUT] = "irq0_out",
74 [FUNC_IRQ1_IN] = "irq1_in",
75 [FUNC_IRQ1_OUT] = "irq1_out",
76 [FUNC_MIIM1] = "miim1",
77 [FUNC_MIIM2] = "miim2",
78 [FUNC_PCI_WAKE] = "pci_wake",
84 [FUNC_RECO_CLK0] = "reco_clk0",
85 [FUNC_RECO_CLK1] = "reco_clk1",
96 [FUNC_SFP10] = "sfp10",
97 [FUNC_SFP11] = "sfp11",
98 [FUNC_SFP12] = "sfp12",
99 [FUNC_SFP13] = "sfp13",
100 [FUNC_SFP14] = "sfp14",
101 [FUNC_SFP15] = "sfp15",
106 [FUNC_TACHO] = "tacho",
108 [FUNC_TWI2] = "twi2",
109 [FUNC_TWI_SCL_M] = "twi_scl_m",
110 [FUNC_UART] = "uart",
111 [FUNC_UART2] = "uart2",
114 #define JR2_P(p, f0, f1) \
115 static struct mscc_pin_caps jr2_pin_##p = { \
118 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
128 JR2_P(6, IRQ0_IN, IRQ0_OUT);
129 JR2_P(7, IRQ1_IN, IRQ1_OUT);
130 JR2_P(8, PTP0, NONE);
131 JR2_P(9, PTP1, NONE);
132 JR2_P(10, UART, NONE);
133 JR2_P(11, UART, NONE);
134 JR2_P(12, SG1, NONE);
135 JR2_P(13, SG1, NONE);
136 JR2_P(14, TWI, TWI_SCL_M);
137 JR2_P(15, TWI, NONE);
138 JR2_P(16, SI, TWI_SCL_M);
139 JR2_P(17, SI, TWI_SCL_M);
140 JR2_P(18, SI, TWI_SCL_M);
141 JR2_P(19, PCI_WAKE, NONE);
142 JR2_P(20, IRQ0_OUT, TWI_SCL_M);
143 JR2_P(21, IRQ1_OUT, TWI_SCL_M);
144 JR2_P(22, TACHO, NONE);
145 JR2_P(23, PWM, NONE);
146 JR2_P(24, UART2, NONE);
147 JR2_P(25, UART2, SI);
156 JR2_P(34, NONE, TWI_SCL_M);
157 JR2_P(35, NONE, TWI_SCL_M);
158 JR2_P(36, NONE, TWI_SCL_M);
159 JR2_P(37, NONE, TWI_SCL_M);
160 JR2_P(38, NONE, TWI_SCL_M);
161 JR2_P(39, NONE, TWI_SCL_M);
162 JR2_P(40, NONE, TWI_SCL_M);
163 JR2_P(41, NONE, TWI_SCL_M);
164 JR2_P(42, NONE, TWI_SCL_M);
165 JR2_P(43, NONE, TWI_SCL_M);
166 JR2_P(44, NONE, SFP8);
167 JR2_P(45, NONE, SFP9);
168 JR2_P(46, NONE, SFP10);
169 JR2_P(47, NONE, SFP11);
170 JR2_P(48, SFP0, NONE);
174 JR2_P(52, SFP4, NONE);
175 JR2_P(53, SFP5, NONE);
176 JR2_P(54, SFP6, NONE);
177 JR2_P(55, SFP7, NONE);
178 JR2_P(56, MIIM1, SFP12);
179 JR2_P(57, MIIM1, SFP13);
180 JR2_P(58, MIIM2, SFP14);
181 JR2_P(59, MIIM2, SFP15);
182 JR2_P(60, NONE, NONE);
183 JR2_P(61, NONE, NONE);
184 JR2_P(62, NONE, NONE);
185 JR2_P(63, NONE, NONE);
187 #define JR2_PIN(n) { \
189 .drv_data = &jr2_pin_##n \
192 static const struct mscc_pin_data jr2_pins[] = {
259 static const unsigned long jr2_gpios[] = {
260 [MSCC_GPIO_OUT_SET] = 0x00,
261 [MSCC_GPIO_OUT_CLR] = 0x08,
262 [MSCC_GPIO_OUT] = 0x10,
263 [MSCC_GPIO_IN] = 0x18,
264 [MSCC_GPIO_OE] = 0x20,
265 [MSCC_GPIO_INTR] = 0x28,
266 [MSCC_GPIO_INTR_ENA] = 0x30,
267 [MSCC_GPIO_INTR_IDENT] = 0x38,
268 [MSCC_GPIO_ALT0] = 0x40,
269 [MSCC_GPIO_ALT1] = 0x48,
272 static int jr2_gpio_probe(struct udevice *dev)
274 struct gpio_dev_priv *uc_priv;
276 uc_priv = dev_get_uclass_priv(dev);
277 uc_priv->bank_name = "jr2-gpio";
278 uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
283 static struct driver jr2_gpio_driver = {
286 .probe = jr2_gpio_probe,
287 .ops = &mscc_gpio_ops,
290 static int jr2_pinctrl_probe(struct udevice *dev)
294 ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
295 ARRAY_SIZE(jr2_pins),
302 ret = device_bind(dev, &jr2_gpio_driver, "jr2-gpio", NULL,
303 dev_ofnode(dev), NULL);
311 static const struct udevice_id jr2_pinctrl_of_match[] = {
312 { .compatible = "mscc,jaguar2-pinctrl" },
316 U_BOOT_DRIVER(jr2_pinctrl) = {
317 .name = "jr2-pinctrl",
318 .id = UCLASS_PINCTRL,
319 .of_match = of_match_ptr(jr2_pinctrl_of_match),
320 .probe = jr2_pinctrl_probe,
321 .priv_auto = sizeof(struct mscc_pinctrl),
322 .ops = &mscc_pinctrl_ops,