1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
9 #include <dm/device-internal.h>
11 #include <dm/pinctrl.h>
13 #include <asm-generic/gpio.h>
15 #include "pinctrl-mtk-common.h"
18 * struct mtk_drive_desc - the structure that holds the information
19 * of the driving current
20 * @min: the minimum current of this group
21 * @max: the maximum current of this group
22 * @step: the step current of this group
23 * @scal: the weight factor
25 * formula: output = ((input) / step - 1) * scal
27 struct mtk_drive_desc {
34 /* The groups of drive strength */
35 static const struct mtk_drive_desc mtk_drive[] = {
36 [DRV_GRP0] = { 4, 16, 4, 1 },
37 [DRV_GRP1] = { 4, 16, 4, 2 },
38 [DRV_GRP2] = { 2, 8, 2, 1 },
39 [DRV_GRP3] = { 2, 8, 2, 2 },
40 [DRV_GRP4] = { 2, 16, 2, 1 },
43 static const char *mtk_pinctrl_dummy_name = "_dummy";
45 static void mtk_w32(struct udevice *dev, u32 reg, u32 val)
47 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
49 __raw_writel(val, priv->base + reg);
52 static u32 mtk_r32(struct udevice *dev, u32 reg)
54 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
56 return __raw_readl(priv->base + reg);
59 static inline int get_count_order(unsigned int count)
63 order = fls(count) - 1;
64 if (count & (count - 1))
69 void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
73 val = mtk_r32(dev, reg);
76 mtk_w32(dev, reg, val);
79 static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
80 const struct mtk_pin_reg_calc *rc,
81 struct mtk_pin_field *pfd)
83 const struct mtk_pin_field_calc *c, *e;
90 if (pin >= c->s_pin && pin <= c->e_pin)
98 /* Calculated bits as the overall offset the pin is located at,
99 * if c->fixed is held, that determines the all the pins in the
100 * range use the same field with the s_pin.
102 bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
104 /* Fill pfd from bits. For example 32-bit register applied is assumed
105 * when c->sz_reg is equal to 32.
107 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
108 pfd->bitpos = bits % c->sz_reg;
109 pfd->mask = (1 << c->x_bits) - 1;
111 /* pfd->next is used for indicating that bit wrapping-around happens
112 * which requires the manipulation for bit 0 starting in the next
113 * register to form the complete field read/write.
115 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
120 static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
121 int field, struct mtk_pin_field *pfd)
123 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
124 const struct mtk_pin_reg_calc *rc;
126 if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
129 if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
130 rc = &priv->soc->reg_cal[field];
134 return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
137 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
139 *l = 32 - pf->bitpos;
140 *h = get_count_order(pf->mask) - *l;
143 static void mtk_hw_write_cross_field(struct udevice *dev,
144 struct mtk_pin_field *pf, int value)
146 int nbits_l, nbits_h;
148 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
150 mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,
151 (value & pf->mask) << pf->bitpos);
153 mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,
154 (value & pf->mask) >> nbits_l);
157 static void mtk_hw_read_cross_field(struct udevice *dev,
158 struct mtk_pin_field *pf, int *value)
160 int nbits_l, nbits_h, h, l;
162 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
164 l = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
165 h = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
167 *value = (h << nbits_l) | l;
170 static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
173 struct mtk_pin_field pf;
176 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
181 mtk_rmw(dev, pf.offset, pf.mask << pf.bitpos,
182 (value & pf.mask) << pf.bitpos);
184 mtk_hw_write_cross_field(dev, &pf, value);
189 static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
192 struct mtk_pin_field pf;
195 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
200 *value = (mtk_r32(dev, pf.offset) >> pf.bitpos) & pf.mask;
202 mtk_hw_read_cross_field(dev, &pf, value);
207 static int mtk_get_groups_count(struct udevice *dev)
209 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
211 return priv->soc->ngrps;
214 static const char *mtk_get_pin_name(struct udevice *dev,
215 unsigned int selector)
217 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
219 if (!priv->soc->grps[selector].name)
220 return mtk_pinctrl_dummy_name;
222 return priv->soc->pins[selector].name;
225 static int mtk_get_pins_count(struct udevice *dev)
227 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
229 return priv->soc->npins;
232 static const char *mtk_get_group_name(struct udevice *dev,
233 unsigned int selector)
235 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
237 if (!priv->soc->grps[selector].name)
238 return mtk_pinctrl_dummy_name;
240 return priv->soc->grps[selector].name;
243 static int mtk_get_functions_count(struct udevice *dev)
245 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
247 return priv->soc->nfuncs;
250 static const char *mtk_get_function_name(struct udevice *dev,
251 unsigned int selector)
253 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
255 if (!priv->soc->funcs[selector].name)
256 return mtk_pinctrl_dummy_name;
258 return priv->soc->funcs[selector].name;
261 static int mtk_pinmux_group_set(struct udevice *dev,
262 unsigned int group_selector,
263 unsigned int func_selector)
265 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
266 const struct mtk_group_desc *grp =
267 &priv->soc->grps[group_selector];
270 for (i = 0; i < grp->num_pins; i++) {
271 int *pin_modes = grp->data;
273 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
280 #if CONFIG_IS_ENABLED(PINCONF)
281 static const struct pinconf_param mtk_conf_params[] = {
282 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
283 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
284 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
285 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
286 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
287 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
288 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
289 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
290 { "output-high", PIN_CONFIG_OUTPUT, 1, },
291 { "output-low", PIN_CONFIG_OUTPUT, 0, },
292 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
295 int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
297 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
298 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
299 const struct mtk_drive_desc *tb;
302 tb = &mtk_drive[desc->drv_n];
303 /* 4mA when (e8, e4) = (0, 0)
304 * 8mA when (e8, e4) = (0, 1)
305 * 12mA when (e8, e4) = (1, 0)
306 * 16mA when (e8, e4) = (1, 1)
308 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
309 arg = (arg / tb->step - 1) * tb->scal;
311 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
319 static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
320 unsigned int param, unsigned int arg)
325 case PIN_CONFIG_BIAS_DISABLE:
326 case PIN_CONFIG_BIAS_PULL_UP:
327 case PIN_CONFIG_BIAS_PULL_DOWN:
328 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
329 (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2;
331 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
336 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN,
341 case PIN_CONFIG_OUTPUT_ENABLE:
342 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
345 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
349 case PIN_CONFIG_INPUT_ENABLE:
350 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
353 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
357 case PIN_CONFIG_OUTPUT:
358 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
362 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
366 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
367 /* arg = 1: Input mode & SMT enable ;
368 * arg = 0: Output mode & SMT disable
371 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
376 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
381 case PIN_CONFIG_DRIVE_STRENGTH:
382 err = mtk_pinconf_drive_set(dev, pin, arg);
396 static int mtk_pinconf_group_set(struct udevice *dev,
397 unsigned int group_selector,
398 unsigned int param, unsigned int arg)
400 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
401 const struct mtk_group_desc *grp =
402 &priv->soc->grps[group_selector];
405 for (i = 0; i < grp->num_pins; i++) {
406 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
415 const struct pinctrl_ops mtk_pinctrl_ops = {
416 .get_pins_count = mtk_get_pins_count,
417 .get_pin_name = mtk_get_pin_name,
418 .get_groups_count = mtk_get_groups_count,
419 .get_group_name = mtk_get_group_name,
420 .get_functions_count = mtk_get_functions_count,
421 .get_function_name = mtk_get_function_name,
422 .pinmux_group_set = mtk_pinmux_group_set,
423 #if CONFIG_IS_ENABLED(PINCONF)
424 .pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
425 .pinconf_params = mtk_conf_params,
426 .pinconf_set = mtk_pinconf_set,
427 .pinconf_group_set = mtk_pinconf_group_set,
429 .set_state = pinctrl_generic_set_state,
432 static int mtk_gpio_get(struct udevice *dev, unsigned int off)
436 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
443 static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
445 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
448 static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
452 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
456 return val ? GPIOF_OUTPUT : GPIOF_INPUT;
459 static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
461 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
464 static int mtk_gpio_direction_output(struct udevice *dev,
465 unsigned int off, int val)
467 mtk_gpio_set(dev, off, val);
469 /* And set the requested value */
470 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
473 static int mtk_gpio_request(struct udevice *dev, unsigned int off,
476 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);
479 static int mtk_gpio_probe(struct udevice *dev)
481 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
482 struct gpio_dev_priv *uc_priv;
484 uc_priv = dev_get_uclass_priv(dev);
485 uc_priv->bank_name = priv->soc->name;
486 uc_priv->gpio_count = priv->soc->npins;
491 static const struct dm_gpio_ops mtk_gpio_ops = {
492 .request = mtk_gpio_request,
493 .set_value = mtk_gpio_set,
494 .get_value = mtk_gpio_get,
495 .get_function = mtk_gpio_get_direction,
496 .direction_input = mtk_gpio_direction_input,
497 .direction_output = mtk_gpio_direction_output,
500 static struct driver mtk_gpio_driver = {
501 .name = "mediatek_gpio",
503 .probe = mtk_gpio_probe,
504 .ops = &mtk_gpio_ops,
507 static int mtk_gpiochip_register(struct udevice *parent)
509 struct uclass_driver *drv;
514 drv = lists_uclass_lookup(UCLASS_GPIO);
518 dev_for_each_subnode(node, parent)
519 if (ofnode_read_bool(node, "gpio-controller")) {
527 ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
528 "mediatek_gpio", 0, node,
536 int mtk_pinctrl_common_probe(struct udevice *dev,
537 struct mtk_pinctrl_soc *soc)
539 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
542 priv->base = dev_read_addr_ptr(dev);
543 if (priv->base == (void *)FDT_ADDR_T_NONE)
548 ret = mtk_gpiochip_register(dev);