1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Ryder Lee <ryder.lee@mediatek.com>
9 #include <dm/device-internal.h>
11 #include <dm/pinctrl.h>
13 #include <asm-generic/gpio.h>
14 #include <linux/bitops.h>
16 #include "pinctrl-mtk-common.h"
18 #if CONFIG_IS_ENABLED(PINCONF)
20 * struct mtk_drive_desc - the structure that holds the information
21 * of the driving current
22 * @min: the minimum current of this group
23 * @max: the maximum current of this group
24 * @step: the step current of this group
25 * @scal: the weight factor
27 * formula: output = ((input) / step - 1) * scal
29 struct mtk_drive_desc {
36 /* The groups of drive strength */
37 static const struct mtk_drive_desc mtk_drive[] = {
38 [DRV_GRP0] = { 4, 16, 4, 1 },
39 [DRV_GRP1] = { 4, 16, 4, 2 },
40 [DRV_GRP2] = { 2, 8, 2, 1 },
41 [DRV_GRP3] = { 2, 8, 2, 2 },
42 [DRV_GRP4] = { 2, 16, 2, 1 },
46 static const char *mtk_pinctrl_dummy_name = "_dummy";
48 static void mtk_w32(struct udevice *dev, u8 i, u32 reg, u32 val)
50 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
52 __raw_writel(val, priv->base[i] + reg);
55 static u32 mtk_r32(struct udevice *dev, u8 i, u32 reg)
57 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
59 return __raw_readl(priv->base[i] + reg);
62 static inline int get_count_order(unsigned int count)
66 order = fls(count) - 1;
67 if (count & (count - 1))
72 void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set)
74 return mtk_i_rmw(dev, 0, reg, mask, set);
77 void mtk_i_rmw(struct udevice *dev, u8 i, u32 reg, u32 mask, u32 set)
81 val = mtk_r32(dev, i, reg);
84 mtk_w32(dev, i, reg, val);
87 static int mtk_hw_pin_field_lookup(struct udevice *dev, int pin,
88 const struct mtk_pin_reg_calc *rc,
89 struct mtk_pin_field *pfd)
91 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
92 const struct mtk_pin_field_calc *c, *e;
94 u32 base_calc = priv->soc->base_calc;
100 if (pin >= c->s_pin && pin <= c->e_pin)
108 /* Calculated bits as the overall offset the pin is located at,
109 * if c->fixed is held, that determines the all the pins in the
110 * range use the same field with the s_pin.
112 bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);
114 /* Fill pfd from bits. For example 32-bit register applied is assumed
115 * when c->sz_reg is equal to 32.
117 pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);
118 pfd->bitpos = bits % c->sz_reg;
119 pfd->mask = (1 << c->x_bits) - 1;
122 pfd->index = c->i_base;
126 /* pfd->next is used for indicating that bit wrapping-around happens
127 * which requires the manipulation for bit 0 starting in the next
128 * register to form the complete field read/write.
130 pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;
135 static int mtk_hw_pin_field_get(struct udevice *dev, int pin,
136 int field, struct mtk_pin_field *pfd)
138 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
139 const struct mtk_pin_reg_calc *rc;
141 if (field < 0 || field >= PINCTRL_PIN_REG_MAX)
144 if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)
145 rc = &priv->soc->reg_cal[field];
149 return mtk_hw_pin_field_lookup(dev, pin, rc, pfd);
152 static void mtk_hw_bits_part(struct mtk_pin_field *pf, int *h, int *l)
154 *l = 32 - pf->bitpos;
155 *h = get_count_order(pf->mask) - *l;
158 static void mtk_hw_write_cross_field(struct udevice *dev,
159 struct mtk_pin_field *pf, int value)
161 int nbits_l, nbits_h;
163 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
165 mtk_i_rmw(dev, pf->index, pf->offset, pf->mask << pf->bitpos,
166 (value & pf->mask) << pf->bitpos);
168 mtk_i_rmw(dev, pf->index, pf->offset + pf->next, BIT(nbits_h) - 1,
169 (value & pf->mask) >> nbits_l);
172 static void mtk_hw_read_cross_field(struct udevice *dev,
173 struct mtk_pin_field *pf, int *value)
175 int nbits_l, nbits_h, h, l;
177 mtk_hw_bits_part(pf, &nbits_h, &nbits_l);
179 l = (mtk_r32(dev, pf->index, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);
180 h = (mtk_r32(dev, pf->index, pf->offset + pf->next)) & (BIT(nbits_h) - 1);
182 *value = (h << nbits_l) | l;
185 static int mtk_hw_set_value(struct udevice *dev, int pin, int field,
188 struct mtk_pin_field pf;
191 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
196 mtk_i_rmw(dev, pf.index, pf.offset, pf.mask << pf.bitpos,
197 (value & pf.mask) << pf.bitpos);
199 mtk_hw_write_cross_field(dev, &pf, value);
204 static int mtk_hw_get_value(struct udevice *dev, int pin, int field,
207 struct mtk_pin_field pf;
210 err = mtk_hw_pin_field_get(dev, pin, field, &pf);
215 *value = (mtk_r32(dev, pf.index, pf.offset) >> pf.bitpos) & pf.mask;
217 mtk_hw_read_cross_field(dev, &pf, value);
222 #if CONFIG_IS_ENABLED(PINCONF)
223 static int mtk_get_pin_io_type(struct udevice *dev, int pin,
224 struct mtk_io_type_desc *io_type)
226 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
227 u8 io_n = priv->soc->pins[pin].io_n;
229 if (io_n >= priv->soc->ntype)
232 io_type->name = priv->soc->io_type[io_n].name;
233 io_type->bias_set = priv->soc->io_type[io_n].bias_set;
234 io_type->drive_set = priv->soc->io_type[io_n].drive_set;
235 io_type->input_enable = priv->soc->io_type[io_n].input_enable;
241 static int mtk_get_groups_count(struct udevice *dev)
243 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
245 return priv->soc->ngrps;
248 static const char *mtk_get_pin_name(struct udevice *dev,
249 unsigned int selector)
251 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
253 if (!priv->soc->pins[selector].name)
254 return mtk_pinctrl_dummy_name;
256 return priv->soc->pins[selector].name;
259 static int mtk_get_pins_count(struct udevice *dev)
261 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
263 return priv->soc->npins;
266 static int mtk_get_pin_muxing(struct udevice *dev, unsigned int selector,
270 err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val);
274 snprintf(buf, size, "Aux Func.%d", val);
278 static const char *mtk_get_group_name(struct udevice *dev,
279 unsigned int selector)
281 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
283 if (!priv->soc->grps[selector].name)
284 return mtk_pinctrl_dummy_name;
286 return priv->soc->grps[selector].name;
289 static int mtk_get_functions_count(struct udevice *dev)
291 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
293 return priv->soc->nfuncs;
296 static const char *mtk_get_function_name(struct udevice *dev,
297 unsigned int selector)
299 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
301 if (!priv->soc->funcs[selector].name)
302 return mtk_pinctrl_dummy_name;
304 return priv->soc->funcs[selector].name;
307 static int mtk_pinmux_group_set(struct udevice *dev,
308 unsigned int group_selector,
309 unsigned int func_selector)
311 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
312 const struct mtk_group_desc *grp =
313 &priv->soc->grps[group_selector];
316 for (i = 0; i < grp->num_pins; i++) {
317 const int *pin_modes = grp->data;
319 mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,
326 #if CONFIG_IS_ENABLED(PINCONF)
327 static const struct pinconf_param mtk_conf_params[] = {
328 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
329 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
330 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
331 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
332 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
333 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
334 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
335 { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
336 { "output-high", PIN_CONFIG_OUTPUT, 1, },
337 { "output-low", PIN_CONFIG_OUTPUT, 0, },
338 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
341 int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, bool disable,
342 bool pullup, u32 val)
344 return mtk_pinconf_bias_set_pu_pd(dev, pin, disable, pullup, val);
347 int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
348 bool pullup, u32 val)
352 /* set pupd_r1_r0 if pullen_pullsel succeeded */
353 err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
356 return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
362 int mtk_pinconf_bias_set_pu_pd(struct udevice *dev, u32 pin, bool disable,
363 bool pullup, u32 val)
368 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
371 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
375 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
378 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup);
386 int mtk_pinconf_bias_set_pullen_pullsel(struct udevice *dev, u32 pin,
387 bool disable, bool pullup, u32 val)
392 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
396 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1);
399 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
408 int mtk_pinconf_bias_set_pupd_r1_r0(struct udevice *dev, u32 pin, bool disable,
409 bool pullup, u32 val)
422 /* MTK HW PUPD bit: 1 for pull-down, 0 for pull-up */
423 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PUPD, !pullup);
427 /* Also set PUPD/R0/R1 if the pin has them */
428 mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R0, r0);
429 mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_R1, r1);
434 int mtk_pinconf_bias_set(struct udevice *dev, u32 pin, u32 arg, u32 val)
437 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
438 struct mtk_io_type_desc io_type;
439 int rev = priv->soc->rev;
440 bool disable, pullup;
442 disable = (arg == PIN_CONFIG_BIAS_DISABLE);
443 pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
445 if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
446 if (io_type.bias_set)
447 err = io_type.bias_set(dev, pin, disable, pullup,
452 } else if (rev == MTK_PINCTRL_V0) {
453 err = mtk_pinconf_bias_set_v0(dev, pin, disable, pullup, val);
455 err = mtk_pinconf_bias_set_v1(dev, pin, disable, pullup, val);
461 int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
465 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
468 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
475 int mtk_pinconf_input_enable(struct udevice *dev, u32 pin, u32 arg)
477 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
478 struct mtk_io_type_desc io_type;
480 int rev = priv->soc->rev;
482 if (!mtk_get_pin_io_type(dev, pin, &io_type))
483 if (io_type.input_enable)
484 return io_type.input_enable(dev, pin, arg);
485 if (rev == MTK_PINCTRL_V1)
486 return mtk_pinconf_input_enable_v1(dev, pin, arg);
491 int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
493 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
494 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
495 const struct mtk_drive_desc *tb;
498 tb = &mtk_drive[desc->drv_n];
499 /* 4mA when (e8, e4) = (0, 0)
500 * 8mA when (e8, e4) = (0, 1)
501 * 12mA when (e8, e4) = (1, 0)
502 * 16mA when (e8, e4) = (1, 1)
504 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
505 arg = (arg / tb->step - 1) * tb->scal;
506 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4,
510 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8,
519 int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
521 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
522 const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
523 const struct mtk_drive_desc *tb;
526 tb = &mtk_drive[desc->drv_n];
527 if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
528 arg = (arg / tb->step - 1) * tb->scal;
529 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
537 int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
540 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
541 struct mtk_io_type_desc io_type;
542 int rev = priv->soc->rev;
544 if (!mtk_get_pin_io_type(dev, pin, &io_type)) {
545 if (io_type.drive_set)
546 err = io_type.drive_set(dev, pin, arg);
549 } else if (rev == MTK_PINCTRL_V0) {
550 err = mtk_pinconf_drive_set_v0(dev, pin, arg);
552 err = mtk_pinconf_drive_set_v1(dev, pin, arg);
558 static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
559 unsigned int param, unsigned int arg)
564 case PIN_CONFIG_BIAS_DISABLE:
565 case PIN_CONFIG_BIAS_PULL_UP:
566 case PIN_CONFIG_BIAS_PULL_DOWN:
567 err = mtk_pinconf_bias_set(dev, pin, param, arg);
571 case PIN_CONFIG_OUTPUT_ENABLE:
572 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT, 0);
575 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
579 case PIN_CONFIG_INPUT_ENABLE:
580 err = mtk_pinconf_input_enable(dev, pin, param);
584 case PIN_CONFIG_OUTPUT:
585 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 1);
589 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DO, arg);
593 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
594 /* arg = 1: Input mode & SMT enable ;
595 * arg = 0: Output mode & SMT disable
598 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR,
603 err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_SMT,
608 case PIN_CONFIG_DRIVE_STRENGTH:
609 err = mtk_pinconf_drive_set(dev, pin, arg);
623 static int mtk_pinconf_group_set(struct udevice *dev,
624 unsigned int group_selector,
625 unsigned int param, unsigned int arg)
627 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
628 const struct mtk_group_desc *grp =
629 &priv->soc->grps[group_selector];
632 for (i = 0; i < grp->num_pins; i++) {
633 ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);
642 const struct pinctrl_ops mtk_pinctrl_ops = {
643 .get_pins_count = mtk_get_pins_count,
644 .get_pin_name = mtk_get_pin_name,
645 .get_pin_muxing = mtk_get_pin_muxing,
646 .get_groups_count = mtk_get_groups_count,
647 .get_group_name = mtk_get_group_name,
648 .get_functions_count = mtk_get_functions_count,
649 .get_function_name = mtk_get_function_name,
650 .pinmux_group_set = mtk_pinmux_group_set,
651 #if CONFIG_IS_ENABLED(PINCONF)
652 .pinconf_num_params = ARRAY_SIZE(mtk_conf_params),
653 .pinconf_params = mtk_conf_params,
654 .pinconf_set = mtk_pinconf_set,
655 .pinconf_group_set = mtk_pinconf_group_set,
657 .set_state = pinctrl_generic_set_state,
660 #if CONFIG_IS_ENABLED(DM_GPIO) || \
661 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
662 static int mtk_gpio_get(struct udevice *dev, unsigned int off)
666 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);
673 static int mtk_gpio_set(struct udevice *dev, unsigned int off, int val)
675 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);
678 static int mtk_gpio_get_direction(struct udevice *dev, unsigned int off)
682 err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);
686 return val ? GPIOF_OUTPUT : GPIOF_INPUT;
689 static int mtk_gpio_direction_input(struct udevice *dev, unsigned int off)
691 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);
694 static int mtk_gpio_direction_output(struct udevice *dev,
695 unsigned int off, int val)
697 mtk_gpio_set(dev, off, val);
699 /* And set the requested value */
700 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);
703 static int mtk_gpio_request(struct udevice *dev, unsigned int off,
706 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
708 return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE,
709 priv->soc->gpio_mode);
712 static int mtk_gpio_probe(struct udevice *dev)
714 struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
715 struct gpio_dev_priv *uc_priv;
717 uc_priv = dev_get_uclass_priv(dev);
718 uc_priv->bank_name = priv->soc->name;
719 uc_priv->gpio_count = priv->soc->npins;
724 static const struct dm_gpio_ops mtk_gpio_ops = {
725 .request = mtk_gpio_request,
726 .set_value = mtk_gpio_set,
727 .get_value = mtk_gpio_get,
728 .get_function = mtk_gpio_get_direction,
729 .direction_input = mtk_gpio_direction_input,
730 .direction_output = mtk_gpio_direction_output,
733 static struct driver mtk_gpio_driver = {
734 .name = "mediatek_gpio",
736 .probe = mtk_gpio_probe,
737 .ops = &mtk_gpio_ops,
740 static int mtk_gpiochip_register(struct udevice *parent)
742 struct uclass_driver *drv;
747 drv = lists_uclass_lookup(UCLASS_GPIO);
752 dev_for_each_subnode(node, parent)
753 if (ofnode_read_bool(node, "gpio-controller")) {
761 ret = device_bind_with_driver_data(parent, &mtk_gpio_driver,
762 "mediatek_gpio", 0, node,
771 int mtk_pinctrl_common_probe(struct udevice *dev,
772 const struct mtk_pinctrl_soc *soc)
774 struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
778 u32 base_calc = soc->base_calc;
779 u32 nbase_names = soc->nbase_names;
786 for (i = 0; i < nbase_names; i++) {
787 addr = devfdt_get_addr_index(dev, i);
788 if (addr == FDT_ADDR_T_NONE)
790 priv->base[i] = (void __iomem *)addr;
793 #if CONFIG_IS_ENABLED(DM_GPIO) || \
794 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
795 ret = mtk_gpiochip_register(dev);