drivers/pinctrl/intel/pinctrl-merrifield.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Merrifield SoC pinctrl driver
   4  *
   5  * Copyright (C) 2016, Intel Corporation
   6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/err.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pinctrl/pinconf.h>
  15 #include <linux/pinctrl/pinconf-generic.h>
  16 #include <linux/pinctrl/pinctrl.h>
  17 #include <linux/pinctrl/pinmux.h>
  18
  19 #include "pinctrl-intel.h"
  20
  21 #define MRFLD_FAMILY_NR                 64
  22 #define MRFLD_FAMILY_LEN                0x400
  23
  24 #define SLEW_OFFSET                     0x000
  25 #define BUFCFG_OFFSET                   0x100
  26 #define MISC_OFFSET                     0x300
  27
  28 #define BUFCFG_PINMODE_SHIFT            0
  29 #define BUFCFG_PINMODE_MASK             GENMASK(2, 0)
  30 #define BUFCFG_PINMODE_GPIO             0
  31 #define BUFCFG_PUPD_VAL_SHIFT           4
  32 #define BUFCFG_PUPD_VAL_MASK            GENMASK(5, 4)
  33 #define BUFCFG_PUPD_VAL_2K              0
  34 #define BUFCFG_PUPD_VAL_20K             1
  35 #define BUFCFG_PUPD_VAL_50K             2
  36 #define BUFCFG_PUPD_VAL_910             3
  37 #define BUFCFG_PU_EN                    BIT(8)
  38 #define BUFCFG_PD_EN                    BIT(9)
  39 #define BUFCFG_Px_EN_MASK               GENMASK(9, 8)
  40 #define BUFCFG_SLEWSEL                  BIT(10)
  41 #define BUFCFG_OVINEN                   BIT(12)
  42 #define BUFCFG_OVINEN_EN                BIT(13)
  43 #define BUFCFG_OVINEN_MASK              GENMASK(13, 12)
  44 #define BUFCFG_OVOUTEN                  BIT(14)
  45 #define BUFCFG_OVOUTEN_EN               BIT(15)
  46 #define BUFCFG_OVOUTEN_MASK             GENMASK(15, 14)
  47 #define BUFCFG_INDATAOV_VAL             BIT(16)
  48 #define BUFCFG_INDATAOV_EN              BIT(17)
  49 #define BUFCFG_INDATAOV_MASK            GENMASK(17, 16)
  50 #define BUFCFG_OUTDATAOV_VAL            BIT(18)
  51 #define BUFCFG_OUTDATAOV_EN             BIT(19)
  52 #define BUFCFG_OUTDATAOV_MASK           GENMASK(19, 18)
  53 #define BUFCFG_OD_EN                    BIT(21)
  54
  55 /**
  56  * struct mrfld_family - Intel pin family description
  57  * @barno: MMIO BAR number where registers for this family reside
  58  * @pin_base: Starting pin of pins in this family
  59  * @npins: Number of pins in this family
  60  * @protected: True if family is protected by access
  61  * @regs: family specific common registers
  62  */
  63 struct mrfld_family {
  64         unsigned int barno;
  65         unsigned int pin_base;
  66         size_t npins;
  67         bool protected;
  68         void __iomem *regs;
  69 };
  70
  71 #define MRFLD_FAMILY(b, s, e)                           \
  72         {                                               \
  73                 .barno = (b),                           \
  74                 .pin_base = (s),                        \
  75                 .npins = (e) - (s) + 1,                 \
  76         }
  77
  78 #define MRFLD_FAMILY_PROTECTED(b, s, e)                 \
  79         {                                               \
  80                 .barno = (b),                           \
  81                 .pin_base = (s),                        \
  82                 .npins = (e) - (s) + 1,                 \
  83                 .protected = true,                      \
  84         }
  85
  86 static const struct pinctrl_pin_desc mrfld_pins[] = {
  87         /* Family 0: OCP2SSC (0 pins) */
  88         /* Family 1: ULPI (13 pins) */
  89         PINCTRL_PIN(0, "ULPI_CLK"),
  90         PINCTRL_PIN(1, "ULPI_D0"),
  91         PINCTRL_PIN(2, "ULPI_D1"),
  92         PINCTRL_PIN(3, "ULPI_D2"),
  93         PINCTRL_PIN(4, "ULPI_D3"),
  94         PINCTRL_PIN(5, "ULPI_D4"),
  95         PINCTRL_PIN(6, "ULPI_D5"),
  96         PINCTRL_PIN(7, "ULPI_D6"),
  97         PINCTRL_PIN(8, "ULPI_D7"),
  98         PINCTRL_PIN(9, "ULPI_DIR"),
  99         PINCTRL_PIN(10, "ULPI_NXT"),
 100         PINCTRL_PIN(11, "ULPI_REFCLK"),
 101         PINCTRL_PIN(12, "ULPI_STP"),
 102         /* Family 2: eMMC (24 pins) */
 103         PINCTRL_PIN(13, "EMMC_CLK"),
 104         PINCTRL_PIN(14, "EMMC_CMD"),
 105         PINCTRL_PIN(15, "EMMC_D0"),
 106         PINCTRL_PIN(16, "EMMC_D1"),
 107         PINCTRL_PIN(17, "EMMC_D2"),
 108         PINCTRL_PIN(18, "EMMC_D3"),
 109         PINCTRL_PIN(19, "EMMC_D4"),
 110         PINCTRL_PIN(20, "EMMC_D5"),
 111         PINCTRL_PIN(21, "EMMC_D6"),
 112         PINCTRL_PIN(22, "EMMC_D7"),
 113         PINCTRL_PIN(23, "EMMC_RST_N"),
 114         PINCTRL_PIN(24, "GP154"),
 115         PINCTRL_PIN(25, "GP155"),
 116         PINCTRL_PIN(26, "GP156"),
 117         PINCTRL_PIN(27, "GP157"),
 118         PINCTRL_PIN(28, "GP158"),
 119         PINCTRL_PIN(29, "GP159"),
 120         PINCTRL_PIN(30, "GP160"),
 121         PINCTRL_PIN(31, "GP161"),
 122         PINCTRL_PIN(32, "GP162"),
 123         PINCTRL_PIN(33, "GP163"),
 124         PINCTRL_PIN(34, "GP97"),
 125         PINCTRL_PIN(35, "GP14"),
 126         PINCTRL_PIN(36, "GP15"),
 127         /* Family 3: SDIO (20 pins) */
 128         PINCTRL_PIN(37, "GP77_SD_CD"),
 129         PINCTRL_PIN(38, "GP78_SD_CLK"),
 130         PINCTRL_PIN(39, "GP79_SD_CMD"),
 131         PINCTRL_PIN(40, "GP80_SD_D0"),
 132         PINCTRL_PIN(41, "GP81_SD_D1"),
 133         PINCTRL_PIN(42, "GP82_SD_D2"),
 134         PINCTRL_PIN(43, "GP83_SD_D3"),
 135         PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
 136         PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
 137         PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"),
 138         PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
 139         PINCTRL_PIN(48, "GP87_SD_PD"),
 140         PINCTRL_PIN(49, "GP89_SD_WP"),
 141         PINCTRL_PIN(50, "GP90_SDIO_CLK"),
 142         PINCTRL_PIN(51, "GP91_SDIO_CMD"),
 143         PINCTRL_PIN(52, "GP92_SDIO_D0"),
 144         PINCTRL_PIN(53, "GP93_SDIO_D1"),
 145         PINCTRL_PIN(54, "GP94_SDIO_D2"),
 146         PINCTRL_PIN(55, "GP95_SDIO_D3"),
 147         PINCTRL_PIN(56, "GP96_SDIO_PD"),
 148         /* Family 4: HSI (8 pins) */
 149         PINCTRL_PIN(57, "HSI_ACDATA"),
 150         PINCTRL_PIN(58, "HSI_ACFLAG"),
 151         PINCTRL_PIN(59, "HSI_ACREADY"),
 152         PINCTRL_PIN(60, "HSI_ACWAKE"),
 153         PINCTRL_PIN(61, "HSI_CADATA"),
 154         PINCTRL_PIN(62, "HSI_CAFLAG"),
 155         PINCTRL_PIN(63, "HSI_CAREADY"),
 156         PINCTRL_PIN(64, "HSI_CAWAKE"),
 157         /* Family 5: SSP Audio (14 pins) */
 158         PINCTRL_PIN(65, "GP70"),
 159         PINCTRL_PIN(66, "GP71"),
 160         PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
 161         PINCTRL_PIN(68, "GP33_I2S_0_FS"),
 162         PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
 163         PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
 164         PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
 165         PINCTRL_PIN(72, "GP37_I2S_1_FS"),
 166         PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
 167         PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
 168         PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
 169         PINCTRL_PIN(76, "GP41_I2S_2_FS"),
 170         PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
 171         PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
 172         /* Family 6: GP SSP (22 pins) */
 173         PINCTRL_PIN(79, "GP120_SPI_3_CLK"),
 174         PINCTRL_PIN(80, "GP121_SPI_3_SS"),
 175         PINCTRL_PIN(81, "GP122_SPI_3_RXD"),
 176         PINCTRL_PIN(82, "GP123_SPI_3_TXD"),
 177         PINCTRL_PIN(83, "GP102_SPI_4_CLK"),
 178         PINCTRL_PIN(84, "GP103_SPI_4_SS_0"),
 179         PINCTRL_PIN(85, "GP104_SPI_4_SS_1"),
 180         PINCTRL_PIN(86, "GP105_SPI_4_SS_2"),
 181         PINCTRL_PIN(87, "GP106_SPI_4_SS_3"),
 182         PINCTRL_PIN(88, "GP107_SPI_4_RXD"),
 183         PINCTRL_PIN(89, "GP108_SPI_4_TXD"),
 184         PINCTRL_PIN(90, "GP109_SPI_5_CLK"),
 185         PINCTRL_PIN(91, "GP110_SPI_5_SS_0"),
 186         PINCTRL_PIN(92, "GP111_SPI_5_SS_1"),
 187         PINCTRL_PIN(93, "GP112_SPI_5_SS_2"),
 188         PINCTRL_PIN(94, "GP113_SPI_5_SS_3"),
 189         PINCTRL_PIN(95, "GP114_SPI_5_RXD"),
 190         PINCTRL_PIN(96, "GP115_SPI_5_TXD"),
 191         PINCTRL_PIN(97, "GP116_SPI_6_CLK"),
 192         PINCTRL_PIN(98, "GP117_SPI_6_SS"),
 193         PINCTRL_PIN(99, "GP118_SPI_6_RXD"),
 194         PINCTRL_PIN(100, "GP119_SPI_6_TXD"),
 195         /* Family 7: I2C (14 pins) */
 196         PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
 197         PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
 198         PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
 199         PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
 200         PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
 201         PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
 202         PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
 203         PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
 204         PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
 205         PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
 206         PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
 207         PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
 208         PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
 209         PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
 210         /* Family 8: UART (12 pins) */
 211         PINCTRL_PIN(115, "GP124_UART_0_CTS"),
 212         PINCTRL_PIN(116, "GP125_UART_0_RTS"),
 213         PINCTRL_PIN(117, "GP126_UART_0_RX"),
 214         PINCTRL_PIN(118, "GP127_UART_0_TX"),
 215         PINCTRL_PIN(119, "GP128_UART_1_CTS"),
 216         PINCTRL_PIN(120, "GP129_UART_1_RTS"),
 217         PINCTRL_PIN(121, "GP130_UART_1_RX"),
 218         PINCTRL_PIN(122, "GP131_UART_1_TX"),
 219         PINCTRL_PIN(123, "GP132_UART_2_CTS"),
 220         PINCTRL_PIN(124, "GP133_UART_2_RTS"),
 221         PINCTRL_PIN(125, "GP134_UART_2_RX"),
 222         PINCTRL_PIN(126, "GP135_UART_2_TX"),
 223         /* Family 9: GPIO South (19 pins) */
 224         PINCTRL_PIN(127, "GP177"),
 225         PINCTRL_PIN(128, "GP178"),
 226         PINCTRL_PIN(129, "GP179"),
 227         PINCTRL_PIN(130, "GP180"),
 228         PINCTRL_PIN(131, "GP181"),
 229         PINCTRL_PIN(132, "GP182_PWM2"),
 230         PINCTRL_PIN(133, "GP183_PWM3"),
 231         PINCTRL_PIN(134, "GP184"),
 232         PINCTRL_PIN(135, "GP185"),
 233         PINCTRL_PIN(136, "GP186"),
 234         PINCTRL_PIN(137, "GP187"),
 235         PINCTRL_PIN(138, "GP188"),
 236         PINCTRL_PIN(139, "GP189"),
 237         PINCTRL_PIN(140, "GP64_FAST_INT0"),
 238         PINCTRL_PIN(141, "GP65_FAST_INT1"),
 239         PINCTRL_PIN(142, "GP66_FAST_INT2"),
 240         PINCTRL_PIN(143, "GP67_FAST_INT3"),
 241         PINCTRL_PIN(144, "GP12_PWM0"),
 242         PINCTRL_PIN(145, "GP13_PWM1"),
 243         /* Family 10: Camera Sideband (12 pins) */
 244         PINCTRL_PIN(146, "GP0"),
 245         PINCTRL_PIN(147, "GP1"),
 246         PINCTRL_PIN(148, "GP2"),
 247         PINCTRL_PIN(149, "GP3"),
 248         PINCTRL_PIN(150, "GP4"),
 249         PINCTRL_PIN(151, "GP5"),
 250         PINCTRL_PIN(152, "GP6"),
 251         PINCTRL_PIN(153, "GP7"),
 252         PINCTRL_PIN(154, "GP8"),
 253         PINCTRL_PIN(155, "GP9"),
 254         PINCTRL_PIN(156, "GP10"),
 255         PINCTRL_PIN(157, "GP11"),
 256         /* Family 11: Clock (22 pins) */
 257         PINCTRL_PIN(158, "GP137"),
 258         PINCTRL_PIN(159, "GP138"),
 259         PINCTRL_PIN(160, "GP139"),
 260         PINCTRL_PIN(161, "GP140"),
 261         PINCTRL_PIN(162, "GP141"),
 262         PINCTRL_PIN(163, "GP142"),
 263         PINCTRL_PIN(164, "GP16_HDMI_HPD"),
 264         PINCTRL_PIN(165, "GP68_DSI_A_TE"),
 265         PINCTRL_PIN(166, "GP69_DSI_C_TE"),
 266         PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
 267         PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
 268         PINCTRL_PIN(169, "OSC_CLK0"),
 269         PINCTRL_PIN(170, "OSC_CLK1"),
 270         PINCTRL_PIN(171, "OSC_CLK2"),
 271         PINCTRL_PIN(172, "OSC_CLK3"),
 272         PINCTRL_PIN(173, "OSC_CLK4"),
 273         PINCTRL_PIN(174, "RESETOUT"),
 274         PINCTRL_PIN(175, "PMODE"),
 275         PINCTRL_PIN(176, "PRDY"),
 276         PINCTRL_PIN(177, "PREQ"),
 277         PINCTRL_PIN(178, "GP190"),
 278         PINCTRL_PIN(179, "GP191"),
 279         /* Family 12: MSIC (15 pins) */
 280         PINCTRL_PIN(180, "I2C_0_SCL"),
 281         PINCTRL_PIN(181, "I2C_0_SDA"),
 282         PINCTRL_PIN(182, "IERR"),
 283         PINCTRL_PIN(183, "JTAG_TCK"),
 284         PINCTRL_PIN(184, "JTAG_TDI"),
 285         PINCTRL_PIN(185, "JTAG_TDO"),
 286         PINCTRL_PIN(186, "JTAG_TMS"),
 287         PINCTRL_PIN(187, "JTAG_TRST"),
 288         PINCTRL_PIN(188, "PROCHOT"),
 289         PINCTRL_PIN(189, "RTC_CLK"),
 290         PINCTRL_PIN(190, "SVID_ALERT"),
 291         PINCTRL_PIN(191, "SVID_CLK"),
 292         PINCTRL_PIN(192, "SVID_D"),
 293         PINCTRL_PIN(193, "THERMTRIP"),
 294         PINCTRL_PIN(194, "STANDBY"),
 295         /* Family 13: Keyboard (20 pins) */
 296         PINCTRL_PIN(195, "GP44"),
 297         PINCTRL_PIN(196, "GP45"),
 298         PINCTRL_PIN(197, "GP46"),
 299         PINCTRL_PIN(198, "GP47"),
 300         PINCTRL_PIN(199, "GP48"),
 301         PINCTRL_PIN(200, "GP49"),
 302         PINCTRL_PIN(201, "GP50"),
 303         PINCTRL_PIN(202, "GP51"),
 304         PINCTRL_PIN(203, "GP52"),
 305         PINCTRL_PIN(204, "GP53"),
 306         PINCTRL_PIN(205, "GP54"),
 307         PINCTRL_PIN(206, "GP55"),
 308         PINCTRL_PIN(207, "GP56"),
 309         PINCTRL_PIN(208, "GP57"),
 310         PINCTRL_PIN(209, "GP58"),
 311         PINCTRL_PIN(210, "GP59"),
 312         PINCTRL_PIN(211, "GP60"),
 313         PINCTRL_PIN(212, "GP61"),
 314         PINCTRL_PIN(213, "GP62"),
 315         PINCTRL_PIN(214, "GP63"),
 316         /* Family 14: GPIO North (13 pins) */
 317         PINCTRL_PIN(215, "GP164"),
 318         PINCTRL_PIN(216, "GP165"),
 319         PINCTRL_PIN(217, "GP166"),
 320         PINCTRL_PIN(218, "GP167"),
 321         PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
 322         PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
 323         PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
 324         PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
 325         PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
 326         PINCTRL_PIN(224, "GP173"),
 327         PINCTRL_PIN(225, "GP174"),
 328         PINCTRL_PIN(226, "GP175"),
 329         PINCTRL_PIN(227, "GP176"),
 330         /* Family 15: PTI (5 pins) */
 331         PINCTRL_PIN(228, "GP72_PTI_CLK"),
 332         PINCTRL_PIN(229, "GP73_PTI_D0"),
 333         PINCTRL_PIN(230, "GP74_PTI_D1"),
 334         PINCTRL_PIN(231, "GP75_PTI_D2"),
 335         PINCTRL_PIN(232, "GP76_PTI_D3"),
 336         /* Family 16: USB3 (0 pins) */
 337         /* Family 17: HSIC (0 pins) */
 338         /* Family 18: Broadcast (0 pins) */
 339 };
 340
 341 static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
 342 static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
 343 static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
 344 static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
 345 static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
 346 static const unsigned int mrfld_pwm0_pins[] = { 144 };
 347 static const unsigned int mrfld_pwm1_pins[] = { 145 };
 348 static const unsigned int mrfld_pwm2_pins[] = { 132 };
 349 static const unsigned int mrfld_pwm3_pins[] = { 133 };
 350
 351 static const struct intel_pingroup mrfld_groups[] = {
 352         PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
 353         PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
 354         PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
 355         PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
 356         PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
 357         PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
 358         PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
 359         PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
 360         PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
 361 };
 362
 363 static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
 364 static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
 365 static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
 366 static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
 367 static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
 368 static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
 369 static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
 370 static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
 371 static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
 372
 373 static const struct intel_function mrfld_functions[] = {
 374         FUNCTION("sdio", mrfld_sdio_groups),
 375         FUNCTION("spi5", mrfld_spi5_groups),
 376         FUNCTION("uart0", mrfld_uart0_groups),
 377         FUNCTION("uart1", mrfld_uart1_groups),
 378         FUNCTION("uart2", mrfld_uart2_groups),
 379         FUNCTION("pwm0", mrfld_pwm0_groups),
 380         FUNCTION("pwm1", mrfld_pwm1_groups),
 381         FUNCTION("pwm2", mrfld_pwm2_groups),
 382         FUNCTION("pwm3", mrfld_pwm3_groups),
 383 };
 384
 385 static const struct mrfld_family mrfld_families[] = {
 386         MRFLD_FAMILY(1, 0, 12),
 387         MRFLD_FAMILY(2, 13, 36),
 388         MRFLD_FAMILY(3, 37, 56),
 389         MRFLD_FAMILY(4, 57, 64),
 390         MRFLD_FAMILY(5, 65, 78),
 391         MRFLD_FAMILY(6, 79, 100),
 392         MRFLD_FAMILY_PROTECTED(7, 101, 114),
 393         MRFLD_FAMILY(8, 115, 126),
 394         MRFLD_FAMILY(9, 127, 145),
 395         MRFLD_FAMILY(10, 146, 157),
 396         MRFLD_FAMILY(11, 158, 179),
 397         MRFLD_FAMILY_PROTECTED(12, 180, 194),
 398         MRFLD_FAMILY(13, 195, 214),
 399         MRFLD_FAMILY(14, 215, 227),
 400         MRFLD_FAMILY(15, 228, 232),
 401 };
 402
 403 /**
 404  * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
 405  * @dev: Pointer to the device structure
 406  * @lock: Lock to serialize register access
 407  * @pctldesc: Pin controller description
 408  * @pctldev: Pointer to the pin controller device
 409  * @families: Array of families this pinctrl handles
 410  * @nfamilies: Number of families in the array
 411  * @functions: Array of functions
 412  * @nfunctions: Number of functions in the array
 413  * @groups: Array of pin groups
 414  * @ngroups: Number of groups in the array
 415  * @pins: Array of pins this pinctrl controls
 416  * @npins: Number of pins in the array
 417  */
 418 struct mrfld_pinctrl {
 419         struct device *dev;
 420         raw_spinlock_t lock;
 421         struct pinctrl_desc pctldesc;
 422         struct pinctrl_dev *pctldev;
 423
 424         /* Pin controller configuration */
 425         const struct mrfld_family *families;
 426         size_t nfamilies;
 427         const struct intel_function *functions;
 428         size_t nfunctions;
 429         const struct intel_pingroup *groups;
 430         size_t ngroups;
 431         const struct pinctrl_pin_desc *pins;
 432         size_t npins;
 433 };
 434
 435 #define pin_to_bufno(f, p)              ((p) - (f)->pin_base)
 436
 437 static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
 438                                                    unsigned int pin)
 439 {
 440         const struct mrfld_family *family;
 441         unsigned int i;
 442
 443         for (i = 0; i < mp->nfamilies; i++) {
 444                 family = &mp->families[i];
 445                 if (pin >= family->pin_base &&
 446                     pin < family->pin_base + family->npins)
 447                         return family;
 448         }
 449
 450         dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
 451         return NULL;
 452 }
 453
 454 static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
 455 {
 456         const struct mrfld_family *family;
 457
 458         family = mrfld_get_family(mp, pin);
 459         if (!family)
 460                 return false;
 461
 462         return !family->protected;
 463 }
 464
 465 static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
 466 {
 467         const struct mrfld_family *family;
 468         unsigned int bufno;
 469
 470         family = mrfld_get_family(mp, pin);
 471         if (!family)
 472                 return NULL;
 473
 474         bufno = pin_to_bufno(family, pin);
 475         return family->regs + BUFCFG_OFFSET + bufno * 4;
 476 }
 477
 478 static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
 479 {
 480         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 481
 482         return mp->ngroups;
 483 }
 484
 485 static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
 486                                         unsigned int group)
 487 {
 488         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 489
 490         return mp->groups[group].name;
 491 }
 492
 493 static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
 494                                 const unsigned int **pins, unsigned int *npins)
 495 {
 496         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 497
 498         *pins = mp->groups[group].pins;
 499         *npins = mp->groups[group].npins;
 500         return 0;
 501 }
 502
 503 static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 504                                unsigned int pin)
 505 {
 506         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 507         void __iomem *bufcfg;
 508         u32 value, mode;
 509
 510         if (!mrfld_buf_available(mp, pin)) {
 511                 seq_puts(s, "not available");
 512                 return;
 513         }
 514
 515         bufcfg = mrfld_get_bufcfg(mp, pin);
 516         value = readl(bufcfg);
 517
 518         mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
 519         if (!mode)
 520                 seq_puts(s, "GPIO ");
 521         else
 522                 seq_printf(s, "mode %d ", mode);
 523
 524         seq_printf(s, "0x%08x", value);
 525 }
 526
 527 static const struct pinctrl_ops mrfld_pinctrl_ops = {
 528         .get_groups_count = mrfld_get_groups_count,
 529         .get_group_name = mrfld_get_group_name,
 530         .get_group_pins = mrfld_get_group_pins,
 531         .pin_dbg_show = mrfld_pin_dbg_show,
 532 };
 533
 534 static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
 535 {
 536         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 537
 538         return mp->nfunctions;
 539 }
 540
 541 static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
 542                                            unsigned int function)
 543 {
 544         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 545
 546         return mp->functions[function].name;
 547 }
 548
 549 static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
 550                                      unsigned int function,
 551                                      const char * const **groups,
 552                                      unsigned int * const ngroups)
 553 {
 554         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 555
 556         *groups = mp->functions[function].groups;
 557         *ngroups = mp->functions[function].ngroups;
 558         return 0;
 559 }
 560
 561 static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
 562                                 u32 bits, u32 mask)
 563 {
 564         void __iomem *bufcfg;
 565         u32 value;
 566
 567         bufcfg = mrfld_get_bufcfg(mp, pin);
 568         value = readl(bufcfg);
 569
 570         value &= ~mask;
 571         value |= bits & mask;
 572
 573         writel(value, bufcfg);
 574 }
 575
 576 static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
 577                                 unsigned int function,
 578                                 unsigned int group)
 579 {
 580         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 581         const struct intel_pingroup *grp = &mp->groups[group];
 582         u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
 583         u32 mask = BUFCFG_PINMODE_MASK;
 584         unsigned long flags;
 585         unsigned int i;
 586
 587         /*
 588          * All pins in the groups needs to be accessible and writable
 589          * before we can enable the mux for this group.
 590          */
 591         for (i = 0; i < grp->npins; i++) {
 592                 if (!mrfld_buf_available(mp, grp->pins[i]))
 593                         return -EBUSY;
 594         }
 595
 596         /* Now enable the mux setting for each pin in the group */
 597         raw_spin_lock_irqsave(&mp->lock, flags);
 598         for (i = 0; i < grp->npins; i++)
 599                 mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
 600         raw_spin_unlock_irqrestore(&mp->lock, flags);
 601
 602         return 0;
 603 }
 604
 605 static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
 606                                      struct pinctrl_gpio_range *range,
 607                                      unsigned int pin)
 608 {
 609         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 610         u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
 611         u32 mask = BUFCFG_PINMODE_MASK;
 612         unsigned long flags;
 613
 614         if (!mrfld_buf_available(mp, pin))
 615                 return -EBUSY;
 616
 617         raw_spin_lock_irqsave(&mp->lock, flags);
 618         mrfld_update_bufcfg(mp, pin, bits, mask);
 619         raw_spin_unlock_irqrestore(&mp->lock, flags);
 620
 621         return 0;
 622 }
 623
 624 static const struct pinmux_ops mrfld_pinmux_ops = {
 625         .get_functions_count = mrfld_get_functions_count,
 626         .get_function_name = mrfld_get_function_name,
 627         .get_function_groups = mrfld_get_function_groups,
 628         .set_mux = mrfld_pinmux_set_mux,
 629         .gpio_request_enable = mrfld_gpio_request_enable,
 630 };
 631
 632 static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
 633                             unsigned long *config)
 634 {
 635         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 636         enum pin_config_param param = pinconf_to_config_param(*config);
 637         u32 value, term;
 638         u16 arg = 0;
 639
 640         if (!mrfld_buf_available(mp, pin))
 641                 return -ENOTSUPP;
 642
 643         value = readl(mrfld_get_bufcfg(mp, pin));
 644         term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
 645
 646         switch (param) {
 647         case PIN_CONFIG_BIAS_DISABLE:
 648                 if (value & BUFCFG_Px_EN_MASK)
 649                         return -EINVAL;
 650                 break;
 651
 652         case PIN_CONFIG_BIAS_PULL_UP:
 653                 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
 654                         return -EINVAL;
 655
 656                 switch (term) {
 657                 case BUFCFG_PUPD_VAL_910:
 658                         arg = 910;
 659                         break;
 660                 case BUFCFG_PUPD_VAL_2K:
 661                         arg = 2000;
 662                         break;
 663                 case BUFCFG_PUPD_VAL_20K:
 664                         arg = 20000;
 665                         break;
 666                 case BUFCFG_PUPD_VAL_50K:
 667                         arg = 50000;
 668                         break;
 669                 }
 670
 671                 break;
 672
 673         case PIN_CONFIG_BIAS_PULL_DOWN:
 674                 if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
 675                         return -EINVAL;
 676
 677                 switch (term) {
 678                 case BUFCFG_PUPD_VAL_910:
 679                         arg = 910;
 680                         break;
 681                 case BUFCFG_PUPD_VAL_2K:
 682                         arg = 2000;
 683                         break;
 684                 case BUFCFG_PUPD_VAL_20K:
 685                         arg = 20000;
 686                         break;
 687                 case BUFCFG_PUPD_VAL_50K:
 688                         arg = 50000;
 689                         break;
 690                 }
 691
 692                 break;
 693
 694         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 695                 if (!(value & BUFCFG_OD_EN))
 696                         return -EINVAL;
 697                 break;
 698
 699         case PIN_CONFIG_SLEW_RATE:
 700                 if (!(value & BUFCFG_SLEWSEL))
 701                         arg = 0;
 702                 else
 703                         arg = 1;
 704                 break;
 705
 706         default:
 707                 return -ENOTSUPP;
 708         }
 709
 710         *config = pinconf_to_config_packed(param, arg);
 711         return 0;
 712 }
 713
 714 static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
 715                                 unsigned long config)
 716 {
 717         unsigned int param = pinconf_to_config_param(config);
 718         unsigned int arg = pinconf_to_config_argument(config);
 719         u32 bits = 0, mask = 0;
 720         unsigned long flags;
 721
 722         switch (param) {
 723         case PIN_CONFIG_BIAS_DISABLE:
 724                 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
 725                 break;
 726
 727         case PIN_CONFIG_BIAS_PULL_UP:
 728                 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
 729                 bits |= BUFCFG_PU_EN;
 730
 731                 switch (arg) {
 732                 case 50000:
 733                         bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
 734                         break;
 735                 case 20000:
 736                         bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
 737                         break;
 738                 case 2000:
 739                         bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
 740                         break;
 741                 default:
 742                         return -EINVAL;
 743                 }
 744
 745                 break;
 746
 747         case PIN_CONFIG_BIAS_PULL_DOWN:
 748                 mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
 749                 bits |= BUFCFG_PD_EN;
 750
 751                 switch (arg) {
 752                 case 50000:
 753                         bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
 754                         break;
 755                 case 20000:
 756                         bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
 757                         break;
 758                 case 2000:
 759                         bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
 760                         break;
 761                 default:
 762                         return -EINVAL;
 763                 }
 764
 765                 break;
 766
 767         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 768                 mask |= BUFCFG_OD_EN;
 769                 if (arg)
 770                         bits |= BUFCFG_OD_EN;
 771                 break;
 772
 773         case PIN_CONFIG_SLEW_RATE:
 774                 mask |= BUFCFG_SLEWSEL;
 775                 if (arg)
 776                         bits |= BUFCFG_SLEWSEL;
 777                 break;
 778         }
 779
 780         raw_spin_lock_irqsave(&mp->lock, flags);
 781         mrfld_update_bufcfg(mp, pin, bits, mask);
 782         raw_spin_unlock_irqrestore(&mp->lock, flags);
 783
 784         return 0;
 785 }
 786
 787 static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
 788                             unsigned long *configs, unsigned int nconfigs)
 789 {
 790         struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
 791         unsigned int i;
 792         int ret;
 793
 794         if (!mrfld_buf_available(mp, pin))
 795                 return -ENOTSUPP;
 796
 797         for (i = 0; i < nconfigs; i++) {
 798                 switch (pinconf_to_config_param(configs[i])) {
 799                 case PIN_CONFIG_BIAS_DISABLE:
 800                 case PIN_CONFIG_BIAS_PULL_UP:
 801                 case PIN_CONFIG_BIAS_PULL_DOWN:
 802                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 803                 case PIN_CONFIG_SLEW_RATE:
 804                         ret = mrfld_config_set_pin(mp, pin, configs[i]);
 805                         if (ret)
 806                                 return ret;
 807                         break;
 808
 809                 default:
 810                         return -ENOTSUPP;
 811                 }
 812         }
 813
 814         return 0;
 815 }
 816
 817 static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
 818                                   unsigned int group, unsigned long *config)
 819 {
 820         const unsigned int *pins;
 821         unsigned int npins;
 822         int ret;
 823
 824         ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
 825         if (ret)
 826                 return ret;
 827
 828         ret = mrfld_config_get(pctldev, pins[0], config);
 829         if (ret)
 830                 return ret;
 831
 832         return 0;
 833 }
 834
 835 static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
 836                                   unsigned int group, unsigned long *configs,
 837                                   unsigned int num_configs)
 838 {
 839         const unsigned int *pins;
 840         unsigned int npins;
 841         int i, ret;
 842
 843         ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
 844         if (ret)
 845                 return ret;
 846
 847         for (i = 0; i < npins; i++) {
 848                 ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
 849                 if (ret)
 850                         return ret;
 851         }
 852
 853         return 0;
 854 }
 855
 856 static const struct pinconf_ops mrfld_pinconf_ops = {
 857         .is_generic = true,
 858         .pin_config_get = mrfld_config_get,
 859         .pin_config_set = mrfld_config_set,
 860         .pin_config_group_get = mrfld_config_group_get,
 861         .pin_config_group_set = mrfld_config_group_set,
 862 };
 863
 864 static const struct pinctrl_desc mrfld_pinctrl_desc = {
 865         .pctlops = &mrfld_pinctrl_ops,
 866         .pmxops = &mrfld_pinmux_ops,
 867         .confops = &mrfld_pinconf_ops,
 868         .owner = THIS_MODULE,
 869 };
 870
 871 static int mrfld_pinctrl_probe(struct platform_device *pdev)
 872 {
 873         struct mrfld_family *families;
 874         struct mrfld_pinctrl *mp;
 875         struct resource *mem;
 876         void __iomem *regs;
 877         size_t nfamilies;
 878         unsigned int i;
 879
 880         mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
 881         if (!mp)
 882                 return -ENOMEM;
 883
 884         mp->dev = &pdev->dev;
 885         raw_spin_lock_init(&mp->lock);
 886
 887         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 888         regs = devm_ioremap_resource(&pdev->dev, mem);
 889         if (IS_ERR(regs))
 890                 return PTR_ERR(regs);
 891
 892         /*
 893          * Make a copy of the families which we can use to hold pointers
 894          * to the registers.
 895          */
 896         nfamilies = ARRAY_SIZE(mrfld_families),
 897         families = devm_kmemdup(&pdev->dev, mrfld_families,
 898                                             sizeof(mrfld_families),
 899                                             GFP_KERNEL);
 900         if (!families)
 901                 return -ENOMEM;
 902
 903         /* Splice memory resource by chunk per family */
 904         for (i = 0; i < nfamilies; i++) {
 905                 struct mrfld_family *family = &families[i];
 906
 907                 family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
 908         }
 909
 910         mp->families = families;
 911         mp->nfamilies = nfamilies;
 912         mp->functions = mrfld_functions;
 913         mp->nfunctions = ARRAY_SIZE(mrfld_functions);
 914         mp->groups = mrfld_groups;
 915         mp->ngroups = ARRAY_SIZE(mrfld_groups);
 916         mp->pctldesc = mrfld_pinctrl_desc;
 917         mp->pctldesc.name = dev_name(&pdev->dev);
 918         mp->pctldesc.pins = mrfld_pins;
 919         mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
 920
 921         mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
 922         if (IS_ERR(mp->pctldev)) {
 923                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
 924                 return PTR_ERR(mp->pctldev);
 925         }
 926
 927         platform_set_drvdata(pdev, mp);
 928         return 0;
 929 }
 930
 931 static const struct acpi_device_id mrfld_acpi_table[] = {
 932         { "INTC1002" },
 933         { }
 934 };
 935 MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
 936
 937 static struct platform_driver mrfld_pinctrl_driver = {
 938         .probe = mrfld_pinctrl_probe,
 939         .driver = {
 940                 .name = "pinctrl-merrifield",
 941                 .acpi_match_table = mrfld_acpi_table,
 942         },
 943 };
 944
 945 static int __init mrfld_pinctrl_init(void)
 946 {
 947         return platform_driver_register(&mrfld_pinctrl_driver);
 948 }
 949 subsys_initcall(mrfld_pinctrl_init);
 950
 951 static void __exit mrfld_pinctrl_exit(void)
 952 {
 953         platform_driver_unregister(&mrfld_pinctrl_driver);
 954 }
 955 module_exit(mrfld_pinctrl_exit);
 956
 957 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 958 MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
 959 MODULE_LICENSE("GPL v2");
 960 MODULE_ALIAS("platform:pinctrl-merrifield");