1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #ifndef PINCTRL_INTEL_H
11 #define PINCTRL_INTEL_H
13 struct pinctrl_pin_desc;
14 struct platform_device;
18 * struct intel_pingroup - Description about group of pins
19 * @name: Name of the groups
20 * @pins: All pins in this group
21 * @npins: Number of pins in this groups
22 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
24 * @modes: If not %NULL this will hold mode for each pin in @pins
26 struct intel_pingroup {
31 const unsigned *modes;
35 * struct intel_function - Description about a function
36 * @name: Name of the function
37 * @groups: An array of groups for this function
38 * @ngroups: Number of groups in @groups
40 struct intel_function {
42 const char * const *groups;
47 * struct intel_padgroup - Hardware pad group information
48 * @reg_num: GPI_IS register number
49 * @base: Starting pin of this group
50 * @size: Size of this group (maximum is 32).
51 * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
52 * and %-1 if no GPIO mapping should be created)
53 * @padown_num: PAD_OWN register number (assigned by the core driver)
55 * If pad groups of a community are not the same size, use this structure
58 struct intel_padgroup {
67 * struct intel_community - Intel pin community description
68 * @barno: MMIO BAR number where registers for this community reside
69 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
70 * then there is no support for owner.
71 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
72 * locking is not supported.
73 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
74 * is assumed that the host owns the pin (rather than
76 * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
78 * @ie_offset: Register offset of GPI_IE from @regs.
79 * @pin_base: Starting pin of pins in this community
80 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
81 * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
82 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
83 * minimum. Use %0 if the number of registers can be
84 * determined by the size of the group.
85 * @npins: Number of pins in this community
86 * @features: Additional features supported by the hardware
87 * @gpps: Pad groups if the controller has variable size pad groups
88 * @ngpps: Number of pad groups in this community
89 * @regs: Community specific common registers (reserved for core driver)
90 * @pad_regs: Community specific pad registers (reserved for core driver)
92 * Most Intel GPIO host controllers this driver supports each pad group is
93 * of equal size (except the last one). In that case the driver can just
94 * fill in @gpp_size field and let the core driver to handle the rest. If
95 * the controller has pad groups of variable size the client driver can
96 * pass custom @gpps and @ngpps instead.
98 struct intel_community {
100 unsigned padown_offset;
101 unsigned padcfglock_offset;
102 unsigned hostown_offset;
107 unsigned gpp_num_padown_regs;
110 const struct intel_padgroup *gpps;
112 /* Reserved for the core driver */
114 void __iomem *pad_regs;
117 /* Additional features supported by the hardware */
118 #define PINCTRL_FEATURE_DEBOUNCE BIT(0)
119 #define PINCTRL_FEATURE_1K_PD BIT(1)
122 * PIN_GROUP - Declare a pin group
123 * @n: Name of the group
124 * @p: An array of pins this group consists
125 * @m: Mode which the pins are put when this group is active. Can be either
126 * a single integer or an array of integers in which case mode is per
129 #define PIN_GROUP(n, p, m) \
133 .npins = ARRAY_SIZE((p)), \
134 .mode = __builtin_choose_expr( \
135 __builtin_constant_p((m)), (m), 0), \
136 .modes = __builtin_choose_expr( \
137 __builtin_constant_p((m)), NULL, (m)), \
140 #define FUNCTION(n, g) \
144 .ngroups = ARRAY_SIZE((g)), \
148 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
149 * @uid: ACPI _UID for the probe driver use if needed
150 * @pins: Array if pins this pinctrl controls
151 * @npins: Number of pins in the array
152 * @groups: Array of pin groups
153 * @ngroups: Number of groups in the array
154 * @functions: Array of functions
155 * @nfunctions: Number of functions in the array
156 * @communities: Array of communities this pinctrl handles
157 * @ncommunities: Number of communities in the array
159 * The @communities is used as a template by the core driver. It will make
160 * copy of all communities and fill in rest of the information.
162 struct intel_pinctrl_soc_data {
164 const struct pinctrl_pin_desc *pins;
166 const struct intel_pingroup *groups;
168 const struct intel_function *functions;
170 const struct intel_community *communities;
174 int intel_pinctrl_probe(struct platform_device *pdev,
175 const struct intel_pinctrl_soc_data *soc_data);
176 #ifdef CONFIG_PM_SLEEP
177 int intel_pinctrl_suspend(struct device *dev);
178 int intel_pinctrl_resume(struct device *dev);
181 #endif /* PINCTRL_INTEL_H */