drivers/pinctrl/intel/pinctrl-intel.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel pinctrl/GPIO core driver.
   4  *
   5  * Copyright (C) 2015, Intel Corporation
   6  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/gpio/driver.h>
  13 #include <linux/log2.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pinctrl/pinctrl.h>
  16 #include <linux/pinctrl/pinmux.h>
  17 #include <linux/pinctrl/pinconf.h>
  18 #include <linux/pinctrl/pinconf-generic.h>
  19
  20 #include "../core.h"
  21 #include "pinctrl-intel.h"
  22
  23 /* Offset from regs */
  24 #define REVID                           0x000
  25 #define REVID_SHIFT                     16
  26 #define REVID_MASK                      GENMASK(31, 16)
  27
  28 #define PADBAR                          0x00c
  29 #define GPI_IS                          0x100
  30
  31 #define PADOWN_BITS                     4
  32 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  33 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  34 #define PADOWN_GPP(p)                   ((p) / 8)
  35
  36 /* Offset from pad_regs */
  37 #define PADCFG0                         0x000
  38 #define PADCFG0_RXEVCFG_SHIFT           25
  39 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  40 #define PADCFG0_RXEVCFG_LEVEL           0
  41 #define PADCFG0_RXEVCFG_EDGE            1
  42 #define PADCFG0_RXEVCFG_DISABLED        2
  43 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  44 #define PADCFG0_PREGFRXSEL              BIT(24)
  45 #define PADCFG0_RXINV                   BIT(23)
  46 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  47 #define PADCFG0_GPIROUTSCI              BIT(19)
  48 #define PADCFG0_GPIROUTSMI              BIT(18)
  49 #define PADCFG0_GPIROUTNMI              BIT(17)
  50 #define PADCFG0_PMODE_SHIFT             10
  51 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  52 #define PADCFG0_GPIORXDIS               BIT(9)
  53 #define PADCFG0_GPIOTXDIS               BIT(8)
  54 #define PADCFG0_GPIORXSTATE             BIT(1)
  55 #define PADCFG0_GPIOTXSTATE             BIT(0)
  56
  57 #define PADCFG1                         0x004
  58 #define PADCFG1_TERM_UP                 BIT(13)
  59 #define PADCFG1_TERM_SHIFT              10
  60 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  61 #define PADCFG1_TERM_20K                4
  62 #define PADCFG1_TERM_2K                 3
  63 #define PADCFG1_TERM_5K                 2
  64 #define PADCFG1_TERM_1K                 1
  65
  66 #define PADCFG2                         0x008
  67 #define PADCFG2_DEBEN                   BIT(0)
  68 #define PADCFG2_DEBOUNCE_SHIFT          1
  69 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  70
  71 #define DEBOUNCE_PERIOD                 31250 /* ns */
  72
  73 struct intel_pad_context {
  74         u32 padcfg0;
  75         u32 padcfg1;
  76         u32 padcfg2;
  77 };
  78
  79 struct intel_community_context {
  80         u32 *intmask;
  81 };
  82
  83 struct intel_pinctrl_context {
  84         struct intel_pad_context *pads;
  85         struct intel_community_context *communities;
  86 };
  87
  88 /**
  89  * struct intel_pinctrl - Intel pinctrl private structure
  90  * @dev: Pointer to the device structure
  91  * @lock: Lock to serialize register access
  92  * @pctldesc: Pin controller description
  93  * @pctldev: Pointer to the pin controller device
  94  * @chip: GPIO chip in this pin controller
  95  * @soc: SoC/PCH specific pin configuration data
  96  * @communities: All communities in this pin controller
  97  * @ncommunities: Number of communities in this pin controller
  98  * @context: Configuration saved over system sleep
  99  * @irq: pinctrl/GPIO chip irq number
 100  */
 101 struct intel_pinctrl {
 102         struct device *dev;
 103         raw_spinlock_t lock;
 104         struct pinctrl_desc pctldesc;
 105         struct pinctrl_dev *pctldev;
 106         struct gpio_chip chip;
 107         const struct intel_pinctrl_soc_data *soc;
 108         struct intel_community *communities;
 109         size_t ncommunities;
 110         struct intel_pinctrl_context context;
 111         int irq;
 112 };
 113
 114 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 115 #define padgroup_offset(g, p)   ((p) - (g)->base)
 116
 117 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 118                                                    unsigned pin)
 119 {
 120         struct intel_community *community;
 121         int i;
 122
 123         for (i = 0; i < pctrl->ncommunities; i++) {
 124                 community = &pctrl->communities[i];
 125                 if (pin >= community->pin_base &&
 126                     pin < community->pin_base + community->npins)
 127                         return community;
 128         }
 129
 130         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 131         return NULL;
 132 }
 133
 134 static const struct intel_padgroup *
 135 intel_community_get_padgroup(const struct intel_community *community,
 136                              unsigned pin)
 137 {
 138         int i;
 139
 140         for (i = 0; i < community->ngpps; i++) {
 141                 const struct intel_padgroup *padgrp = &community->gpps[i];
 142
 143                 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
 144                         return padgrp;
 145         }
 146
 147         return NULL;
 148 }
 149
 150 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 151                                       unsigned reg)
 152 {
 153         const struct intel_community *community;
 154         unsigned padno;
 155         size_t nregs;
 156
 157         community = intel_get_community(pctrl, pin);
 158         if (!community)
 159                 return NULL;
 160
 161         padno = pin_to_padno(community, pin);
 162         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 163
 164         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 165                 return NULL;
 166
 167         return community->pad_regs + reg + padno * nregs * 4;
 168 }
 169
 170 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 171 {
 172         const struct intel_community *community;
 173         const struct intel_padgroup *padgrp;
 174         unsigned gpp, offset, gpp_offset;
 175         void __iomem *padown;
 176
 177         community = intel_get_community(pctrl, pin);
 178         if (!community)
 179                 return false;
 180         if (!community->padown_offset)
 181                 return true;
 182
 183         padgrp = intel_community_get_padgroup(community, pin);
 184         if (!padgrp)
 185                 return false;
 186
 187         gpp_offset = padgroup_offset(padgrp, pin);
 188         gpp = PADOWN_GPP(gpp_offset);
 189         offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
 190         padown = community->regs + offset;
 191
 192         return !(readl(padown) & PADOWN_MASK(gpp_offset));
 193 }
 194
 195 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 196 {
 197         const struct intel_community *community;
 198         const struct intel_padgroup *padgrp;
 199         unsigned offset, gpp_offset;
 200         void __iomem *hostown;
 201
 202         community = intel_get_community(pctrl, pin);
 203         if (!community)
 204                 return true;
 205         if (!community->hostown_offset)
 206                 return false;
 207
 208         padgrp = intel_community_get_padgroup(community, pin);
 209         if (!padgrp)
 210                 return true;
 211
 212         gpp_offset = padgroup_offset(padgrp, pin);
 213         offset = community->hostown_offset + padgrp->reg_num * 4;
 214         hostown = community->regs + offset;
 215
 216         return !(readl(hostown) & BIT(gpp_offset));
 217 }
 218
 219 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 220 {
 221         struct intel_community *community;
 222         const struct intel_padgroup *padgrp;
 223         unsigned offset, gpp_offset;
 224         u32 value;
 225
 226         community = intel_get_community(pctrl, pin);
 227         if (!community)
 228                 return true;
 229         if (!community->padcfglock_offset)
 230                 return false;
 231
 232         padgrp = intel_community_get_padgroup(community, pin);
 233         if (!padgrp)
 234                 return true;
 235
 236         gpp_offset = padgroup_offset(padgrp, pin);
 237
 238         /*
 239          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 240          * the pad is considered unlocked. Any other case means that it is
 241          * either fully or partially locked and we don't touch it.
 242          */
 243         offset = community->padcfglock_offset + padgrp->reg_num * 8;
 244         value = readl(community->regs + offset);
 245         if (value & BIT(gpp_offset))
 246                 return true;
 247
 248         offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
 249         value = readl(community->regs + offset);
 250         if (value & BIT(gpp_offset))
 251                 return true;
 252
 253         return false;
 254 }
 255
 256 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 257 {
 258         return intel_pad_owned_by_host(pctrl, pin) &&
 259                 !intel_pad_locked(pctrl, pin);
 260 }
 261
 262 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 263 {
 264         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 265
 266         return pctrl->soc->ngroups;
 267 }
 268
 269 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 270                                       unsigned group)
 271 {
 272         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 273
 274         return pctrl->soc->groups[group].name;
 275 }
 276
 277 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 278                               const unsigned **pins, unsigned *npins)
 279 {
 280         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 281
 282         *pins = pctrl->soc->groups[group].pins;
 283         *npins = pctrl->soc->groups[group].npins;
 284         return 0;
 285 }
 286
 287 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 288                                unsigned pin)
 289 {
 290         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 291         void __iomem *padcfg;
 292         u32 cfg0, cfg1, mode;
 293         bool locked, acpi;
 294
 295         if (!intel_pad_owned_by_host(pctrl, pin)) {
 296                 seq_puts(s, "not available");
 297                 return;
 298         }
 299
 300         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 301         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 302
 303         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 304         if (!mode)
 305                 seq_puts(s, "GPIO ");
 306         else
 307                 seq_printf(s, "mode %d ", mode);
 308
 309         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 310
 311         /* Dump the additional PADCFG registers if available */
 312         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 313         if (padcfg)
 314                 seq_printf(s, " 0x%08x", readl(padcfg));
 315
 316         locked = intel_pad_locked(pctrl, pin);
 317         acpi = intel_pad_acpi_mode(pctrl, pin);
 318
 319         if (locked || acpi) {
 320                 seq_puts(s, " [");
 321                 if (locked) {
 322                         seq_puts(s, "LOCKED");
 323                         if (acpi)
 324                                 seq_puts(s, ", ");
 325                 }
 326                 if (acpi)
 327                         seq_puts(s, "ACPI");
 328                 seq_puts(s, "]");
 329         }
 330 }
 331
 332 static const struct pinctrl_ops intel_pinctrl_ops = {
 333         .get_groups_count = intel_get_groups_count,
 334         .get_group_name = intel_get_group_name,
 335         .get_group_pins = intel_get_group_pins,
 336         .pin_dbg_show = intel_pin_dbg_show,
 337 };
 338
 339 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 340 {
 341         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 342
 343         return pctrl->soc->nfunctions;
 344 }
 345
 346 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 347                                            unsigned function)
 348 {
 349         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 350
 351         return pctrl->soc->functions[function].name;
 352 }
 353
 354 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 355                                      unsigned function,
 356                                      const char * const **groups,
 357                                      unsigned * const ngroups)
 358 {
 359         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 360
 361         *groups = pctrl->soc->functions[function].groups;
 362         *ngroups = pctrl->soc->functions[function].ngroups;
 363         return 0;
 364 }
 365
 366 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 367                                 unsigned group)
 368 {
 369         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 370         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 371         unsigned long flags;
 372         int i;
 373
 374         raw_spin_lock_irqsave(&pctrl->lock, flags);
 375
 376         /*
 377          * All pins in the groups needs to be accessible and writable
 378          * before we can enable the mux for this group.
 379          */
 380         for (i = 0; i < grp->npins; i++) {
 381                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 382                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 383                         return -EBUSY;
 384                 }
 385         }
 386
 387         /* Now enable the mux setting for each pin in the group */
 388         for (i = 0; i < grp->npins; i++) {
 389                 void __iomem *padcfg0;
 390                 u32 value;
 391
 392                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 393                 value = readl(padcfg0);
 394
 395                 value &= ~PADCFG0_PMODE_MASK;
 396
 397                 if (grp->modes)
 398                         value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
 399                 else
 400                         value |= grp->mode << PADCFG0_PMODE_SHIFT;
 401
 402                 writel(value, padcfg0);
 403         }
 404
 405         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 406
 407         return 0;
 408 }
 409
 410 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 411 {
 412         u32 value;
 413
 414         value = readl(padcfg0);
 415         if (input) {
 416                 value &= ~PADCFG0_GPIORXDIS;
 417                 value |= PADCFG0_GPIOTXDIS;
 418         } else {
 419                 value &= ~PADCFG0_GPIOTXDIS;
 420                 value |= PADCFG0_GPIORXDIS;
 421         }
 422         writel(value, padcfg0);
 423 }
 424
 425 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
 426 {
 427         u32 value;
 428
 429         /* Put the pad into GPIO mode */
 430         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 431         /* Disable SCI/SMI/NMI generation */
 432         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 433         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 434         writel(value, padcfg0);
 435 }
 436
 437 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 438                                      struct pinctrl_gpio_range *range,
 439                                      unsigned pin)
 440 {
 441         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 442         void __iomem *padcfg0;
 443         unsigned long flags;
 444
 445         raw_spin_lock_irqsave(&pctrl->lock, flags);
 446
 447         if (!intel_pad_usable(pctrl, pin)) {
 448                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 449                 return -EBUSY;
 450         }
 451
 452         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 453         intel_gpio_set_gpio_mode(padcfg0);
 454         /* Disable TX buffer and enable RX (this will be input) */
 455         __intel_gpio_set_direction(padcfg0, true);
 456
 457         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 458
 459         return 0;
 460 }
 461
 462 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 463                                     struct pinctrl_gpio_range *range,
 464                                     unsigned pin, bool input)
 465 {
 466         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 467         void __iomem *padcfg0;
 468         unsigned long flags;
 469
 470         raw_spin_lock_irqsave(&pctrl->lock, flags);
 471
 472         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 473         __intel_gpio_set_direction(padcfg0, input);
 474
 475         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 476
 477         return 0;
 478 }
 479
 480 static const struct pinmux_ops intel_pinmux_ops = {
 481         .get_functions_count = intel_get_functions_count,
 482         .get_function_name = intel_get_function_name,
 483         .get_function_groups = intel_get_function_groups,
 484         .set_mux = intel_pinmux_set_mux,
 485         .gpio_request_enable = intel_gpio_request_enable,
 486         .gpio_set_direction = intel_gpio_set_direction,
 487 };
 488
 489 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 490                             unsigned long *config)
 491 {
 492         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 493         enum pin_config_param param = pinconf_to_config_param(*config);
 494         const struct intel_community *community;
 495         u32 value, term;
 496         u32 arg = 0;
 497
 498         if (!intel_pad_owned_by_host(pctrl, pin))
 499                 return -ENOTSUPP;
 500
 501         community = intel_get_community(pctrl, pin);
 502         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 503         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 504
 505         switch (param) {
 506         case PIN_CONFIG_BIAS_DISABLE:
 507                 if (term)
 508                         return -EINVAL;
 509                 break;
 510
 511         case PIN_CONFIG_BIAS_PULL_UP:
 512                 if (!term || !(value & PADCFG1_TERM_UP))
 513                         return -EINVAL;
 514
 515                 switch (term) {
 516                 case PADCFG1_TERM_1K:
 517                         arg = 1000;
 518                         break;
 519                 case PADCFG1_TERM_2K:
 520                         arg = 2000;
 521                         break;
 522                 case PADCFG1_TERM_5K:
 523                         arg = 5000;
 524                         break;
 525                 case PADCFG1_TERM_20K:
 526                         arg = 20000;
 527                         break;
 528                 }
 529
 530                 break;
 531
 532         case PIN_CONFIG_BIAS_PULL_DOWN:
 533                 if (!term || value & PADCFG1_TERM_UP)
 534                         return -EINVAL;
 535
 536                 switch (term) {
 537                 case PADCFG1_TERM_1K:
 538                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 539                                 return -EINVAL;
 540                         arg = 1000;
 541                         break;
 542                 case PADCFG1_TERM_5K:
 543                         arg = 5000;
 544                         break;
 545                 case PADCFG1_TERM_20K:
 546                         arg = 20000;
 547                         break;
 548                 }
 549
 550                 break;
 551
 552         case PIN_CONFIG_INPUT_DEBOUNCE: {
 553                 void __iomem *padcfg2;
 554                 u32 v;
 555
 556                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 557                 if (!padcfg2)
 558                         return -ENOTSUPP;
 559
 560                 v = readl(padcfg2);
 561                 if (!(v & PADCFG2_DEBEN))
 562                         return -EINVAL;
 563
 564                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 565                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 566
 567                 break;
 568         }
 569
 570         default:
 571                 return -ENOTSUPP;
 572         }
 573
 574         *config = pinconf_to_config_packed(param, arg);
 575         return 0;
 576 }
 577
 578 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 579                                  unsigned long config)
 580 {
 581         unsigned param = pinconf_to_config_param(config);
 582         unsigned arg = pinconf_to_config_argument(config);
 583         const struct intel_community *community;
 584         void __iomem *padcfg1;
 585         unsigned long flags;
 586         int ret = 0;
 587         u32 value;
 588
 589         raw_spin_lock_irqsave(&pctrl->lock, flags);
 590
 591         community = intel_get_community(pctrl, pin);
 592         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 593         value = readl(padcfg1);
 594
 595         switch (param) {
 596         case PIN_CONFIG_BIAS_DISABLE:
 597                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 598                 break;
 599
 600         case PIN_CONFIG_BIAS_PULL_UP:
 601                 value &= ~PADCFG1_TERM_MASK;
 602
 603                 value |= PADCFG1_TERM_UP;
 604
 605                 switch (arg) {
 606                 case 20000:
 607                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 608                         break;
 609                 case 5000:
 610                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 611                         break;
 612                 case 2000:
 613                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 614                         break;
 615                 case 1000:
 616                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 617                         break;
 618                 default:
 619                         ret = -EINVAL;
 620                 }
 621
 622                 break;
 623
 624         case PIN_CONFIG_BIAS_PULL_DOWN:
 625                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 626
 627                 switch (arg) {
 628                 case 20000:
 629                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 630                         break;
 631                 case 5000:
 632                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 633                         break;
 634                 case 1000:
 635                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 636                                 ret = -EINVAL;
 637                                 break;
 638                         }
 639                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 640                         break;
 641                 default:
 642                         ret = -EINVAL;
 643                 }
 644
 645                 break;
 646         }
 647
 648         if (!ret)
 649                 writel(value, padcfg1);
 650
 651         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 652
 653         return ret;
 654 }
 655
 656 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
 657                                      unsigned debounce)
 658 {
 659         void __iomem *padcfg0, *padcfg2;
 660         unsigned long flags;
 661         u32 value0, value2;
 662         int ret = 0;
 663
 664         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 665         if (!padcfg2)
 666                 return -ENOTSUPP;
 667
 668         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 669
 670         raw_spin_lock_irqsave(&pctrl->lock, flags);
 671
 672         value0 = readl(padcfg0);
 673         value2 = readl(padcfg2);
 674
 675         /* Disable glitch filter and debouncer */
 676         value0 &= ~PADCFG0_PREGFRXSEL;
 677         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 678
 679         if (debounce) {
 680                 unsigned long v;
 681
 682                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 683                 if (v < 3 || v > 15) {
 684                         ret = -EINVAL;
 685                         goto exit_unlock;
 686                 } else {
 687                         /* Enable glitch filter and debouncer */
 688                         value0 |= PADCFG0_PREGFRXSEL;
 689                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 690                         value2 |= PADCFG2_DEBEN;
 691                 }
 692         }
 693
 694         writel(value0, padcfg0);
 695         writel(value2, padcfg2);
 696
 697 exit_unlock:
 698         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 699
 700         return ret;
 701 }
 702
 703 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 704                           unsigned long *configs, unsigned nconfigs)
 705 {
 706         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 707         int i, ret;
 708
 709         if (!intel_pad_usable(pctrl, pin))
 710                 return -ENOTSUPP;
 711
 712         for (i = 0; i < nconfigs; i++) {
 713                 switch (pinconf_to_config_param(configs[i])) {
 714                 case PIN_CONFIG_BIAS_DISABLE:
 715                 case PIN_CONFIG_BIAS_PULL_UP:
 716                 case PIN_CONFIG_BIAS_PULL_DOWN:
 717                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 718                         if (ret)
 719                                 return ret;
 720                         break;
 721
 722                 case PIN_CONFIG_INPUT_DEBOUNCE:
 723                         ret = intel_config_set_debounce(pctrl, pin,
 724                                 pinconf_to_config_argument(configs[i]));
 725                         if (ret)
 726                                 return ret;
 727                         break;
 728
 729                 default:
 730                         return -ENOTSUPP;
 731                 }
 732         }
 733
 734         return 0;
 735 }
 736
 737 static const struct pinconf_ops intel_pinconf_ops = {
 738         .is_generic = true,
 739         .pin_config_get = intel_config_get,
 740         .pin_config_set = intel_config_set,
 741 };
 742
 743 static const struct pinctrl_desc intel_pinctrl_desc = {
 744         .pctlops = &intel_pinctrl_ops,
 745         .pmxops = &intel_pinmux_ops,
 746         .confops = &intel_pinconf_ops,
 747         .owner = THIS_MODULE,
 748 };
 749
 750 /**
 751  * intel_gpio_to_pin() - Translate from GPIO offset to pin number
 752  * @pctrl: Pinctrl structure
 753  * @offset: GPIO offset from gpiolib
 754  * @commmunity: Community is filled here if not %NULL
 755  * @padgrp: Pad group is filled here if not %NULL
 756  *
 757  * When coming through gpiolib irqchip, the GPIO offset is not
 758  * automatically translated to pinctrl pin number. This function can be
 759  * used to find out the corresponding pinctrl pin.
 760  */
 761 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
 762                              const struct intel_community **community,
 763                              const struct intel_padgroup **padgrp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < pctrl->ncommunities; i++) {
 768                 const struct intel_community *comm = &pctrl->communities[i];
 769                 int j;
 770
 771                 for (j = 0; j < comm->ngpps; j++) {
 772                         const struct intel_padgroup *pgrp = &comm->gpps[j];
 773
 774                         if (pgrp->gpio_base < 0)
 775                                 continue;
 776
 777                         if (offset >= pgrp->gpio_base &&
 778                             offset < pgrp->gpio_base + pgrp->size) {
 779                                 int pin;
 780
 781                                 pin = pgrp->base + offset - pgrp->gpio_base;
 782                                 if (community)
 783                                         *community = comm;
 784                                 if (padgrp)
 785                                         *padgrp = pgrp;
 786
 787                                 return pin;
 788                         }
 789                 }
 790         }
 791
 792         return -EINVAL;
 793 }
 794
 795 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 796 {
 797         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 798         void __iomem *reg;
 799         u32 padcfg0;
 800         int pin;
 801
 802         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 803         if (pin < 0)
 804                 return -EINVAL;
 805
 806         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 807         if (!reg)
 808                 return -EINVAL;
 809
 810         padcfg0 = readl(reg);
 811         if (!(padcfg0 & PADCFG0_GPIOTXDIS))
 812                 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
 813
 814         return !!(padcfg0 & PADCFG0_GPIORXSTATE);
 815 }
 816
 817 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 818 {
 819         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 820         unsigned long flags;
 821         void __iomem *reg;
 822         u32 padcfg0;
 823         int pin;
 824
 825         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 826         if (pin < 0)
 827                 return;
 828
 829         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 830         if (!reg)
 831                 return;
 832
 833         raw_spin_lock_irqsave(&pctrl->lock, flags);
 834         padcfg0 = readl(reg);
 835         if (value)
 836                 padcfg0 |= PADCFG0_GPIOTXSTATE;
 837         else
 838                 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 839         writel(padcfg0, reg);
 840         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 841 }
 842
 843 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 844 {
 845         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 846         void __iomem *reg;
 847         u32 padcfg0;
 848         int pin;
 849
 850         pin = intel_gpio_to_pin(pctrl, offset, NULL, NULL);
 851         if (pin < 0)
 852                 return -EINVAL;
 853
 854         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 855         if (!reg)
 856                 return -EINVAL;
 857
 858         padcfg0 = readl(reg);
 859
 860         if (padcfg0 & PADCFG0_PMODE_MASK)
 861                 return -EINVAL;
 862
 863         return !!(padcfg0 & PADCFG0_GPIOTXDIS);
 864 }
 865
 866 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 867 {
 868         return pinctrl_gpio_direction_input(chip->base + offset);
 869 }
 870
 871 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 872                                        int value)
 873 {
 874         intel_gpio_set(chip, offset, value);
 875         return pinctrl_gpio_direction_output(chip->base + offset);
 876 }
 877
 878 static const struct gpio_chip intel_gpio_chip = {
 879         .owner = THIS_MODULE,
 880         .request = gpiochip_generic_request,
 881         .free = gpiochip_generic_free,
 882         .get_direction = intel_gpio_get_direction,
 883         .direction_input = intel_gpio_direction_input,
 884         .direction_output = intel_gpio_direction_output,
 885         .get = intel_gpio_get,
 886         .set = intel_gpio_set,
 887         .set_config = gpiochip_generic_config,
 888 };
 889
 890 static int intel_gpio_irq_reqres(struct irq_data *d)
 891 {
 892         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 893         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 894         int pin;
 895         int ret;
 896
 897         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
 898         if (pin >= 0) {
 899                 ret = gpiochip_lock_as_irq(gc, pin);
 900                 if (ret) {
 901                         dev_err(pctrl->dev, "unable to lock HW IRQ %d for IRQ\n",
 902                                 pin);
 903                         return ret;
 904                 }
 905         }
 906         return 0;
 907 }
 908
 909 static void intel_gpio_irq_relres(struct irq_data *d)
 910 {
 911         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 912         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 913         int pin;
 914
 915         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
 916         if (pin >= 0)
 917                 gpiochip_unlock_as_irq(gc, pin);
 918 }
 919
 920 static void intel_gpio_irq_ack(struct irq_data *d)
 921 {
 922         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 923         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 924         const struct intel_community *community;
 925         const struct intel_padgroup *padgrp;
 926         int pin;
 927
 928         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 929         if (pin >= 0) {
 930                 unsigned gpp, gpp_offset, is_offset;
 931
 932                 gpp = padgrp->reg_num;
 933                 gpp_offset = padgroup_offset(padgrp, pin);
 934                 is_offset = community->is_offset + gpp * 4;
 935
 936                 raw_spin_lock(&pctrl->lock);
 937                 writel(BIT(gpp_offset), community->regs + is_offset);
 938                 raw_spin_unlock(&pctrl->lock);
 939         }
 940 }
 941
 942 static void intel_gpio_irq_enable(struct irq_data *d)
 943 {
 944         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 945         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 946         const struct intel_community *community;
 947         const struct intel_padgroup *padgrp;
 948         int pin;
 949
 950         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 951         if (pin >= 0) {
 952                 unsigned gpp, gpp_offset, is_offset;
 953                 unsigned long flags;
 954                 u32 value;
 955
 956                 gpp = padgrp->reg_num;
 957                 gpp_offset = padgroup_offset(padgrp, pin);
 958                 is_offset = community->is_offset + gpp * 4;
 959
 960                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 961                 /* Clear interrupt status first to avoid unexpected interrupt */
 962                 writel(BIT(gpp_offset), community->regs + is_offset);
 963
 964                 value = readl(community->regs + community->ie_offset + gpp * 4);
 965                 value |= BIT(gpp_offset);
 966                 writel(value, community->regs + community->ie_offset + gpp * 4);
 967                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 968         }
 969 }
 970
 971 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 972 {
 973         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 974         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 975         const struct intel_community *community;
 976         const struct intel_padgroup *padgrp;
 977         int pin;
 978
 979         pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
 980         if (pin >= 0) {
 981                 unsigned gpp, gpp_offset;
 982                 unsigned long flags;
 983                 void __iomem *reg;
 984                 u32 value;
 985
 986                 gpp = padgrp->reg_num;
 987                 gpp_offset = padgroup_offset(padgrp, pin);
 988
 989                 reg = community->regs + community->ie_offset + gpp * 4;
 990
 991                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 992                 value = readl(reg);
 993                 if (mask)
 994                         value &= ~BIT(gpp_offset);
 995                 else
 996                         value |= BIT(gpp_offset);
 997                 writel(value, reg);
 998                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 999         }
1000 }
1001
1002 static void intel_gpio_irq_mask(struct irq_data *d)
1003 {
1004         intel_gpio_irq_mask_unmask(d, true);
1005 }
1006
1007 static void intel_gpio_irq_unmask(struct irq_data *d)
1008 {
1009         intel_gpio_irq_mask_unmask(d, false);
1010 }
1011
1012 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
1013 {
1014         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1015         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1016         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1017         unsigned long flags;
1018         void __iomem *reg;
1019         u32 value;
1020
1021         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
1022         if (!reg)
1023                 return -EINVAL;
1024
1025         /*
1026          * If the pin is in ACPI mode it is still usable as a GPIO but it
1027          * cannot be used as IRQ because GPI_IS status bit will not be
1028          * updated by the host controller hardware.
1029          */
1030         if (intel_pad_acpi_mode(pctrl, pin)) {
1031                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
1032                 return -EPERM;
1033         }
1034
1035         raw_spin_lock_irqsave(&pctrl->lock, flags);
1036
1037         intel_gpio_set_gpio_mode(reg);
1038
1039         value = readl(reg);
1040
1041         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1042
1043         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
1044                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1045         } else if (type & IRQ_TYPE_EDGE_FALLING) {
1046                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1047                 value |= PADCFG0_RXINV;
1048         } else if (type & IRQ_TYPE_EDGE_RISING) {
1049                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1050         } else if (type & IRQ_TYPE_LEVEL_MASK) {
1051                 if (type & IRQ_TYPE_LEVEL_LOW)
1052                         value |= PADCFG0_RXINV;
1053         } else {
1054                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1055         }
1056
1057         writel(value, reg);
1058
1059         if (type & IRQ_TYPE_EDGE_BOTH)
1060                 irq_set_handler_locked(d, handle_edge_irq);
1061         else if (type & IRQ_TYPE_LEVEL_MASK)
1062                 irq_set_handler_locked(d, handle_level_irq);
1063
1064         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1065
1066         return 0;
1067 }
1068
1069 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1070 {
1071         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1072         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1073         unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1074
1075         if (on)
1076                 enable_irq_wake(pctrl->irq);
1077         else
1078                 disable_irq_wake(pctrl->irq);
1079
1080         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1081         return 0;
1082 }
1083
1084 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1085         const struct intel_community *community)
1086 {
1087         struct gpio_chip *gc = &pctrl->chip;
1088         irqreturn_t ret = IRQ_NONE;
1089         int gpp;
1090
1091         for (gpp = 0; gpp < community->ngpps; gpp++) {
1092                 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1093                 unsigned long pending, enabled, gpp_offset;
1094
1095                 pending = readl(community->regs + community->is_offset +
1096                                 padgrp->reg_num * 4);
1097                 enabled = readl(community->regs + community->ie_offset +
1098                                 padgrp->reg_num * 4);
1099
1100                 /* Only interrupts that are enabled */
1101                 pending &= enabled;
1102
1103                 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1104                         unsigned irq;
1105
1106                         irq = irq_find_mapping(gc->irq.domain,
1107                                                padgrp->gpio_base + gpp_offset);
1108                         generic_handle_irq(irq);
1109
1110                         ret |= IRQ_HANDLED;
1111                 }
1112         }
1113
1114         return ret;
1115 }
1116
1117 static irqreturn_t intel_gpio_irq(int irq, void *data)
1118 {
1119         const struct intel_community *community;
1120         struct intel_pinctrl *pctrl = data;
1121         irqreturn_t ret = IRQ_NONE;
1122         int i;
1123
1124         /* Need to check all communities for pending interrupts */
1125         for (i = 0; i < pctrl->ncommunities; i++) {
1126                 community = &pctrl->communities[i];
1127                 ret |= intel_gpio_community_irq_handler(pctrl, community);
1128         }
1129
1130         return ret;
1131 }
1132
1133 static struct irq_chip intel_gpio_irqchip = {
1134         .name = "intel-gpio",
1135         .irq_request_resources = intel_gpio_irq_reqres,
1136         .irq_release_resources = intel_gpio_irq_relres,
1137         .irq_enable = intel_gpio_irq_enable,
1138         .irq_ack = intel_gpio_irq_ack,
1139         .irq_mask = intel_gpio_irq_mask,
1140         .irq_unmask = intel_gpio_irq_unmask,
1141         .irq_set_type = intel_gpio_irq_type,
1142         .irq_set_wake = intel_gpio_irq_wake,
1143         .flags = IRQCHIP_MASK_ON_SUSPEND,
1144 };
1145
1146 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1147                                      const struct intel_community *community)
1148 {
1149         int ret = 0, i;
1150
1151         for (i = 0; i < community->ngpps; i++) {
1152                 const struct intel_padgroup *gpp = &community->gpps[i];
1153
1154                 if (gpp->gpio_base < 0)
1155                         continue;
1156
1157                 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1158                                              gpp->gpio_base, gpp->base,
1159                                              gpp->size);
1160                 if (ret)
1161                         return ret;
1162         }
1163
1164         return ret;
1165 }
1166
1167 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1168 {
1169         const struct intel_community *community;
1170         unsigned ngpio = 0;
1171         int i, j;
1172
1173         for (i = 0; i < pctrl->ncommunities; i++) {
1174                 community = &pctrl->communities[i];
1175                 for (j = 0; j < community->ngpps; j++) {
1176                         const struct intel_padgroup *gpp = &community->gpps[j];
1177
1178                         if (gpp->gpio_base < 0)
1179                                 continue;
1180
1181                         if (gpp->gpio_base + gpp->size > ngpio)
1182                                 ngpio = gpp->gpio_base + gpp->size;
1183                 }
1184         }
1185
1186         return ngpio;
1187 }
1188
1189 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1190 {
1191         int ret, i;
1192
1193         pctrl->chip = intel_gpio_chip;
1194
1195         pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1196         pctrl->chip.label = dev_name(pctrl->dev);
1197         pctrl->chip.parent = pctrl->dev;
1198         pctrl->chip.base = -1;
1199         pctrl->irq = irq;
1200
1201         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1202         if (ret) {
1203                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1204                 return ret;
1205         }
1206
1207         for (i = 0; i < pctrl->ncommunities; i++) {
1208                 struct intel_community *community = &pctrl->communities[i];
1209
1210                 ret = intel_gpio_add_pin_ranges(pctrl, community);
1211                 if (ret) {
1212                         dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1213                         return ret;
1214                 }
1215         }
1216
1217         /*
1218          * We need to request the interrupt here (instead of providing chip
1219          * to the irq directly) because on some platforms several GPIO
1220          * controllers share the same interrupt line.
1221          */
1222         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1223                                IRQF_SHARED | IRQF_NO_THREAD,
1224                                dev_name(pctrl->dev), pctrl);
1225         if (ret) {
1226                 dev_err(pctrl->dev, "failed to request interrupt\n");
1227                 return ret;
1228         }
1229
1230         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1231                                    handle_bad_irq, IRQ_TYPE_NONE);
1232         if (ret) {
1233                 dev_err(pctrl->dev, "failed to add irqchip\n");
1234                 return ret;
1235         }
1236
1237         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1238                                      NULL);
1239         return 0;
1240 }
1241
1242 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1243                                        struct intel_community *community)
1244 {
1245         struct intel_padgroup *gpps;
1246         unsigned npins = community->npins;
1247         unsigned padown_num = 0;
1248         size_t ngpps, i;
1249
1250         if (community->gpps)
1251                 ngpps = community->ngpps;
1252         else
1253                 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1254
1255         gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1256         if (!gpps)
1257                 return -ENOMEM;
1258
1259         for (i = 0; i < ngpps; i++) {
1260                 if (community->gpps) {
1261                         gpps[i] = community->gpps[i];
1262                 } else {
1263                         unsigned gpp_size = community->gpp_size;
1264
1265                         gpps[i].reg_num = i;
1266                         gpps[i].base = community->pin_base + i * gpp_size;
1267                         gpps[i].size = min(gpp_size, npins);
1268                         npins -= gpps[i].size;
1269                 }
1270
1271                 if (gpps[i].size > 32)
1272                         return -EINVAL;
1273
1274                 if (!gpps[i].gpio_base)
1275                         gpps[i].gpio_base = gpps[i].base;
1276
1277                 gpps[i].padown_num = padown_num;
1278
1279                 /*
1280                  * In older hardware the number of padown registers per
1281                  * group is fixed regardless of the group size.
1282                  */
1283                 if (community->gpp_num_padown_regs)
1284                         padown_num += community->gpp_num_padown_regs;
1285                 else
1286                         padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1287         }
1288
1289         community->ngpps = ngpps;
1290         community->gpps = gpps;
1291
1292         return 0;
1293 }
1294
1295 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1296 {
1297 #ifdef CONFIG_PM_SLEEP
1298         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1299         struct intel_community_context *communities;
1300         struct intel_pad_context *pads;
1301         int i;
1302
1303         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1304         if (!pads)
1305                 return -ENOMEM;
1306
1307         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1308                                    sizeof(*communities), GFP_KERNEL);
1309         if (!communities)
1310                 return -ENOMEM;
1311
1312
1313         for (i = 0; i < pctrl->ncommunities; i++) {
1314                 struct intel_community *community = &pctrl->communities[i];
1315                 u32 *intmask;
1316
1317                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1318                                        sizeof(*intmask), GFP_KERNEL);
1319                 if (!intmask)
1320                         return -ENOMEM;
1321
1322                 communities[i].intmask = intmask;
1323         }
1324
1325         pctrl->context.pads = pads;
1326         pctrl->context.communities = communities;
1327 #endif
1328
1329         return 0;
1330 }
1331
1332 int intel_pinctrl_probe(struct platform_device *pdev,
1333                         const struct intel_pinctrl_soc_data *soc_data)
1334 {
1335         struct intel_pinctrl *pctrl;
1336         int i, ret, irq;
1337
1338         if (!soc_data)
1339                 return -EINVAL;
1340
1341         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1342         if (!pctrl)
1343                 return -ENOMEM;
1344
1345         pctrl->dev = &pdev->dev;
1346         pctrl->soc = soc_data;
1347         raw_spin_lock_init(&pctrl->lock);
1348
1349         /*
1350          * Make a copy of the communities which we can use to hold pointers
1351          * to the registers.
1352          */
1353         pctrl->ncommunities = pctrl->soc->ncommunities;
1354         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1355                                   sizeof(*pctrl->communities), GFP_KERNEL);
1356         if (!pctrl->communities)
1357                 return -ENOMEM;
1358
1359         for (i = 0; i < pctrl->ncommunities; i++) {
1360                 struct intel_community *community = &pctrl->communities[i];
1361                 struct resource *res;
1362                 void __iomem *regs;
1363                 u32 padbar;
1364
1365                 *community = pctrl->soc->communities[i];
1366
1367                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1368                                             community->barno);
1369                 regs = devm_ioremap_resource(&pdev->dev, res);
1370                 if (IS_ERR(regs))
1371                         return PTR_ERR(regs);
1372
1373                 /*
1374                  * Determine community features based on the revision if
1375                  * not specified already.
1376                  */
1377                 if (!community->features) {
1378                         u32 rev;
1379
1380                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1381                         if (rev >= 0x94) {
1382                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1383                                 community->features |= PINCTRL_FEATURE_1K_PD;
1384                         }
1385                 }
1386
1387                 /* Read offset of the pad configuration registers */
1388                 padbar = readl(regs + PADBAR);
1389
1390                 community->regs = regs;
1391                 community->pad_regs = regs + padbar;
1392
1393                 if (!community->is_offset)
1394                         community->is_offset = GPI_IS;
1395
1396                 ret = intel_pinctrl_add_padgroups(pctrl, community);
1397                 if (ret)
1398                         return ret;
1399         }
1400
1401         irq = platform_get_irq(pdev, 0);
1402         if (irq < 0) {
1403                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1404                 return irq;
1405         }
1406
1407         ret = intel_pinctrl_pm_init(pctrl);
1408         if (ret)
1409                 return ret;
1410
1411         pctrl->pctldesc = intel_pinctrl_desc;
1412         pctrl->pctldesc.name = dev_name(&pdev->dev);
1413         pctrl->pctldesc.pins = pctrl->soc->pins;
1414         pctrl->pctldesc.npins = pctrl->soc->npins;
1415
1416         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1417                                                pctrl);
1418         if (IS_ERR(pctrl->pctldev)) {
1419                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1420                 return PTR_ERR(pctrl->pctldev);
1421         }
1422
1423         ret = intel_gpio_probe(pctrl, irq);
1424         if (ret)
1425                 return ret;
1426
1427         platform_set_drvdata(pdev, pctrl);
1428
1429         return 0;
1430 }
1431 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1432
1433 #ifdef CONFIG_PM_SLEEP
1434 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1435 {
1436         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1437
1438         if (!pd || !intel_pad_usable(pctrl, pin))
1439                 return false;
1440
1441         /*
1442          * Only restore the pin if it is actually in use by the kernel (or
1443          * by userspace). It is possible that some pins are used by the
1444          * BIOS during resume and those are not always locked down so leave
1445          * them alone.
1446          */
1447         if (pd->mux_owner || pd->gpio_owner ||
1448             gpiochip_line_is_irq(&pctrl->chip, pin))
1449                 return true;
1450
1451         return false;
1452 }
1453
1454 int intel_pinctrl_suspend(struct device *dev)
1455 {
1456         struct platform_device *pdev = to_platform_device(dev);
1457         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1458         struct intel_community_context *communities;
1459         struct intel_pad_context *pads;
1460         int i;
1461
1462         pads = pctrl->context.pads;
1463         for (i = 0; i < pctrl->soc->npins; i++) {
1464                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1465                 void __iomem *padcfg;
1466                 u32 val;
1467
1468                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1469                         continue;
1470
1471                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1472                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1473                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1474                 pads[i].padcfg1 = val;
1475
1476                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1477                 if (padcfg)
1478                         pads[i].padcfg2 = readl(padcfg);
1479         }
1480
1481         communities = pctrl->context.communities;
1482         for (i = 0; i < pctrl->ncommunities; i++) {
1483                 struct intel_community *community = &pctrl->communities[i];
1484                 void __iomem *base;
1485                 unsigned gpp;
1486
1487                 base = community->regs + community->ie_offset;
1488                 for (gpp = 0; gpp < community->ngpps; gpp++)
1489                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1490         }
1491
1492         return 0;
1493 }
1494 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1495
1496 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1497 {
1498         size_t i;
1499
1500         for (i = 0; i < pctrl->ncommunities; i++) {
1501                 const struct intel_community *community;
1502                 void __iomem *base;
1503                 unsigned gpp;
1504
1505                 community = &pctrl->communities[i];
1506                 base = community->regs;
1507
1508                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1509                         /* Mask and clear all interrupts */
1510                         writel(0, base + community->ie_offset + gpp * 4);
1511                         writel(0xffff, base + community->is_offset + gpp * 4);
1512                 }
1513         }
1514 }
1515
1516 int intel_pinctrl_resume(struct device *dev)
1517 {
1518         struct platform_device *pdev = to_platform_device(dev);
1519         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1520         const struct intel_community_context *communities;
1521         const struct intel_pad_context *pads;
1522         int i;
1523
1524         /* Mask all interrupts */
1525         intel_gpio_irq_init(pctrl);
1526
1527         pads = pctrl->context.pads;
1528         for (i = 0; i < pctrl->soc->npins; i++) {
1529                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1530                 void __iomem *padcfg;
1531                 u32 val;
1532
1533                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1534                         continue;
1535
1536                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1537                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1538                 if (val != pads[i].padcfg0) {
1539                         writel(pads[i].padcfg0, padcfg);
1540                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1541                                 desc->number, readl(padcfg));
1542                 }
1543
1544                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1545                 val = readl(padcfg);
1546                 if (val != pads[i].padcfg1) {
1547                         writel(pads[i].padcfg1, padcfg);
1548                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1549                                 desc->number, readl(padcfg));
1550                 }
1551
1552                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1553                 if (padcfg) {
1554                         val = readl(padcfg);
1555                         if (val != pads[i].padcfg2) {
1556                                 writel(pads[i].padcfg2, padcfg);
1557                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1558                                         desc->number, readl(padcfg));
1559                         }
1560                 }
1561         }
1562
1563         communities = pctrl->context.communities;
1564         for (i = 0; i < pctrl->ncommunities; i++) {
1565                 struct intel_community *community = &pctrl->communities[i];
1566                 void __iomem *base;
1567                 unsigned gpp;
1568
1569                 base = community->regs + community->ie_offset;
1570                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1571                         writel(communities[i].intmask[gpp], base + gpp * 4);
1572                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1573                                 readl(base + gpp * 4));
1574                 }
1575         }
1576
1577         return 0;
1578 }
1579 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1580 #endif
1581
1582 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1583 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1584 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1585 MODULE_LICENSE("GPL v2");