1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/log2.h>
14 #include <linux/platform_device.h>
15 #include <linux/pinctrl/pinctrl.h>
16 #include <linux/pinctrl/pinmux.h>
17 #include <linux/pinctrl/pinconf.h>
18 #include <linux/pinctrl/pinconf-generic.h>
21 #include "pinctrl-intel.h"
23 /* Offset from regs */
25 #define REVID_SHIFT 16
26 #define REVID_MASK GENMASK(31, 16)
32 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
34 #define PADOWN_GPP(p) ((p) / 8)
36 /* Offset from pad_regs */
38 #define PADCFG0_RXEVCFG_SHIFT 25
39 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
40 #define PADCFG0_RXEVCFG_LEVEL 0
41 #define PADCFG0_RXEVCFG_EDGE 1
42 #define PADCFG0_RXEVCFG_DISABLED 2
43 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
44 #define PADCFG0_PREGFRXSEL BIT(24)
45 #define PADCFG0_RXINV BIT(23)
46 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
47 #define PADCFG0_GPIROUTSCI BIT(19)
48 #define PADCFG0_GPIROUTSMI BIT(18)
49 #define PADCFG0_GPIROUTNMI BIT(17)
50 #define PADCFG0_PMODE_SHIFT 10
51 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
52 #define PADCFG0_GPIORXDIS BIT(9)
53 #define PADCFG0_GPIOTXDIS BIT(8)
54 #define PADCFG0_GPIORXSTATE BIT(1)
55 #define PADCFG0_GPIOTXSTATE BIT(0)
58 #define PADCFG1_TERM_UP BIT(13)
59 #define PADCFG1_TERM_SHIFT 10
60 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
61 #define PADCFG1_TERM_20K 4
62 #define PADCFG1_TERM_2K 3
63 #define PADCFG1_TERM_5K 2
64 #define PADCFG1_TERM_1K 1
67 #define PADCFG2_DEBEN BIT(0)
68 #define PADCFG2_DEBOUNCE_SHIFT 1
69 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
71 #define DEBOUNCE_PERIOD 31250 /* ns */
73 struct intel_pad_context {
79 struct intel_community_context {
83 struct intel_pinctrl_context {
84 struct intel_pad_context *pads;
85 struct intel_community_context *communities;
89 * struct intel_pinctrl - Intel pinctrl private structure
90 * @dev: Pointer to the device structure
91 * @lock: Lock to serialize register access
92 * @pctldesc: Pin controller description
93 * @pctldev: Pointer to the pin controller device
94 * @chip: GPIO chip in this pin controller
95 * @soc: SoC/PCH specific pin configuration data
96 * @communities: All communities in this pin controller
97 * @ncommunities: Number of communities in this pin controller
98 * @context: Configuration saved over system sleep
99 * @irq: pinctrl/GPIO chip irq number
101 struct intel_pinctrl {
104 struct pinctrl_desc pctldesc;
105 struct pinctrl_dev *pctldev;
106 struct gpio_chip chip;
107 const struct intel_pinctrl_soc_data *soc;
108 struct intel_community *communities;
110 struct intel_pinctrl_context context;
114 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
115 #define padgroup_offset(g, p) ((p) - (g)->base)
117 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
120 struct intel_community *community;
123 for (i = 0; i < pctrl->ncommunities; i++) {
124 community = &pctrl->communities[i];
125 if (pin >= community->pin_base &&
126 pin < community->pin_base + community->npins)
130 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
134 static const struct intel_padgroup *
135 intel_community_get_padgroup(const struct intel_community *community,
140 for (i = 0; i < community->ngpps; i++) {
141 const struct intel_padgroup *padgrp = &community->gpps[i];
143 if (pin >= padgrp->base && pin < padgrp->base + padgrp->size)
150 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
153 const struct intel_community *community;
157 community = intel_get_community(pctrl, pin);
161 padno = pin_to_padno(community, pin);
162 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
164 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
167 return community->pad_regs + reg + padno * nregs * 4;
170 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
172 const struct intel_community *community;
173 const struct intel_padgroup *padgrp;
174 unsigned gpp, offset, gpp_offset;
175 void __iomem *padown;
177 community = intel_get_community(pctrl, pin);
180 if (!community->padown_offset)
183 padgrp = intel_community_get_padgroup(community, pin);
187 gpp_offset = padgroup_offset(padgrp, pin);
188 gpp = PADOWN_GPP(gpp_offset);
189 offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4;
190 padown = community->regs + offset;
192 return !(readl(padown) & PADOWN_MASK(gpp_offset));
195 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
197 const struct intel_community *community;
198 const struct intel_padgroup *padgrp;
199 unsigned offset, gpp_offset;
200 void __iomem *hostown;
202 community = intel_get_community(pctrl, pin);
205 if (!community->hostown_offset)
208 padgrp = intel_community_get_padgroup(community, pin);
212 gpp_offset = padgroup_offset(padgrp, pin);
213 offset = community->hostown_offset + padgrp->reg_num * 4;
214 hostown = community->regs + offset;
216 return !(readl(hostown) & BIT(gpp_offset));
219 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
221 struct intel_community *community;
222 const struct intel_padgroup *padgrp;
223 unsigned offset, gpp_offset;
226 community = intel_get_community(pctrl, pin);
229 if (!community->padcfglock_offset)
232 padgrp = intel_community_get_padgroup(community, pin);
236 gpp_offset = padgroup_offset(padgrp, pin);
239 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
240 * the pad is considered unlocked. Any other case means that it is
241 * either fully or partially locked and we don't touch it.
243 offset = community->padcfglock_offset + padgrp->reg_num * 8;
244 value = readl(community->regs + offset);
245 if (value & BIT(gpp_offset))
248 offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
249 value = readl(community->regs + offset);
250 if (value & BIT(gpp_offset))
256 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
258 return intel_pad_owned_by_host(pctrl, pin) &&
259 !intel_pad_locked(pctrl, pin);
262 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
264 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
266 return pctrl->soc->ngroups;
269 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
272 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
274 return pctrl->soc->groups[group].name;
277 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
278 const unsigned **pins, unsigned *npins)
280 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
282 *pins = pctrl->soc->groups[group].pins;
283 *npins = pctrl->soc->groups[group].npins;
287 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
290 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
291 void __iomem *padcfg;
292 u32 cfg0, cfg1, mode;
295 if (!intel_pad_owned_by_host(pctrl, pin)) {
296 seq_puts(s, "not available");
300 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
301 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
303 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
305 seq_puts(s, "GPIO ");
307 seq_printf(s, "mode %d ", mode);
309 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
311 /* Dump the additional PADCFG registers if available */
312 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
314 seq_printf(s, " 0x%08x", readl(padcfg));
316 locked = intel_pad_locked(pctrl, pin);
317 acpi = intel_pad_acpi_mode(pctrl, pin);
319 if (locked || acpi) {
322 seq_puts(s, "LOCKED");
332 static const struct pinctrl_ops intel_pinctrl_ops = {
333 .get_groups_count = intel_get_groups_count,
334 .get_group_name = intel_get_group_name,
335 .get_group_pins = intel_get_group_pins,
336 .pin_dbg_show = intel_pin_dbg_show,
339 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
341 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
343 return pctrl->soc->nfunctions;
346 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
349 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
351 return pctrl->soc->functions[function].name;
354 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
356 const char * const **groups,
357 unsigned * const ngroups)
359 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
361 *groups = pctrl->soc->functions[function].groups;
362 *ngroups = pctrl->soc->functions[function].ngroups;
366 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
369 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
370 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
374 raw_spin_lock_irqsave(&pctrl->lock, flags);
377 * All pins in the groups needs to be accessible and writable
378 * before we can enable the mux for this group.
380 for (i = 0; i < grp->npins; i++) {
381 if (!intel_pad_usable(pctrl, grp->pins[i])) {
382 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
387 /* Now enable the mux setting for each pin in the group */
388 for (i = 0; i < grp->npins; i++) {
389 void __iomem *padcfg0;
392 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
393 value = readl(padcfg0);
395 value &= ~PADCFG0_PMODE_MASK;
398 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
400 value |= grp->mode << PADCFG0_PMODE_SHIFT;
402 writel(value, padcfg0);
405 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
410 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
414 value = readl(padcfg0);
416 value &= ~PADCFG0_GPIORXDIS;
417 value |= PADCFG0_GPIOTXDIS;
419 value &= ~PADCFG0_GPIOTXDIS;
420 value |= PADCFG0_GPIORXDIS;
422 writel(value, padcfg0);
425 static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
429 /* Put the pad into GPIO mode */
430 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
431 /* Disable SCI/SMI/NMI generation */
432 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
433 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
434 writel(value, padcfg0);
437 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
438 struct pinctrl_gpio_range *range,
441 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
442 void __iomem *padcfg0;
445 raw_spin_lock_irqsave(&pctrl->lock, flags);
447 if (!intel_pad_usable(pctrl, pin)) {
448 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
452 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
453 intel_gpio_set_gpio_mode(padcfg0);
454 /* Disable TX buffer and enable RX (this will be input) */
455 __intel_gpio_set_direction(padcfg0, true);
457 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
462 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
463 struct pinctrl_gpio_range *range,
464 unsigned pin, bool input)
466 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
467 void __iomem *padcfg0;
470 raw_spin_lock_irqsave(&pctrl->lock, flags);
472 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
473 __intel_gpio_set_direction(padcfg0, input);
475 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
480 static const struct pinmux_ops intel_pinmux_ops = {
481 .get_functions_count = intel_get_functions_count,
482 .get_function_name = intel_get_function_name,
483 .get_function_groups = intel_get_function_groups,
484 .set_mux = intel_pinmux_set_mux,
485 .gpio_request_enable = intel_gpio_request_enable,
486 .gpio_set_direction = intel_gpio_set_direction,
489 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
490 unsigned long *config)
492 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
493 enum pin_config_param param = pinconf_to_config_param(*config);
494 const struct intel_community *community;
498 if (!intel_pad_owned_by_host(pctrl, pin))
501 community = intel_get_community(pctrl, pin);
502 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
503 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
506 case PIN_CONFIG_BIAS_DISABLE:
511 case PIN_CONFIG_BIAS_PULL_UP:
512 if (!term || !(value & PADCFG1_TERM_UP))
516 case PADCFG1_TERM_1K:
519 case PADCFG1_TERM_2K:
522 case PADCFG1_TERM_5K:
525 case PADCFG1_TERM_20K:
532 case PIN_CONFIG_BIAS_PULL_DOWN:
533 if (!term || value & PADCFG1_TERM_UP)
537 case PADCFG1_TERM_1K:
538 if (!(community->features & PINCTRL_FEATURE_1K_PD))
542 case PADCFG1_TERM_5K:
545 case PADCFG1_TERM_20K:
552 case PIN_CONFIG_INPUT_DEBOUNCE: {
553 void __iomem *padcfg2;
556 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
561 if (!(v & PADCFG2_DEBEN))
564 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
565 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
574 *config = pinconf_to_config_packed(param, arg);
578 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
579 unsigned long config)
581 unsigned param = pinconf_to_config_param(config);
582 unsigned arg = pinconf_to_config_argument(config);
583 const struct intel_community *community;
584 void __iomem *padcfg1;
589 raw_spin_lock_irqsave(&pctrl->lock, flags);
591 community = intel_get_community(pctrl, pin);
592 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
593 value = readl(padcfg1);
596 case PIN_CONFIG_BIAS_DISABLE:
597 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
600 case PIN_CONFIG_BIAS_PULL_UP:
601 value &= ~PADCFG1_TERM_MASK;
603 value |= PADCFG1_TERM_UP;
607 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
610 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
613 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
616 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
624 case PIN_CONFIG_BIAS_PULL_DOWN:
625 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
629 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
632 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
635 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
639 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
649 writel(value, padcfg1);
651 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
656 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
659 void __iomem *padcfg0, *padcfg2;
664 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
668 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
670 raw_spin_lock_irqsave(&pctrl->lock, flags);
672 value0 = readl(padcfg0);
673 value2 = readl(padcfg2);
675 /* Disable glitch filter and debouncer */
676 value0 &= ~PADCFG0_PREGFRXSEL;
677 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
682 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
683 if (v < 3 || v > 15) {
687 /* Enable glitch filter and debouncer */
688 value0 |= PADCFG0_PREGFRXSEL;
689 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
690 value2 |= PADCFG2_DEBEN;
694 writel(value0, padcfg0);
695 writel(value2, padcfg2);
698 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
703 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
704 unsigned long *configs, unsigned nconfigs)
706 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
709 if (!intel_pad_usable(pctrl, pin))
712 for (i = 0; i < nconfigs; i++) {
713 switch (pinconf_to_config_param(configs[i])) {
714 case PIN_CONFIG_BIAS_DISABLE:
715 case PIN_CONFIG_BIAS_PULL_UP:
716 case PIN_CONFIG_BIAS_PULL_DOWN:
717 ret = intel_config_set_pull(pctrl, pin, configs[i]);
722 case PIN_CONFIG_INPUT_DEBOUNCE:
723 ret = intel_config_set_debounce(pctrl, pin,
724 pinconf_to_config_argument(configs[i]));
737 static const struct pinconf_ops intel_pinconf_ops = {
739 .pin_config_get = intel_config_get,
740 .pin_config_set = intel_config_set,
743 static const struct pinctrl_desc intel_pinctrl_desc = {
744 .pctlops = &intel_pinctrl_ops,
745 .pmxops = &intel_pinmux_ops,
746 .confops = &intel_pinconf_ops,
747 .owner = THIS_MODULE,
750 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
752 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
756 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
760 padcfg0 = readl(reg);
761 if (!(padcfg0 & PADCFG0_GPIOTXDIS))
762 return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
764 return !!(padcfg0 & PADCFG0_GPIORXSTATE);
767 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
769 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
774 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
778 raw_spin_lock_irqsave(&pctrl->lock, flags);
779 padcfg0 = readl(reg);
781 padcfg0 |= PADCFG0_GPIOTXSTATE;
783 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
784 writel(padcfg0, reg);
785 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
788 static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
790 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
794 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
798 padcfg0 = readl(reg);
800 if (padcfg0 & PADCFG0_PMODE_MASK)
803 return !!(padcfg0 & PADCFG0_GPIOTXDIS);
806 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
808 return pinctrl_gpio_direction_input(chip->base + offset);
811 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
814 intel_gpio_set(chip, offset, value);
815 return pinctrl_gpio_direction_output(chip->base + offset);
818 static const struct gpio_chip intel_gpio_chip = {
819 .owner = THIS_MODULE,
820 .request = gpiochip_generic_request,
821 .free = gpiochip_generic_free,
822 .get_direction = intel_gpio_get_direction,
823 .direction_input = intel_gpio_direction_input,
824 .direction_output = intel_gpio_direction_output,
825 .get = intel_gpio_get,
826 .set = intel_gpio_set,
827 .set_config = gpiochip_generic_config,
831 * intel_gpio_to_pin() - Translate from GPIO offset to pin number
832 * @pctrl: Pinctrl structure
833 * @offset: GPIO offset from gpiolib
834 * @commmunity: Community is filled here if not %NULL
835 * @padgrp: Pad group is filled here if not %NULL
837 * When coming through gpiolib irqchip, the GPIO offset is not
838 * automatically translated to pinctrl pin number. This function can be
839 * used to find out the corresponding pinctrl pin.
841 static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
842 const struct intel_community **community,
843 const struct intel_padgroup **padgrp)
847 for (i = 0; i < pctrl->ncommunities; i++) {
848 const struct intel_community *comm = &pctrl->communities[i];
851 for (j = 0; j < comm->ngpps; j++) {
852 const struct intel_padgroup *pgrp = &comm->gpps[j];
854 if (pgrp->gpio_base < 0)
857 if (offset >= pgrp->gpio_base &&
858 offset < pgrp->gpio_base + pgrp->size) {
861 pin = pgrp->base + offset - pgrp->gpio_base;
875 static void intel_gpio_irq_ack(struct irq_data *d)
877 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
878 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
879 const struct intel_community *community;
880 const struct intel_padgroup *padgrp;
883 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
885 unsigned gpp, gpp_offset, is_offset;
887 gpp = padgrp->reg_num;
888 gpp_offset = padgroup_offset(padgrp, pin);
889 is_offset = community->is_offset + gpp * 4;
891 raw_spin_lock(&pctrl->lock);
892 writel(BIT(gpp_offset), community->regs + is_offset);
893 raw_spin_unlock(&pctrl->lock);
897 static void intel_gpio_irq_enable(struct irq_data *d)
899 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
900 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
901 const struct intel_community *community;
902 const struct intel_padgroup *padgrp;
905 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
907 unsigned gpp, gpp_offset, is_offset;
911 gpp = padgrp->reg_num;
912 gpp_offset = padgroup_offset(padgrp, pin);
913 is_offset = community->is_offset + gpp * 4;
915 raw_spin_lock_irqsave(&pctrl->lock, flags);
916 /* Clear interrupt status first to avoid unexpected interrupt */
917 writel(BIT(gpp_offset), community->regs + is_offset);
919 value = readl(community->regs + community->ie_offset + gpp * 4);
920 value |= BIT(gpp_offset);
921 writel(value, community->regs + community->ie_offset + gpp * 4);
922 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
926 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
928 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
929 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
930 const struct intel_community *community;
931 const struct intel_padgroup *padgrp;
934 pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
936 unsigned gpp, gpp_offset;
941 gpp = padgrp->reg_num;
942 gpp_offset = padgroup_offset(padgrp, pin);
944 reg = community->regs + community->ie_offset + gpp * 4;
946 raw_spin_lock_irqsave(&pctrl->lock, flags);
949 value &= ~BIT(gpp_offset);
951 value |= BIT(gpp_offset);
953 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
957 static void intel_gpio_irq_mask(struct irq_data *d)
959 intel_gpio_irq_mask_unmask(d, true);
962 static void intel_gpio_irq_unmask(struct irq_data *d)
964 intel_gpio_irq_mask_unmask(d, false);
967 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
969 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
970 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
971 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
976 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
981 * If the pin is in ACPI mode it is still usable as a GPIO but it
982 * cannot be used as IRQ because GPI_IS status bit will not be
983 * updated by the host controller hardware.
985 if (intel_pad_acpi_mode(pctrl, pin)) {
986 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
990 raw_spin_lock_irqsave(&pctrl->lock, flags);
992 intel_gpio_set_gpio_mode(reg);
996 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
998 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
999 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1000 } else if (type & IRQ_TYPE_EDGE_FALLING) {
1001 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1002 value |= PADCFG0_RXINV;
1003 } else if (type & IRQ_TYPE_EDGE_RISING) {
1004 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1005 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1006 if (type & IRQ_TYPE_LEVEL_LOW)
1007 value |= PADCFG0_RXINV;
1009 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1014 if (type & IRQ_TYPE_EDGE_BOTH)
1015 irq_set_handler_locked(d, handle_edge_irq);
1016 else if (type & IRQ_TYPE_LEVEL_MASK)
1017 irq_set_handler_locked(d, handle_level_irq);
1019 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1024 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
1026 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1027 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1028 unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1031 enable_irq_wake(pctrl->irq);
1033 disable_irq_wake(pctrl->irq);
1035 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
1039 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1040 const struct intel_community *community)
1042 struct gpio_chip *gc = &pctrl->chip;
1043 irqreturn_t ret = IRQ_NONE;
1046 for (gpp = 0; gpp < community->ngpps; gpp++) {
1047 const struct intel_padgroup *padgrp = &community->gpps[gpp];
1048 unsigned long pending, enabled, gpp_offset;
1050 pending = readl(community->regs + community->is_offset +
1051 padgrp->reg_num * 4);
1052 enabled = readl(community->regs + community->ie_offset +
1053 padgrp->reg_num * 4);
1055 /* Only interrupts that are enabled */
1058 for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1061 irq = irq_find_mapping(gc->irq.domain,
1062 padgrp->gpio_base + gpp_offset);
1063 generic_handle_irq(irq);
1072 static irqreturn_t intel_gpio_irq(int irq, void *data)
1074 const struct intel_community *community;
1075 struct intel_pinctrl *pctrl = data;
1076 irqreturn_t ret = IRQ_NONE;
1079 /* Need to check all communities for pending interrupts */
1080 for (i = 0; i < pctrl->ncommunities; i++) {
1081 community = &pctrl->communities[i];
1082 ret |= intel_gpio_community_irq_handler(pctrl, community);
1088 static struct irq_chip intel_gpio_irqchip = {
1089 .name = "intel-gpio",
1090 .irq_enable = intel_gpio_irq_enable,
1091 .irq_ack = intel_gpio_irq_ack,
1092 .irq_mask = intel_gpio_irq_mask,
1093 .irq_unmask = intel_gpio_irq_unmask,
1094 .irq_set_type = intel_gpio_irq_type,
1095 .irq_set_wake = intel_gpio_irq_wake,
1096 .flags = IRQCHIP_MASK_ON_SUSPEND,
1099 static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1100 const struct intel_community *community)
1104 for (i = 0; i < community->ngpps; i++) {
1105 const struct intel_padgroup *gpp = &community->gpps[i];
1107 if (gpp->gpio_base < 0)
1110 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1111 gpp->gpio_base, gpp->base,
1120 static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1122 const struct intel_community *community;
1126 for (i = 0; i < pctrl->ncommunities; i++) {
1127 community = &pctrl->communities[i];
1128 for (j = 0; j < community->ngpps; j++) {
1129 const struct intel_padgroup *gpp = &community->gpps[j];
1131 if (gpp->gpio_base < 0)
1134 if (gpp->gpio_base + gpp->size > ngpio)
1135 ngpio = gpp->gpio_base + gpp->size;
1142 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1146 pctrl->chip = intel_gpio_chip;
1148 pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1149 pctrl->chip.label = dev_name(pctrl->dev);
1150 pctrl->chip.parent = pctrl->dev;
1151 pctrl->chip.base = -1;
1154 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1156 dev_err(pctrl->dev, "failed to register gpiochip\n");
1160 for (i = 0; i < pctrl->ncommunities; i++) {
1161 struct intel_community *community = &pctrl->communities[i];
1163 ret = intel_gpio_add_pin_ranges(pctrl, community);
1165 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1171 * We need to request the interrupt here (instead of providing chip
1172 * to the irq directly) because on some platforms several GPIO
1173 * controllers share the same interrupt line.
1175 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1176 IRQF_SHARED | IRQF_NO_THREAD,
1177 dev_name(pctrl->dev), pctrl);
1179 dev_err(pctrl->dev, "failed to request interrupt\n");
1183 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1184 handle_bad_irq, IRQ_TYPE_NONE);
1186 dev_err(pctrl->dev, "failed to add irqchip\n");
1190 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1195 static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl,
1196 struct intel_community *community)
1198 struct intel_padgroup *gpps;
1199 unsigned npins = community->npins;
1200 unsigned padown_num = 0;
1203 if (community->gpps)
1204 ngpps = community->ngpps;
1206 ngpps = DIV_ROUND_UP(community->npins, community->gpp_size);
1208 gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
1212 for (i = 0; i < ngpps; i++) {
1213 if (community->gpps) {
1214 gpps[i] = community->gpps[i];
1216 unsigned gpp_size = community->gpp_size;
1218 gpps[i].reg_num = i;
1219 gpps[i].base = community->pin_base + i * gpp_size;
1220 gpps[i].size = min(gpp_size, npins);
1221 npins -= gpps[i].size;
1224 if (gpps[i].size > 32)
1227 if (!gpps[i].gpio_base)
1228 gpps[i].gpio_base = gpps[i].base;
1230 gpps[i].padown_num = padown_num;
1233 * In older hardware the number of padown registers per
1234 * group is fixed regardless of the group size.
1236 if (community->gpp_num_padown_regs)
1237 padown_num += community->gpp_num_padown_regs;
1239 padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
1242 community->ngpps = ngpps;
1243 community->gpps = gpps;
1248 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1250 #ifdef CONFIG_PM_SLEEP
1251 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1252 struct intel_community_context *communities;
1253 struct intel_pad_context *pads;
1256 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1260 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1261 sizeof(*communities), GFP_KERNEL);
1266 for (i = 0; i < pctrl->ncommunities; i++) {
1267 struct intel_community *community = &pctrl->communities[i];
1270 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1271 sizeof(*intmask), GFP_KERNEL);
1275 communities[i].intmask = intmask;
1278 pctrl->context.pads = pads;
1279 pctrl->context.communities = communities;
1285 int intel_pinctrl_probe(struct platform_device *pdev,
1286 const struct intel_pinctrl_soc_data *soc_data)
1288 struct intel_pinctrl *pctrl;
1294 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1298 pctrl->dev = &pdev->dev;
1299 pctrl->soc = soc_data;
1300 raw_spin_lock_init(&pctrl->lock);
1303 * Make a copy of the communities which we can use to hold pointers
1306 pctrl->ncommunities = pctrl->soc->ncommunities;
1307 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1308 sizeof(*pctrl->communities), GFP_KERNEL);
1309 if (!pctrl->communities)
1312 for (i = 0; i < pctrl->ncommunities; i++) {
1313 struct intel_community *community = &pctrl->communities[i];
1314 struct resource *res;
1318 *community = pctrl->soc->communities[i];
1320 res = platform_get_resource(pdev, IORESOURCE_MEM,
1322 regs = devm_ioremap_resource(&pdev->dev, res);
1324 return PTR_ERR(regs);
1327 * Determine community features based on the revision if
1328 * not specified already.
1330 if (!community->features) {
1333 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1335 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1336 community->features |= PINCTRL_FEATURE_1K_PD;
1340 /* Read offset of the pad configuration registers */
1341 padbar = readl(regs + PADBAR);
1343 community->regs = regs;
1344 community->pad_regs = regs + padbar;
1346 if (!community->is_offset)
1347 community->is_offset = GPI_IS;
1349 ret = intel_pinctrl_add_padgroups(pctrl, community);
1354 irq = platform_get_irq(pdev, 0);
1356 dev_err(&pdev->dev, "failed to get interrupt number\n");
1360 ret = intel_pinctrl_pm_init(pctrl);
1364 pctrl->pctldesc = intel_pinctrl_desc;
1365 pctrl->pctldesc.name = dev_name(&pdev->dev);
1366 pctrl->pctldesc.pins = pctrl->soc->pins;
1367 pctrl->pctldesc.npins = pctrl->soc->npins;
1369 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1371 if (IS_ERR(pctrl->pctldev)) {
1372 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1373 return PTR_ERR(pctrl->pctldev);
1376 ret = intel_gpio_probe(pctrl, irq);
1380 platform_set_drvdata(pdev, pctrl);
1384 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1386 #ifdef CONFIG_PM_SLEEP
1387 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1389 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1391 if (!pd || !intel_pad_usable(pctrl, pin))
1395 * Only restore the pin if it is actually in use by the kernel (or
1396 * by userspace). It is possible that some pins are used by the
1397 * BIOS during resume and those are not always locked down so leave
1400 if (pd->mux_owner || pd->gpio_owner ||
1401 gpiochip_line_is_irq(&pctrl->chip, pin))
1407 int intel_pinctrl_suspend(struct device *dev)
1409 struct platform_device *pdev = to_platform_device(dev);
1410 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1411 struct intel_community_context *communities;
1412 struct intel_pad_context *pads;
1415 pads = pctrl->context.pads;
1416 for (i = 0; i < pctrl->soc->npins; i++) {
1417 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1418 void __iomem *padcfg;
1421 if (!intel_pinctrl_should_save(pctrl, desc->number))
1424 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1425 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1426 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1427 pads[i].padcfg1 = val;
1429 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1431 pads[i].padcfg2 = readl(padcfg);
1434 communities = pctrl->context.communities;
1435 for (i = 0; i < pctrl->ncommunities; i++) {
1436 struct intel_community *community = &pctrl->communities[i];
1440 base = community->regs + community->ie_offset;
1441 for (gpp = 0; gpp < community->ngpps; gpp++)
1442 communities[i].intmask[gpp] = readl(base + gpp * 4);
1447 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1449 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1453 for (i = 0; i < pctrl->ncommunities; i++) {
1454 const struct intel_community *community;
1458 community = &pctrl->communities[i];
1459 base = community->regs;
1461 for (gpp = 0; gpp < community->ngpps; gpp++) {
1462 /* Mask and clear all interrupts */
1463 writel(0, base + community->ie_offset + gpp * 4);
1464 writel(0xffff, base + community->is_offset + gpp * 4);
1469 int intel_pinctrl_resume(struct device *dev)
1471 struct platform_device *pdev = to_platform_device(dev);
1472 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1473 const struct intel_community_context *communities;
1474 const struct intel_pad_context *pads;
1477 /* Mask all interrupts */
1478 intel_gpio_irq_init(pctrl);
1480 pads = pctrl->context.pads;
1481 for (i = 0; i < pctrl->soc->npins; i++) {
1482 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1483 void __iomem *padcfg;
1486 if (!intel_pinctrl_should_save(pctrl, desc->number))
1489 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1490 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1491 if (val != pads[i].padcfg0) {
1492 writel(pads[i].padcfg0, padcfg);
1493 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1494 desc->number, readl(padcfg));
1497 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1498 val = readl(padcfg);
1499 if (val != pads[i].padcfg1) {
1500 writel(pads[i].padcfg1, padcfg);
1501 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1502 desc->number, readl(padcfg));
1505 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1507 val = readl(padcfg);
1508 if (val != pads[i].padcfg2) {
1509 writel(pads[i].padcfg2, padcfg);
1510 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1511 desc->number, readl(padcfg));
1516 communities = pctrl->context.communities;
1517 for (i = 0; i < pctrl->ncommunities; i++) {
1518 struct intel_community *community = &pctrl->communities[i];
1522 base = community->regs + community->ie_offset;
1523 for (gpp = 0; gpp < community->ngpps; gpp++) {
1524 writel(communities[i].intmask[gpp], base + gpp * 4);
1525 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1526 readl(base + gpp * 4));
1532 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1535 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1536 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1537 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1538 MODULE_LICENSE("GPL v2");