drivers/pinctrl/intel/pinctrl-baytrail.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Pinctrl GPIO driver for Intel Baytrail
   4  *
   5  * Copyright (c) 2012-2013, Intel Corporation
   6  * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/bitops.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/types.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/property.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/string_helpers.h>
  23
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinmux.h>
  26 #include <linux/pinctrl/pinconf.h>
  27 #include <linux/pinctrl/pinconf-generic.h>
  28
  29 #include "pinctrl-intel.h"
  30
  31 /* memory mapped register offsets */
  32 #define BYT_CONF0_REG           0x000
  33 #define BYT_CONF1_REG           0x004
  34 #define BYT_VAL_REG             0x008
  35 #define BYT_DFT_REG             0x00c
  36 #define BYT_INT_STAT_REG        0x800
  37 #define BYT_DIRECT_IRQ_REG      0x980
  38 #define BYT_DEBOUNCE_REG        0x9d0
  39
  40 /* BYT_CONF0_REG register bits */
  41 #define BYT_IODEN               BIT(31)
  42 #define BYT_DIRECT_IRQ_EN       BIT(27)
  43 #define BYT_TRIG_MASK           GENMASK(26, 24)
  44 #define BYT_TRIG_NEG            BIT(26)
  45 #define BYT_TRIG_POS            BIT(25)
  46 #define BYT_TRIG_LVL            BIT(24)
  47 #define BYT_DEBOUNCE_EN         BIT(20)
  48 #define BYT_GLITCH_FILTER_EN    BIT(19)
  49 #define BYT_GLITCH_F_SLOW_CLK   BIT(17)
  50 #define BYT_GLITCH_F_FAST_CLK   BIT(16)
  51 #define BYT_PULL_STR_SHIFT      9
  52 #define BYT_PULL_STR_MASK       GENMASK(10, 9)
  53 #define BYT_PULL_STR_2K         (0 << BYT_PULL_STR_SHIFT)
  54 #define BYT_PULL_STR_10K        (1 << BYT_PULL_STR_SHIFT)
  55 #define BYT_PULL_STR_20K        (2 << BYT_PULL_STR_SHIFT)
  56 #define BYT_PULL_STR_40K        (3 << BYT_PULL_STR_SHIFT)
  57 #define BYT_PULL_ASSIGN_MASK    GENMASK(8, 7)
  58 #define BYT_PULL_ASSIGN_DOWN    BIT(8)
  59 #define BYT_PULL_ASSIGN_UP      BIT(7)
  60 #define BYT_PIN_MUX             GENMASK(2, 0)
  61
  62 /* BYT_VAL_REG register bits */
  63 #define BYT_DIR_MASK            GENMASK(2, 1)
  64 #define BYT_INPUT_EN            BIT(2)  /* 0: input enabled (active low)*/
  65 #define BYT_OUTPUT_EN           BIT(1)  /* 0: output enabled (active low)*/
  66 #define BYT_LEVEL               BIT(0)
  67
  68 #define BYT_CONF0_RESTORE_MASK  (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX)
  69 #define BYT_VAL_RESTORE_MASK    (BYT_DIR_MASK | BYT_LEVEL)
  70
  71 /* BYT_DEBOUNCE_REG bits */
  72 #define BYT_DEBOUNCE_PULSE_MASK         GENMASK(2, 0)
  73 #define BYT_DEBOUNCE_PULSE_375US        1
  74 #define BYT_DEBOUNCE_PULSE_750US        2
  75 #define BYT_DEBOUNCE_PULSE_1500US       3
  76 #define BYT_DEBOUNCE_PULSE_3MS          4
  77 #define BYT_DEBOUNCE_PULSE_6MS          5
  78 #define BYT_DEBOUNCE_PULSE_12MS         6
  79 #define BYT_DEBOUNCE_PULSE_24MS         7
  80
  81 #define BYT_NGPIO_SCORE         102
  82 #define BYT_NGPIO_NCORE         28
  83 #define BYT_NGPIO_SUS           44
  84
  85 #define BYT_SCORE_ACPI_UID      "1"
  86 #define BYT_NCORE_ACPI_UID      "2"
  87 #define BYT_SUS_ACPI_UID        "3"
  88
  89 /*
  90  * This is the function value most pins have for GPIO muxing. If the value
  91  * differs from the default one, it must be explicitly mentioned. Otherwise, the
  92  * pin control implementation will set the muxing value to default GPIO if it
  93  * does not find a match for the requested function.
  94  */
  95 #define BYT_DEFAULT_GPIO_MUX    0
  96 #define BYT_ALTER_GPIO_MUX      1
  97
  98 struct intel_pad_context {
  99         u32 conf0;
 100         u32 val;
 101 };
 102
 103 #define COMMUNITY(p, n, map)            \
 104         {                               \
 105                 .pin_base       = (p),  \
 106                 .npins          = (n),  \
 107                 .pad_map        = (map),\
 108         }
 109
 110 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
 111 static const struct pinctrl_pin_desc byt_score_pins[] = {
 112         PINCTRL_PIN(0, "SATA_GP0"),
 113         PINCTRL_PIN(1, "SATA_GP1"),
 114         PINCTRL_PIN(2, "SATA_LED#"),
 115         PINCTRL_PIN(3, "PCIE_CLKREQ0"),
 116         PINCTRL_PIN(4, "PCIE_CLKREQ1"),
 117         PINCTRL_PIN(5, "PCIE_CLKREQ2"),
 118         PINCTRL_PIN(6, "PCIE_CLKREQ3"),
 119         PINCTRL_PIN(7, "SD3_WP"),
 120         PINCTRL_PIN(8, "HDA_RST"),
 121         PINCTRL_PIN(9, "HDA_SYNC"),
 122         PINCTRL_PIN(10, "HDA_CLK"),
 123         PINCTRL_PIN(11, "HDA_SDO"),
 124         PINCTRL_PIN(12, "HDA_SDI0"),
 125         PINCTRL_PIN(13, "HDA_SDI1"),
 126         PINCTRL_PIN(14, "GPIO_S0_SC14"),
 127         PINCTRL_PIN(15, "GPIO_S0_SC15"),
 128         PINCTRL_PIN(16, "MMC1_CLK"),
 129         PINCTRL_PIN(17, "MMC1_D0"),
 130         PINCTRL_PIN(18, "MMC1_D1"),
 131         PINCTRL_PIN(19, "MMC1_D2"),
 132         PINCTRL_PIN(20, "MMC1_D3"),
 133         PINCTRL_PIN(21, "MMC1_D4"),
 134         PINCTRL_PIN(22, "MMC1_D5"),
 135         PINCTRL_PIN(23, "MMC1_D6"),
 136         PINCTRL_PIN(24, "MMC1_D7"),
 137         PINCTRL_PIN(25, "MMC1_CMD"),
 138         PINCTRL_PIN(26, "MMC1_RST"),
 139         PINCTRL_PIN(27, "SD2_CLK"),
 140         PINCTRL_PIN(28, "SD2_D0"),
 141         PINCTRL_PIN(29, "SD2_D1"),
 142         PINCTRL_PIN(30, "SD2_D2"),
 143         PINCTRL_PIN(31, "SD2_D3_CD"),
 144         PINCTRL_PIN(32, "SD2_CMD"),
 145         PINCTRL_PIN(33, "SD3_CLK"),
 146         PINCTRL_PIN(34, "SD3_D0"),
 147         PINCTRL_PIN(35, "SD3_D1"),
 148         PINCTRL_PIN(36, "SD3_D2"),
 149         PINCTRL_PIN(37, "SD3_D3"),
 150         PINCTRL_PIN(38, "SD3_CD"),
 151         PINCTRL_PIN(39, "SD3_CMD"),
 152         PINCTRL_PIN(40, "SD3_1P8EN"),
 153         PINCTRL_PIN(41, "SD3_PWREN#"),
 154         PINCTRL_PIN(42, "ILB_LPC_AD0"),
 155         PINCTRL_PIN(43, "ILB_LPC_AD1"),
 156         PINCTRL_PIN(44, "ILB_LPC_AD2"),
 157         PINCTRL_PIN(45, "ILB_LPC_AD3"),
 158         PINCTRL_PIN(46, "ILB_LPC_FRAME"),
 159         PINCTRL_PIN(47, "ILB_LPC_CLK0"),
 160         PINCTRL_PIN(48, "ILB_LPC_CLK1"),
 161         PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
 162         PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
 163         PINCTRL_PIN(51, "PCU_SMB_DATA"),
 164         PINCTRL_PIN(52, "PCU_SMB_CLK"),
 165         PINCTRL_PIN(53, "PCU_SMB_ALERT"),
 166         PINCTRL_PIN(54, "ILB_8254_SPKR"),
 167         PINCTRL_PIN(55, "GPIO_S0_SC55"),
 168         PINCTRL_PIN(56, "GPIO_S0_SC56"),
 169         PINCTRL_PIN(57, "GPIO_S0_SC57"),
 170         PINCTRL_PIN(58, "GPIO_S0_SC58"),
 171         PINCTRL_PIN(59, "GPIO_S0_SC59"),
 172         PINCTRL_PIN(60, "GPIO_S0_SC60"),
 173         PINCTRL_PIN(61, "GPIO_S0_SC61"),
 174         PINCTRL_PIN(62, "LPE_I2S2_CLK"),
 175         PINCTRL_PIN(63, "LPE_I2S2_FRM"),
 176         PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
 177         PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
 178         PINCTRL_PIN(66, "SIO_SPI_CS"),
 179         PINCTRL_PIN(67, "SIO_SPI_MISO"),
 180         PINCTRL_PIN(68, "SIO_SPI_MOSI"),
 181         PINCTRL_PIN(69, "SIO_SPI_CLK"),
 182         PINCTRL_PIN(70, "SIO_UART1_RXD"),
 183         PINCTRL_PIN(71, "SIO_UART1_TXD"),
 184         PINCTRL_PIN(72, "SIO_UART1_RTS"),
 185         PINCTRL_PIN(73, "SIO_UART1_CTS"),
 186         PINCTRL_PIN(74, "SIO_UART2_RXD"),
 187         PINCTRL_PIN(75, "SIO_UART2_TXD"),
 188         PINCTRL_PIN(76, "SIO_UART2_RTS"),
 189         PINCTRL_PIN(77, "SIO_UART2_CTS"),
 190         PINCTRL_PIN(78, "SIO_I2C0_DATA"),
 191         PINCTRL_PIN(79, "SIO_I2C0_CLK"),
 192         PINCTRL_PIN(80, "SIO_I2C1_DATA"),
 193         PINCTRL_PIN(81, "SIO_I2C1_CLK"),
 194         PINCTRL_PIN(82, "SIO_I2C2_DATA"),
 195         PINCTRL_PIN(83, "SIO_I2C2_CLK"),
 196         PINCTRL_PIN(84, "SIO_I2C3_DATA"),
 197         PINCTRL_PIN(85, "SIO_I2C3_CLK"),
 198         PINCTRL_PIN(86, "SIO_I2C4_DATA"),
 199         PINCTRL_PIN(87, "SIO_I2C4_CLK"),
 200         PINCTRL_PIN(88, "SIO_I2C5_DATA"),
 201         PINCTRL_PIN(89, "SIO_I2C5_CLK"),
 202         PINCTRL_PIN(90, "SIO_I2C6_DATA"),
 203         PINCTRL_PIN(91, "SIO_I2C6_CLK"),
 204         PINCTRL_PIN(92, "GPIO_S0_SC92"),
 205         PINCTRL_PIN(93, "GPIO_S0_SC93"),
 206         PINCTRL_PIN(94, "SIO_PWM0"),
 207         PINCTRL_PIN(95, "SIO_PWM1"),
 208         PINCTRL_PIN(96, "PMC_PLT_CLK0"),
 209         PINCTRL_PIN(97, "PMC_PLT_CLK1"),
 210         PINCTRL_PIN(98, "PMC_PLT_CLK2"),
 211         PINCTRL_PIN(99, "PMC_PLT_CLK3"),
 212         PINCTRL_PIN(100, "PMC_PLT_CLK4"),
 213         PINCTRL_PIN(101, "PMC_PLT_CLK5"),
 214 };
 215
 216 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
 217         85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
 218         36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
 219         54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
 220         52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
 221         95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
 222         86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
 223         80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
 224         2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
 225         31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
 226         24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
 227         97, 100,
 228 };
 229
 230 /* SCORE groups */
 231 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
 232 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
 233
 234 static const unsigned int byt_score_pwm0_pins[] = { 94 };
 235 static const unsigned int byt_score_pwm1_pins[] = { 95 };
 236
 237 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
 238
 239 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
 240 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
 241 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
 242 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
 243 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
 244 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
 245 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
 246
 247 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
 248 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
 249 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
 250
 251 static const unsigned int byt_score_sdcard_pins[] = {
 252         7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
 253 };
 254 static const unsigned int byt_score_sdcard_mux_values[] = {
 255         2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 256 };
 257
 258 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
 259
 260 static const unsigned int byt_score_emmc_pins[] = {
 261         16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
 262 };
 263
 264 static const unsigned int byt_score_ilb_lpc_pins[] = {
 265         42, 43, 44, 45, 46, 47, 48, 49, 50,
 266 };
 267
 268 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
 269
 270 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
 271 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
 272 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
 273 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
 274 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
 275 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
 276
 277 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
 278
 279 static const struct intel_pingroup byt_score_groups[] = {
 280         PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1),
 281         PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1),
 282         PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1),
 283         PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1),
 284         PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1),
 285         PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1),
 286         PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1),
 287         PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1),
 288         PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1),
 289         PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1),
 290         PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1),
 291         PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1),
 292         PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1),
 293         PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1),
 294         PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1),
 295         PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values),
 296         PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1),
 297         PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1),
 298         PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1),
 299         PIN_GROUP("sata_grp", byt_score_sata_pins, 1),
 300         PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1),
 301         PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1),
 302         PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1),
 303         PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1),
 304         PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1),
 305         PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1),
 306         PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1),
 307 };
 308
 309 static const char * const byt_score_uart_groups[] = {
 310         "uart1_grp", "uart2_grp",
 311 };
 312 static const char * const byt_score_pwm_groups[] = {
 313         "pwm0_grp", "pwm1_grp",
 314 };
 315 static const char * const byt_score_ssp_groups[] = {
 316         "ssp0_grp", "ssp1_grp", "ssp2_grp",
 317 };
 318 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
 319 static const char * const byt_score_i2c_groups[] = {
 320         "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
 321         "i2c6_grp",
 322 };
 323 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
 324 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
 325 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
 326 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
 327 static const char * const byt_score_sata_groups[] = { "sata_grp" };
 328 static const char * const byt_score_plt_clk_groups[] = {
 329         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 330         "plt_clk4_grp", "plt_clk5_grp",
 331 };
 332 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
 333 static const char * const byt_score_gpio_groups[] = {
 334         "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
 335         "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
 336         "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
 337         "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
 338         "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
 339         "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
 340 };
 341
 342 static const struct intel_function byt_score_functions[] = {
 343         FUNCTION("uart", byt_score_uart_groups),
 344         FUNCTION("pwm", byt_score_pwm_groups),
 345         FUNCTION("ssp", byt_score_ssp_groups),
 346         FUNCTION("spi", byt_score_spi_groups),
 347         FUNCTION("i2c", byt_score_i2c_groups),
 348         FUNCTION("sdcard", byt_score_sdcard_groups),
 349         FUNCTION("sdio", byt_score_sdio_groups),
 350         FUNCTION("emmc", byt_score_emmc_groups),
 351         FUNCTION("lpc", byt_score_lpc_groups),
 352         FUNCTION("sata", byt_score_sata_groups),
 353         FUNCTION("plt_clk", byt_score_plt_clk_groups),
 354         FUNCTION("smbus", byt_score_smbus_groups),
 355         FUNCTION("gpio", byt_score_gpio_groups),
 356 };
 357
 358 static const struct intel_community byt_score_communities[] = {
 359         COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
 360 };
 361
 362 static const struct intel_pinctrl_soc_data byt_score_soc_data = {
 363         .uid            = BYT_SCORE_ACPI_UID,
 364         .pins           = byt_score_pins,
 365         .npins          = ARRAY_SIZE(byt_score_pins),
 366         .groups         = byt_score_groups,
 367         .ngroups        = ARRAY_SIZE(byt_score_groups),
 368         .functions      = byt_score_functions,
 369         .nfunctions     = ARRAY_SIZE(byt_score_functions),
 370         .communities    = byt_score_communities,
 371         .ncommunities   = ARRAY_SIZE(byt_score_communities),
 372 };
 373
 374 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>]  */
 375 static const struct pinctrl_pin_desc byt_sus_pins[] = {
 376         PINCTRL_PIN(0, "GPIO_S50"),
 377         PINCTRL_PIN(1, "GPIO_S51"),
 378         PINCTRL_PIN(2, "GPIO_S52"),
 379         PINCTRL_PIN(3, "GPIO_S53"),
 380         PINCTRL_PIN(4, "GPIO_S54"),
 381         PINCTRL_PIN(5, "GPIO_S55"),
 382         PINCTRL_PIN(6, "GPIO_S56"),
 383         PINCTRL_PIN(7, "GPIO_S57"),
 384         PINCTRL_PIN(8, "GPIO_S58"),
 385         PINCTRL_PIN(9, "GPIO_S59"),
 386         PINCTRL_PIN(10, "GPIO_S510"),
 387         PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
 388         PINCTRL_PIN(12, "PMC_SUSCLK0"),
 389         PINCTRL_PIN(13, "GPIO_S513"),
 390         PINCTRL_PIN(14, "USB_ULPI_RST"),
 391         PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
 392         PINCTRL_PIN(16, "PMC_PWRBTN"),
 393         PINCTRL_PIN(17, "GPIO_S517"),
 394         PINCTRL_PIN(18, "PMC_SUS_STAT"),
 395         PINCTRL_PIN(19, "USB_OC0"),
 396         PINCTRL_PIN(20, "USB_OC1"),
 397         PINCTRL_PIN(21, "PCU_SPI_CS1"),
 398         PINCTRL_PIN(22, "GPIO_S522"),
 399         PINCTRL_PIN(23, "GPIO_S523"),
 400         PINCTRL_PIN(24, "GPIO_S524"),
 401         PINCTRL_PIN(25, "GPIO_S525"),
 402         PINCTRL_PIN(26, "GPIO_S526"),
 403         PINCTRL_PIN(27, "GPIO_S527"),
 404         PINCTRL_PIN(28, "GPIO_S528"),
 405         PINCTRL_PIN(29, "GPIO_S529"),
 406         PINCTRL_PIN(30, "GPIO_S530"),
 407         PINCTRL_PIN(31, "USB_ULPI_CLK"),
 408         PINCTRL_PIN(32, "USB_ULPI_DATA0"),
 409         PINCTRL_PIN(33, "USB_ULPI_DATA1"),
 410         PINCTRL_PIN(34, "USB_ULPI_DATA2"),
 411         PINCTRL_PIN(35, "USB_ULPI_DATA3"),
 412         PINCTRL_PIN(36, "USB_ULPI_DATA4"),
 413         PINCTRL_PIN(37, "USB_ULPI_DATA5"),
 414         PINCTRL_PIN(38, "USB_ULPI_DATA6"),
 415         PINCTRL_PIN(39, "USB_ULPI_DATA7"),
 416         PINCTRL_PIN(40, "USB_ULPI_DIR"),
 417         PINCTRL_PIN(41, "USB_ULPI_NXT"),
 418         PINCTRL_PIN(42, "USB_ULPI_STP"),
 419         PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
 420 };
 421
 422 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
 423         29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
 424         18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
 425         0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
 426         26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
 427         52, 53, 59, 40,
 428 };
 429
 430 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
 431 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 };
 432 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 };
 433
 434 static const unsigned int byt_sus_usb_ulpi_pins[] = {
 435         14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 436 };
 437 static const unsigned int byt_sus_usb_ulpi_mode_values[] = {
 438         2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
 439 };
 440 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = {
 441         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 442 };
 443
 444 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
 445 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 };
 446 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 };
 447
 448 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 };
 449 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 };
 450
 451 static const struct intel_pingroup byt_sus_groups[] = {
 452         PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values),
 453         PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values),
 454         PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values),
 455         PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values),
 456         PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values),
 457         PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values),
 458         PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1),
 459         PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1),
 460 };
 461
 462 static const char * const byt_sus_usb_groups[] = {
 463         "usb_oc_grp", "usb_ulpi_grp",
 464 };
 465 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
 466 static const char * const byt_sus_pmu_clk_groups[] = {
 467         "pmu_clk1_grp", "pmu_clk2_grp",
 468 };
 469 static const char * const byt_sus_gpio_groups[] = {
 470         "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio",
 471         "pmu_clk1_grp", "pmu_clk2_grp",
 472 };
 473
 474 static const struct intel_function byt_sus_functions[] = {
 475         FUNCTION("usb", byt_sus_usb_groups),
 476         FUNCTION("spi", byt_sus_spi_groups),
 477         FUNCTION("gpio", byt_sus_gpio_groups),
 478         FUNCTION("pmu_clk", byt_sus_pmu_clk_groups),
 479 };
 480
 481 static const struct intel_community byt_sus_communities[] = {
 482         COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
 483 };
 484
 485 static const struct intel_pinctrl_soc_data byt_sus_soc_data = {
 486         .uid            = BYT_SUS_ACPI_UID,
 487         .pins           = byt_sus_pins,
 488         .npins          = ARRAY_SIZE(byt_sus_pins),
 489         .groups         = byt_sus_groups,
 490         .ngroups        = ARRAY_SIZE(byt_sus_groups),
 491         .functions      = byt_sus_functions,
 492         .nfunctions     = ARRAY_SIZE(byt_sus_functions),
 493         .communities    = byt_sus_communities,
 494         .ncommunities   = ARRAY_SIZE(byt_sus_communities),
 495 };
 496
 497 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
 498         PINCTRL_PIN(0, "HV_DDI0_HPD"),
 499         PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"),
 500         PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"),
 501         PINCTRL_PIN(3, "PANEL0_VDDEN"),
 502         PINCTRL_PIN(4, "PANEL0_BKLTEN"),
 503         PINCTRL_PIN(5, "PANEL0_BKLTCTL"),
 504         PINCTRL_PIN(6, "HV_DDI1_HPD"),
 505         PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"),
 506         PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"),
 507         PINCTRL_PIN(9, "PANEL1_VDDEN"),
 508         PINCTRL_PIN(10, "PANEL1_BKLTEN"),
 509         PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
 510         PINCTRL_PIN(12, "GP_INTD_DSI_TE1"),
 511         PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"),
 512         PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"),
 513         PINCTRL_PIN(15, "GP_CAMERASB00"),
 514         PINCTRL_PIN(16, "GP_CAMERASB01"),
 515         PINCTRL_PIN(17, "GP_CAMERASB02"),
 516         PINCTRL_PIN(18, "GP_CAMERASB03"),
 517         PINCTRL_PIN(19, "GP_CAMERASB04"),
 518         PINCTRL_PIN(20, "GP_CAMERASB05"),
 519         PINCTRL_PIN(21, "GP_CAMERASB06"),
 520         PINCTRL_PIN(22, "GP_CAMERASB07"),
 521         PINCTRL_PIN(23, "GP_CAMERASB08"),
 522         PINCTRL_PIN(24, "GP_CAMERASB09"),
 523         PINCTRL_PIN(25, "GP_CAMERASB10"),
 524         PINCTRL_PIN(26, "GP_CAMERASB11"),
 525         PINCTRL_PIN(27, "GP_INTD_DSI_TE2"),
 526 };
 527
 528 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
 529         19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
 530         14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
 531         3, 6, 10, 13, 2, 5, 9, 7,
 532 };
 533
 534 static const struct intel_community byt_ncore_communities[] = {
 535         COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
 536 };
 537
 538 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = {
 539         .uid            = BYT_NCORE_ACPI_UID,
 540         .pins           = byt_ncore_pins,
 541         .npins          = ARRAY_SIZE(byt_ncore_pins),
 542         .communities    = byt_ncore_communities,
 543         .ncommunities   = ARRAY_SIZE(byt_ncore_communities),
 544 };
 545
 546 static const struct intel_pinctrl_soc_data *byt_soc_data[] = {
 547         &byt_score_soc_data,
 548         &byt_sus_soc_data,
 549         &byt_ncore_soc_data,
 550         NULL
 551 };
 552
 553 static DEFINE_RAW_SPINLOCK(byt_lock);
 554
 555 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
 556                                   int reg)
 557 {
 558         struct intel_community *comm = intel_get_community(vg, offset);
 559         u32 reg_offset;
 560
 561         if (!comm)
 562                 return NULL;
 563
 564         offset -= comm->pin_base;
 565         switch (reg) {
 566         case BYT_INT_STAT_REG:
 567                 reg_offset = (offset / 32) * 4;
 568                 break;
 569         case BYT_DEBOUNCE_REG:
 570                 reg_offset = 0;
 571                 break;
 572         default:
 573                 reg_offset = comm->pad_map[offset] * 16;
 574                 break;
 575         }
 576
 577         return comm->pad_regs + reg_offset + reg;
 578 }
 579
 580 static const struct pinctrl_ops byt_pinctrl_ops = {
 581         .get_groups_count       = intel_get_groups_count,
 582         .get_group_name         = intel_get_group_name,
 583         .get_group_pins         = intel_get_group_pins,
 584 };
 585
 586 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
 587                                      const struct intel_pingroup group,
 588                                      unsigned int func)
 589 {
 590         unsigned long flags;
 591         int i;
 592
 593         raw_spin_lock_irqsave(&byt_lock, flags);
 594
 595         for (i = 0; i < group.grp.npins; i++) {
 596                 void __iomem *padcfg0;
 597                 u32 value;
 598
 599                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 600                 if (!padcfg0) {
 601                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 602                                  group.grp.name, i);
 603                         continue;
 604                 }
 605
 606                 value = readl(padcfg0);
 607                 value &= ~BYT_PIN_MUX;
 608                 value |= func;
 609                 writel(value, padcfg0);
 610         }
 611
 612         raw_spin_unlock_irqrestore(&byt_lock, flags);
 613 }
 614
 615 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
 616                                     const struct intel_pingroup group,
 617                                     const unsigned int *func)
 618 {
 619         unsigned long flags;
 620         int i;
 621
 622         raw_spin_lock_irqsave(&byt_lock, flags);
 623
 624         for (i = 0; i < group.grp.npins; i++) {
 625                 void __iomem *padcfg0;
 626                 u32 value;
 627
 628                 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
 629                 if (!padcfg0) {
 630                         dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
 631                                  group.grp.name, i);
 632                         continue;
 633                 }
 634
 635                 value = readl(padcfg0);
 636                 value &= ~BYT_PIN_MUX;
 637                 value |= func[i];
 638                 writel(value, padcfg0);
 639         }
 640
 641         raw_spin_unlock_irqrestore(&byt_lock, flags);
 642 }
 643
 644 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
 645                        unsigned int group_selector)
 646 {
 647         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
 648         const struct intel_function func = vg->soc->functions[func_selector];
 649         const struct intel_pingroup group = vg->soc->groups[group_selector];
 650
 651         if (group.modes)
 652                 byt_set_group_mixed_mux(vg, group, group.modes);
 653         else if (!strcmp(func.func.name, "gpio"))
 654                 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
 655         else
 656                 byt_set_group_simple_mux(vg, group, group.mode);
 657
 658         return 0;
 659 }
 660
 661 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
 662 {
 663         /* SCORE pin 92-93 */
 664         if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
 665             offset >= 92 && offset <= 93)
 666                 return BYT_ALTER_GPIO_MUX;
 667
 668         /* SUS pin 11-21 */
 669         if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
 670             offset >= 11 && offset <= 21)
 671                 return BYT_ALTER_GPIO_MUX;
 672
 673         return BYT_DEFAULT_GPIO_MUX;
 674 }
 675
 676 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
 677 {
 678         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 679         unsigned long flags;
 680         u32 value;
 681
 682         raw_spin_lock_irqsave(&byt_lock, flags);
 683         value = readl(reg);
 684
 685         /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
 686         if (!(value & BYT_DIRECT_IRQ_EN))
 687                 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
 688
 689         writel(value, reg);
 690         raw_spin_unlock_irqrestore(&byt_lock, flags);
 691 }
 692
 693 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
 694                                    struct pinctrl_gpio_range *range,
 695                                    unsigned int offset)
 696 {
 697         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 698         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 699         u32 value, gpio_mux;
 700         unsigned long flags;
 701
 702         raw_spin_lock_irqsave(&byt_lock, flags);
 703
 704         /*
 705          * In most cases, func pin mux 000 means GPIO function.
 706          * But, some pins may have func pin mux 001 represents
 707          * GPIO function.
 708          *
 709          * Because there are devices out there where some pins were not
 710          * configured correctly we allow changing the mux value from
 711          * request (but print out warning about that).
 712          */
 713         value = readl(reg) & BYT_PIN_MUX;
 714         gpio_mux = byt_get_gpio_mux(vg, offset);
 715         if (gpio_mux != value) {
 716                 value = readl(reg) & ~BYT_PIN_MUX;
 717                 value |= gpio_mux;
 718                 writel(value, reg);
 719
 720                 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
 721         }
 722
 723         raw_spin_unlock_irqrestore(&byt_lock, flags);
 724
 725         pm_runtime_get(vg->dev);
 726
 727         return 0;
 728 }
 729
 730 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
 731                                   struct pinctrl_gpio_range *range,
 732                                   unsigned int offset)
 733 {
 734         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 735
 736         byt_gpio_clear_triggering(vg, offset);
 737         pm_runtime_put(vg->dev);
 738 }
 739
 740 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
 741                                       unsigned int offset)
 742 {
 743         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 744
 745         /*
 746          * Before making any direction modifications, do a check if gpio is set
 747          * for direct IRQ. On Bay Trail, setting GPIO to output does not make
 748          * sense, so let's at least inform the caller before they shoot
 749          * themselves in the foot.
 750          */
 751         if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
 752                 dev_info_once(vg->dev,
 753                               "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
 754                               offset);
 755 }
 756
 757 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
 758                                   struct pinctrl_gpio_range *range,
 759                                   unsigned int offset,
 760                                   bool input)
 761 {
 762         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 763         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 764         unsigned long flags;
 765         u32 value;
 766
 767         raw_spin_lock_irqsave(&byt_lock, flags);
 768
 769         value = readl(val_reg);
 770         value &= ~BYT_DIR_MASK;
 771         if (input)
 772                 value |= BYT_OUTPUT_EN;
 773         else
 774                 byt_gpio_direct_irq_check(vg, offset);
 775
 776         writel(value, val_reg);
 777
 778         raw_spin_unlock_irqrestore(&byt_lock, flags);
 779
 780         return 0;
 781 }
 782
 783 static const struct pinmux_ops byt_pinmux_ops = {
 784         .get_functions_count    = intel_get_functions_count,
 785         .get_function_name      = intel_get_function_name,
 786         .get_function_groups    = intel_get_function_groups,
 787         .set_mux                = byt_set_mux,
 788         .gpio_request_enable    = byt_gpio_request_enable,
 789         .gpio_disable_free      = byt_gpio_disable_free,
 790         .gpio_set_direction     = byt_gpio_set_direction,
 791 };
 792
 793 static void byt_get_pull_strength(u32 reg, u16 *strength)
 794 {
 795         switch (reg & BYT_PULL_STR_MASK) {
 796         case BYT_PULL_STR_2K:
 797                 *strength = 2000;
 798                 break;
 799         case BYT_PULL_STR_10K:
 800                 *strength = 10000;
 801                 break;
 802         case BYT_PULL_STR_20K:
 803                 *strength = 20000;
 804                 break;
 805         case BYT_PULL_STR_40K:
 806                 *strength = 40000;
 807                 break;
 808         }
 809 }
 810
 811 static int byt_set_pull_strength(u32 *reg, u16 strength)
 812 {
 813         *reg &= ~BYT_PULL_STR_MASK;
 814
 815         switch (strength) {
 816         case 2000:
 817                 *reg |= BYT_PULL_STR_2K;
 818                 break;
 819         case 10000:
 820                 *reg |= BYT_PULL_STR_10K;
 821                 break;
 822         case 20000:
 823                 *reg |= BYT_PULL_STR_20K;
 824                 break;
 825         case 40000:
 826                 *reg |= BYT_PULL_STR_40K;
 827                 break;
 828         default:
 829                 return -EINVAL;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
 836                               unsigned long *config)
 837 {
 838         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 839         enum pin_config_param param = pinconf_to_config_param(*config);
 840         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 841         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 842         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 843         unsigned long flags;
 844         u32 conf, pull, val, debounce;
 845         u16 arg = 0;
 846
 847         raw_spin_lock_irqsave(&byt_lock, flags);
 848         conf = readl(conf_reg);
 849         pull = conf & BYT_PULL_ASSIGN_MASK;
 850         val = readl(val_reg);
 851         raw_spin_unlock_irqrestore(&byt_lock, flags);
 852
 853         switch (param) {
 854         case PIN_CONFIG_BIAS_DISABLE:
 855                 if (pull)
 856                         return -EINVAL;
 857                 break;
 858         case PIN_CONFIG_BIAS_PULL_DOWN:
 859                 /* Pull assignment is only applicable in input mode */
 860                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
 861                         return -EINVAL;
 862
 863                 byt_get_pull_strength(conf, &arg);
 864
 865                 break;
 866         case PIN_CONFIG_BIAS_PULL_UP:
 867                 /* Pull assignment is only applicable in input mode */
 868                 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
 869                         return -EINVAL;
 870
 871                 byt_get_pull_strength(conf, &arg);
 872
 873                 break;
 874         case PIN_CONFIG_INPUT_DEBOUNCE:
 875                 if (!(conf & BYT_DEBOUNCE_EN))
 876                         return -EINVAL;
 877
 878                 raw_spin_lock_irqsave(&byt_lock, flags);
 879                 debounce = readl(db_reg);
 880                 raw_spin_unlock_irqrestore(&byt_lock, flags);
 881
 882                 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
 883                 case BYT_DEBOUNCE_PULSE_375US:
 884                         arg = 375;
 885                         break;
 886                 case BYT_DEBOUNCE_PULSE_750US:
 887                         arg = 750;
 888                         break;
 889                 case BYT_DEBOUNCE_PULSE_1500US:
 890                         arg = 1500;
 891                         break;
 892                 case BYT_DEBOUNCE_PULSE_3MS:
 893                         arg = 3000;
 894                         break;
 895                 case BYT_DEBOUNCE_PULSE_6MS:
 896                         arg = 6000;
 897                         break;
 898                 case BYT_DEBOUNCE_PULSE_12MS:
 899                         arg = 12000;
 900                         break;
 901                 case BYT_DEBOUNCE_PULSE_24MS:
 902                         arg = 24000;
 903                         break;
 904                 default:
 905                         return -EINVAL;
 906                 }
 907
 908                 break;
 909         default:
 910                 return -ENOTSUPP;
 911         }
 912
 913         *config = pinconf_to_config_packed(param, arg);
 914
 915         return 0;
 916 }
 917
 918 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
 919                               unsigned int offset,
 920                               unsigned long *configs,
 921                               unsigned int num_configs)
 922 {
 923         struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
 924         void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
 925         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
 926         void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
 927         u32 conf, val, db_pulse, debounce;
 928         enum pin_config_param param;
 929         unsigned long flags;
 930         int i, ret = 0;
 931         u32 arg;
 932
 933         raw_spin_lock_irqsave(&byt_lock, flags);
 934
 935         conf = readl(conf_reg);
 936         val = readl(val_reg);
 937
 938         for (i = 0; i < num_configs; i++) {
 939                 param = pinconf_to_config_param(configs[i]);
 940                 arg = pinconf_to_config_argument(configs[i]);
 941
 942                 switch (param) {
 943                 case PIN_CONFIG_BIAS_DISABLE:
 944                         conf &= ~BYT_PULL_ASSIGN_MASK;
 945                         break;
 946                 case PIN_CONFIG_BIAS_PULL_DOWN:
 947                         /* Set default strength value in case none is given */
 948                         if (arg == 1)
 949                                 arg = 2000;
 950
 951                         /*
 952                          * Pull assignment is only applicable in input mode. If
 953                          * chip is not in input mode, set it and warn about it.
 954                          */
 955                         if (val & BYT_INPUT_EN) {
 956                                 val &= ~BYT_INPUT_EN;
 957                                 writel(val, val_reg);
 958                                 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
 959                         }
 960
 961                         conf &= ~BYT_PULL_ASSIGN_MASK;
 962                         conf |= BYT_PULL_ASSIGN_DOWN;
 963                         ret = byt_set_pull_strength(&conf, arg);
 964
 965                         break;
 966                 case PIN_CONFIG_BIAS_PULL_UP:
 967                         /* Set default strength value in case none is given */
 968                         if (arg == 1)
 969                                 arg = 2000;
 970
 971                         /*
 972                          * Pull assignment is only applicable in input mode. If
 973                          * chip is not in input mode, set it and warn about it.
 974                          */
 975                         if (val & BYT_INPUT_EN) {
 976                                 val &= ~BYT_INPUT_EN;
 977                                 writel(val, val_reg);
 978                                 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
 979                         }
 980
 981                         conf &= ~BYT_PULL_ASSIGN_MASK;
 982                         conf |= BYT_PULL_ASSIGN_UP;
 983                         ret = byt_set_pull_strength(&conf, arg);
 984
 985                         break;
 986                 case PIN_CONFIG_INPUT_DEBOUNCE:
 987                         if (arg) {
 988                                 conf |= BYT_DEBOUNCE_EN;
 989                         } else {
 990                                 conf &= ~BYT_DEBOUNCE_EN;
 991
 992                                 /*
 993                                  * No need to update the pulse value.
 994                                  * Debounce is going to be disabled.
 995                                  */
 996                                 break;
 997                         }
 998
 999                         switch (arg) {
1000                         case 375:
1001                                 db_pulse = BYT_DEBOUNCE_PULSE_375US;
1002                                 break;
1003                         case 750:
1004                                 db_pulse = BYT_DEBOUNCE_PULSE_750US;
1005                                 break;
1006                         case 1500:
1007                                 db_pulse = BYT_DEBOUNCE_PULSE_1500US;
1008                                 break;
1009                         case 3000:
1010                                 db_pulse = BYT_DEBOUNCE_PULSE_3MS;
1011                                 break;
1012                         case 6000:
1013                                 db_pulse = BYT_DEBOUNCE_PULSE_6MS;
1014                                 break;
1015                         case 12000:
1016                                 db_pulse = BYT_DEBOUNCE_PULSE_12MS;
1017                                 break;
1018                         case 24000:
1019                                 db_pulse = BYT_DEBOUNCE_PULSE_24MS;
1020                                 break;
1021                         default:
1022                                 if (arg)
1023                                         ret = -EINVAL;
1024                                 break;
1025                         }
1026
1027                         if (ret)
1028                                 break;
1029
1030                         debounce = readl(db_reg);
1031                         debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse;
1032                         writel(debounce, db_reg);
1033
1034                         break;
1035                 default:
1036                         ret = -ENOTSUPP;
1037                 }
1038
1039                 if (ret)
1040                         break;
1041         }
1042
1043         if (!ret)
1044                 writel(conf, conf_reg);
1045
1046         raw_spin_unlock_irqrestore(&byt_lock, flags);
1047
1048         return ret;
1049 }
1050
1051 static const struct pinconf_ops byt_pinconf_ops = {
1052         .is_generic     = true,
1053         .pin_config_get = byt_pin_config_get,
1054         .pin_config_set = byt_pin_config_set,
1055 };
1056
1057 static const struct pinctrl_desc byt_pinctrl_desc = {
1058         .pctlops        = &byt_pinctrl_ops,
1059         .pmxops         = &byt_pinmux_ops,
1060         .confops        = &byt_pinconf_ops,
1061         .owner          = THIS_MODULE,
1062 };
1063
1064 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset)
1065 {
1066         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1067         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1068         unsigned long flags;
1069         u32 val;
1070
1071         raw_spin_lock_irqsave(&byt_lock, flags);
1072         val = readl(reg);
1073         raw_spin_unlock_irqrestore(&byt_lock, flags);
1074
1075         return !!(val & BYT_LEVEL);
1076 }
1077
1078 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1079 {
1080         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1081         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1082         unsigned long flags;
1083         u32 old_val;
1084
1085         if (!reg)
1086                 return;
1087
1088         raw_spin_lock_irqsave(&byt_lock, flags);
1089         old_val = readl(reg);
1090         if (value)
1091                 writel(old_val | BYT_LEVEL, reg);
1092         else
1093                 writel(old_val & ~BYT_LEVEL, reg);
1094         raw_spin_unlock_irqrestore(&byt_lock, flags);
1095 }
1096
1097 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1098 {
1099         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1100         void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1101         unsigned long flags;
1102         u32 value;
1103
1104         if (!reg)
1105                 return -EINVAL;
1106
1107         raw_spin_lock_irqsave(&byt_lock, flags);
1108         value = readl(reg);
1109         raw_spin_unlock_irqrestore(&byt_lock, flags);
1110
1111         if (!(value & BYT_OUTPUT_EN))
1112                 return GPIO_LINE_DIRECTION_OUT;
1113         if (!(value & BYT_INPUT_EN))
1114                 return GPIO_LINE_DIRECTION_IN;
1115
1116         return -EINVAL;
1117 }
1118
1119 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1120 {
1121         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1122         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1123         unsigned long flags;
1124         u32 reg;
1125
1126         raw_spin_lock_irqsave(&byt_lock, flags);
1127
1128         reg = readl(val_reg);
1129         reg &= ~BYT_DIR_MASK;
1130         reg |= BYT_OUTPUT_EN;
1131         writel(reg, val_reg);
1132
1133         raw_spin_unlock_irqrestore(&byt_lock, flags);
1134         return 0;
1135 }
1136
1137 /*
1138  * Note despite the temptation this MUST NOT be converted into a call to
1139  * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this
1140  * MUST be done as a single BYT_VAL_REG register write.
1141  * See the commit message of the commit adding this comment for details.
1142  */
1143 static int byt_gpio_direction_output(struct gpio_chip *chip,
1144                                      unsigned int offset, int value)
1145 {
1146         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1147         void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1148         unsigned long flags;
1149         u32 reg;
1150
1151         raw_spin_lock_irqsave(&byt_lock, flags);
1152
1153         byt_gpio_direct_irq_check(vg, offset);
1154
1155         reg = readl(val_reg);
1156         reg &= ~BYT_DIR_MASK;
1157         if (value)
1158                 reg |= BYT_LEVEL;
1159         else
1160                 reg &= ~BYT_LEVEL;
1161
1162         writel(reg, val_reg);
1163
1164         raw_spin_unlock_irqrestore(&byt_lock, flags);
1165         return 0;
1166 }
1167
1168 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1169 {
1170         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1171         int i;
1172         u32 conf0, val;
1173
1174         for (i = 0; i < vg->soc->npins; i++) {
1175                 const struct intel_community *comm;
1176                 void __iomem *conf_reg, *val_reg;
1177                 const char *pull_str = NULL;
1178                 const char *pull = NULL;
1179                 unsigned long flags;
1180                 const char *label;
1181                 unsigned int pin;
1182
1183                 pin = vg->soc->pins[i].number;
1184
1185                 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1186                 if (!conf_reg) {
1187                         seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
1188                         continue;
1189                 }
1190
1191                 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1192                 if (!val_reg) {
1193                         seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
1194                         continue;
1195                 }
1196
1197                 raw_spin_lock_irqsave(&byt_lock, flags);
1198                 conf0 = readl(conf_reg);
1199                 val = readl(val_reg);
1200                 raw_spin_unlock_irqrestore(&byt_lock, flags);
1201
1202                 comm = intel_get_community(vg, pin);
1203                 if (!comm) {
1204                         seq_printf(s, "Pin %i: can't retrieve community\n", pin);
1205                         continue;
1206                 }
1207                 label = gpiochip_is_requested(chip, i);
1208                 if (!label)
1209                         label = "Unrequested";
1210
1211                 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1212                 case BYT_PULL_ASSIGN_UP:
1213                         pull = "up";
1214                         break;
1215                 case BYT_PULL_ASSIGN_DOWN:
1216                         pull = "down";
1217                         break;
1218                 }
1219
1220                 switch (conf0 & BYT_PULL_STR_MASK) {
1221                 case BYT_PULL_STR_2K:
1222                         pull_str = "2k";
1223                         break;
1224                 case BYT_PULL_STR_10K:
1225                         pull_str = "10k";
1226                         break;
1227                 case BYT_PULL_STR_20K:
1228                         pull_str = "20k";
1229                         break;
1230                 case BYT_PULL_STR_40K:
1231                         pull_str = "40k";
1232                         break;
1233                 }
1234
1235                 seq_printf(s,
1236                            " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1237                            pin,
1238                            label,
1239                            val & BYT_INPUT_EN ? "  " : "in",
1240                            val & BYT_OUTPUT_EN ? "   " : "out",
1241                            str_hi_lo(val & BYT_LEVEL),
1242                            comm->pad_map[i], comm->pad_map[i] * 16,
1243                            conf0 & 0x7,
1244                            conf0 & BYT_TRIG_NEG ? " fall" : "     ",
1245                            conf0 & BYT_TRIG_POS ? " rise" : "     ",
1246                            conf0 & BYT_TRIG_LVL ? " level" : "      ");
1247
1248                 if (pull && pull_str)
1249                         seq_printf(s, " %-4s %-3s", pull, pull_str);
1250                 else
1251                         seq_puts(s, "          ");
1252
1253                 if (conf0 & BYT_IODEN)
1254                         seq_puts(s, " open-drain");
1255
1256                 seq_puts(s, "\n");
1257         }
1258 }
1259
1260 static const struct gpio_chip byt_gpio_chip = {
1261         .owner                  = THIS_MODULE,
1262         .request                = gpiochip_generic_request,
1263         .free                   = gpiochip_generic_free,
1264         .get_direction          = byt_gpio_get_direction,
1265         .direction_input        = byt_gpio_direction_input,
1266         .direction_output       = byt_gpio_direction_output,
1267         .get                    = byt_gpio_get,
1268         .set                    = byt_gpio_set,
1269         .set_config             = gpiochip_generic_config,
1270         .dbg_show               = byt_gpio_dbg_show,
1271 };
1272
1273 static void byt_irq_ack(struct irq_data *d)
1274 {
1275         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1276         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1277         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1278         void __iomem *reg;
1279
1280         reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG);
1281         if (!reg)
1282                 return;
1283
1284         raw_spin_lock(&byt_lock);
1285         writel(BIT(hwirq % 32), reg);
1286         raw_spin_unlock(&byt_lock);
1287 }
1288
1289 static void byt_irq_mask(struct irq_data *d)
1290 {
1291         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1292         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1293         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1294
1295         byt_gpio_clear_triggering(vg, hwirq);
1296         gpiochip_disable_irq(gc, hwirq);
1297 }
1298
1299 static void byt_irq_unmask(struct irq_data *d)
1300 {
1301         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1302         struct intel_pinctrl *vg = gpiochip_get_data(gc);
1303         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1304         unsigned long flags;
1305         void __iomem *reg;
1306         u32 value;
1307
1308         gpiochip_enable_irq(gc, hwirq);
1309
1310         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1311         if (!reg)
1312                 return;
1313
1314         raw_spin_lock_irqsave(&byt_lock, flags);
1315         value = readl(reg);
1316
1317         switch (irqd_get_trigger_type(d)) {
1318         case IRQ_TYPE_LEVEL_HIGH:
1319                 value |= BYT_TRIG_LVL;
1320                 fallthrough;
1321         case IRQ_TYPE_EDGE_RISING:
1322                 value |= BYT_TRIG_POS;
1323                 break;
1324         case IRQ_TYPE_LEVEL_LOW:
1325                 value |= BYT_TRIG_LVL;
1326                 fallthrough;
1327         case IRQ_TYPE_EDGE_FALLING:
1328                 value |= BYT_TRIG_NEG;
1329                 break;
1330         case IRQ_TYPE_EDGE_BOTH:
1331                 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1332                 break;
1333         }
1334
1335         writel(value, reg);
1336
1337         raw_spin_unlock_irqrestore(&byt_lock, flags);
1338 }
1339
1340 static int byt_irq_type(struct irq_data *d, unsigned int type)
1341 {
1342         struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1343         irq_hw_number_t hwirq = irqd_to_hwirq(d);
1344         u32 value;
1345         unsigned long flags;
1346         void __iomem *reg;
1347
1348         reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG);
1349         if (!reg)
1350                 return -EINVAL;
1351
1352         raw_spin_lock_irqsave(&byt_lock, flags);
1353         value = readl(reg);
1354
1355         WARN(value & BYT_DIRECT_IRQ_EN,
1356              "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
1357
1358         /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1359          * are used to indicate high and low level triggering
1360          */
1361         value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1362                    BYT_TRIG_LVL);
1363         /* Enable glitch filtering */
1364         value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1365                  BYT_GLITCH_F_FAST_CLK;
1366
1367         writel(value, reg);
1368
1369         if (type & IRQ_TYPE_EDGE_BOTH)
1370                 irq_set_handler_locked(d, handle_edge_irq);
1371         else if (type & IRQ_TYPE_LEVEL_MASK)
1372                 irq_set_handler_locked(d, handle_level_irq);
1373
1374         raw_spin_unlock_irqrestore(&byt_lock, flags);
1375
1376         return 0;
1377 }
1378
1379 static const struct irq_chip byt_gpio_irq_chip = {
1380         .name           = "BYT-GPIO",
1381         .irq_ack        = byt_irq_ack,
1382         .irq_mask       = byt_irq_mask,
1383         .irq_unmask     = byt_irq_unmask,
1384         .irq_set_type   = byt_irq_type,
1385         .flags          = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
1386         GPIOCHIP_IRQ_RESOURCE_HELPERS,
1387 };
1388
1389 static void byt_gpio_irq_handler(struct irq_desc *desc)
1390 {
1391         struct irq_data *data = irq_desc_get_irq_data(desc);
1392         struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1393         struct irq_chip *chip = irq_data_get_irq_chip(data);
1394         u32 base, pin;
1395         void __iomem *reg;
1396         unsigned long pending;
1397
1398         /* check from GPIO controller which pin triggered the interrupt */
1399         for (base = 0; base < vg->chip.ngpio; base += 32) {
1400                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1401
1402                 if (!reg) {
1403                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1404                         continue;
1405                 }
1406
1407                 raw_spin_lock(&byt_lock);
1408                 pending = readl(reg);
1409                 raw_spin_unlock(&byt_lock);
1410                 for_each_set_bit(pin, &pending, 32)
1411                         generic_handle_domain_irq(vg->chip.irq.domain, base + pin);
1412         }
1413         chip->irq_eoi(data);
1414 }
1415
1416 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0)
1417 {
1418         int direct_irq, ioapic_direct_irq_base;
1419         u8 *match, direct_irq_mux[16];
1420         u32 trig;
1421
1422         memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG,
1423                       sizeof(direct_irq_mux));
1424         match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
1425         if (!match) {
1426                 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
1427                 return false;
1428         }
1429
1430         direct_irq = match - direct_irq_mux;
1431         /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */
1432         ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67;
1433         dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin,
1434                 direct_irq, direct_irq + ioapic_direct_irq_base);
1435
1436         /*
1437          * Testing has shown that the way direct IRQs work is that the combination of the
1438          * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ
1439          * trigger block, which normally sets the status flag in the IRQ status reg at
1440          * 0x800, to one of the IO-APIC pins according to the mux registers.
1441          *
1442          * This means that:
1443          * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block
1444          * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1445          *    passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set,
1446          *    selecting edge mode operation then on the first edge the IO-APIC pin goes
1447          *    high, but since no write-to-clear write will be done to the IRQ status reg
1448          *    at 0x800, the detected edge condition will never get cleared.
1449          */
1450         trig = conf0 & BYT_TRIG_MASK;
1451         if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
1452             trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
1453                 dev_warn(vg->dev,
1454                          FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
1455                          pin, conf0);
1456                 return false;
1457         }
1458
1459         return true;
1460 }
1461
1462 static void byt_init_irq_valid_mask(struct gpio_chip *chip,
1463                                     unsigned long *valid_mask,
1464                                     unsigned int ngpios)
1465 {
1466         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1467         void __iomem *reg;
1468         u32 value;
1469         int i;
1470
1471         /*
1472          * Clear interrupt triggers for all pins that are GPIOs and
1473          * do not use direct IRQ mode. This will prevent spurious
1474          * interrupts from misconfigured pins.
1475          */
1476         for (i = 0; i < vg->soc->npins; i++) {
1477                 unsigned int pin = vg->soc->pins[i].number;
1478
1479                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1480                 if (!reg) {
1481                         dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
1482                         continue;
1483                 }
1484
1485                 value = readl(reg);
1486                 if (value & BYT_DIRECT_IRQ_EN) {
1487                         if (byt_direct_irq_sanity_check(vg, i, value)) {
1488                                 clear_bit(i, valid_mask);
1489                         } else {
1490                                 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1491                                            BYT_TRIG_NEG | BYT_TRIG_LVL);
1492                                 writel(value, reg);
1493                         }
1494                 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1495                         byt_gpio_clear_triggering(vg, i);
1496                         dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1497                 }
1498         }
1499 }
1500
1501 static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
1502 {
1503         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1504         void __iomem *reg;
1505         u32 base, value;
1506
1507         /* clear interrupt status trigger registers */
1508         for (base = 0; base < vg->soc->npins; base += 32) {
1509                 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1510
1511                 if (!reg) {
1512                         dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
1513                         continue;
1514                 }
1515
1516                 writel(0xffffffff, reg);
1517                 /* make sure trigger bits are cleared, if not then a pin
1518                    might be misconfigured in bios */
1519                 value = readl(reg);
1520                 if (value)
1521                         dev_err(vg->dev,
1522                                 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
1523                                 base / 32, value);
1524         }
1525
1526         return 0;
1527 }
1528
1529 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
1530 {
1531         struct intel_pinctrl *vg = gpiochip_get_data(chip);
1532         struct device *dev = vg->dev;
1533         int ret;
1534
1535         ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1536         if (ret)
1537                 dev_err(dev, "failed to add GPIO pin range\n");
1538
1539         return ret;
1540 }
1541
1542 static int byt_gpio_probe(struct intel_pinctrl *vg)
1543 {
1544         struct platform_device *pdev = to_platform_device(vg->dev);
1545         struct gpio_chip *gc;
1546         int irq, ret;
1547
1548         /* Set up gpio chip */
1549         vg->chip        = byt_gpio_chip;
1550         gc              = &vg->chip;
1551         gc->label       = dev_name(vg->dev);
1552         gc->base        = -1;
1553         gc->can_sleep   = false;
1554         gc->add_pin_ranges = byt_gpio_add_pin_ranges;
1555         gc->parent      = vg->dev;
1556         gc->ngpio       = vg->soc->npins;
1557
1558 #ifdef CONFIG_PM_SLEEP
1559         vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1560                                         GFP_KERNEL);
1561         if (!vg->context.pads)
1562                 return -ENOMEM;
1563 #endif
1564
1565         /* set up interrupts  */
1566         irq = platform_get_irq_optional(pdev, 0);
1567         if (irq > 0) {
1568                 struct gpio_irq_chip *girq;
1569
1570                 girq = &gc->irq;
1571                 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip);
1572                 girq->init_hw = byt_gpio_irq_init_hw;
1573                 girq->init_valid_mask = byt_init_irq_valid_mask;
1574                 girq->parent_handler = byt_gpio_irq_handler;
1575                 girq->num_parents = 1;
1576                 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1577                                              sizeof(*girq->parents), GFP_KERNEL);
1578                 if (!girq->parents)
1579                         return -ENOMEM;
1580                 girq->parents[0] = irq;
1581                 girq->default_type = IRQ_TYPE_NONE;
1582                 girq->handler = handle_bad_irq;
1583         }
1584
1585         ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1586         if (ret) {
1587                 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1588                 return ret;
1589         }
1590
1591         return ret;
1592 }
1593
1594 static int byt_set_soc_data(struct intel_pinctrl *vg,
1595                             const struct intel_pinctrl_soc_data *soc)
1596 {
1597         struct platform_device *pdev = to_platform_device(vg->dev);
1598         int i;
1599
1600         vg->soc = soc;
1601
1602         vg->ncommunities = vg->soc->ncommunities;
1603         vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1604                                        sizeof(*vg->communities), GFP_KERNEL);
1605         if (!vg->communities)
1606                 return -ENOMEM;
1607
1608         for (i = 0; i < vg->soc->ncommunities; i++) {
1609                 struct intel_community *comm = vg->communities + i;
1610
1611                 *comm = vg->soc->communities[i];
1612
1613                 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0);
1614                 if (IS_ERR(comm->pad_regs))
1615                         return PTR_ERR(comm->pad_regs);
1616         }
1617
1618         return 0;
1619 }
1620
1621 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1622         { "INT33B2", (kernel_ulong_t)byt_soc_data },
1623         { "INT33FC", (kernel_ulong_t)byt_soc_data },
1624         { }
1625 };
1626
1627 static int byt_pinctrl_probe(struct platform_device *pdev)
1628 {
1629         const struct intel_pinctrl_soc_data *soc_data;
1630         struct device *dev = &pdev->dev;
1631         struct intel_pinctrl *vg;
1632         int ret;
1633
1634         soc_data = intel_pinctrl_get_soc_data(pdev);
1635         if (IS_ERR(soc_data))
1636                 return PTR_ERR(soc_data);
1637
1638         vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1639         if (!vg)
1640                 return -ENOMEM;
1641
1642         vg->dev = dev;
1643         ret = byt_set_soc_data(vg, soc_data);
1644         if (ret) {
1645                 dev_err(dev, "failed to set soc data\n");
1646                 return ret;
1647         }
1648
1649         vg->pctldesc            = byt_pinctrl_desc;
1650         vg->pctldesc.name       = dev_name(dev);
1651         vg->pctldesc.pins       = vg->soc->pins;
1652         vg->pctldesc.npins      = vg->soc->npins;
1653
1654         vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1655         if (IS_ERR(vg->pctldev)) {
1656                 dev_err(dev, "failed to register pinctrl driver\n");
1657                 return PTR_ERR(vg->pctldev);
1658         }
1659
1660         ret = byt_gpio_probe(vg);
1661         if (ret)
1662                 return ret;
1663
1664         platform_set_drvdata(pdev, vg);
1665         pm_runtime_enable(dev);
1666
1667         return 0;
1668 }
1669
1670 static int byt_gpio_suspend(struct device *dev)
1671 {
1672         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1673         unsigned long flags;
1674         int i;
1675
1676         raw_spin_lock_irqsave(&byt_lock, flags);
1677
1678         for (i = 0; i < vg->soc->npins; i++) {
1679                 void __iomem *reg;
1680                 u32 value;
1681                 unsigned int pin = vg->soc->pins[i].number;
1682
1683                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1684                 if (!reg) {
1685                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1686                         continue;
1687                 }
1688                 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1689                 vg->context.pads[i].conf0 = value;
1690
1691                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1692                 if (!reg) {
1693                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1694                         continue;
1695                 }
1696                 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1697                 vg->context.pads[i].val = value;
1698         }
1699
1700         raw_spin_unlock_irqrestore(&byt_lock, flags);
1701         return 0;
1702 }
1703
1704 static int byt_gpio_resume(struct device *dev)
1705 {
1706         struct intel_pinctrl *vg = dev_get_drvdata(dev);
1707         unsigned long flags;
1708         int i;
1709
1710         raw_spin_lock_irqsave(&byt_lock, flags);
1711
1712         for (i = 0; i < vg->soc->npins; i++) {
1713                 void __iomem *reg;
1714                 u32 value;
1715                 unsigned int pin = vg->soc->pins[i].number;
1716
1717                 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1718                 if (!reg) {
1719                         dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
1720                         continue;
1721                 }
1722                 value = readl(reg);
1723                 if ((value & BYT_CONF0_RESTORE_MASK) !=
1724                      vg->context.pads[i].conf0) {
1725                         value &= ~BYT_CONF0_RESTORE_MASK;
1726                         value |= vg->context.pads[i].conf0;
1727                         writel(value, reg);
1728                         dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1729                 }
1730
1731                 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1732                 if (!reg) {
1733                         dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
1734                         continue;
1735                 }
1736                 value = readl(reg);
1737                 if ((value & BYT_VAL_RESTORE_MASK) !=
1738                      vg->context.pads[i].val) {
1739                         u32 v;
1740
1741                         v = value & ~BYT_VAL_RESTORE_MASK;
1742                         v |= vg->context.pads[i].val;
1743                         if (v != value) {
1744                                 writel(v, reg);
1745                                 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
1746                         }
1747                 }
1748         }
1749
1750         raw_spin_unlock_irqrestore(&byt_lock, flags);
1751         return 0;
1752 }
1753
1754 static int byt_gpio_runtime_suspend(struct device *dev)
1755 {
1756         return 0;
1757 }
1758
1759 static int byt_gpio_runtime_resume(struct device *dev)
1760 {
1761         return 0;
1762 }
1763
1764 static const struct dev_pm_ops byt_gpio_pm_ops = {
1765         LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1766         RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, NULL)
1767 };
1768
1769 static struct platform_driver byt_gpio_driver = {
1770         .probe          = byt_pinctrl_probe,
1771         .driver         = {
1772                 .name                   = "byt_gpio",
1773                 .pm                     = pm_ptr(&byt_gpio_pm_ops),
1774                 .acpi_match_table       = byt_gpio_acpi_match,
1775                 .suppress_bind_attrs    = true,
1776         },
1777 };
1778
1779 static int __init byt_gpio_init(void)
1780 {
1781         return platform_driver_register(&byt_gpio_driver);
1782 }
1783 subsys_initcall(byt_gpio_init);
1784
1785 MODULE_IMPORT_NS(PINCTRL_INTEL);