drivers/pinctrl/freescale/pinctrl-imx.c

   1 /*
   2  * Core driver for the imx pin controller
   3  *
   4  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2012 Linaro Ltd.
   6  *
   7  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  */
  14
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_address.h>
  22 #include <linux/pinctrl/machine.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinctrl.h>
  25 #include <linux/pinctrl/pinmux.h>
  26 #include <linux/slab.h>
  27 #include <linux/regmap.h>
  28
  29 #include "../core.h"
  30 #include "../pinconf.h"
  31 #include "../pinmux.h"
  32 #include "pinctrl-imx.h"
  33
  34 /* The bits in CONFIG cell defined in binding doc*/
  35 #define IMX_NO_PAD_CTL  0x80000000      /* no pin config need */
  36 #define IMX_PAD_SION 0x40000000         /* set SION */
  37
  38 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
  39                                 struct pinctrl_dev *pctldev,
  40                                 const char *name)
  41 {
  42         const struct group_desc *grp = NULL;
  43         int i;
  44
  45         for (i = 0; i < pctldev->num_groups; i++) {
  46                 grp = pinctrl_generic_get_group(pctldev, i);
  47                 if (grp && !strcmp(grp->name, name))
  48                         break;
  49         }
  50
  51         return grp;
  52 }
  53
  54 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
  55                    unsigned offset)
  56 {
  57         seq_printf(s, "%s", dev_name(pctldev->dev));
  58 }
  59
  60 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
  61                         struct device_node *np,
  62                         struct pinctrl_map **map, unsigned *num_maps)
  63 {
  64         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
  65         const struct group_desc *grp;
  66         struct pinctrl_map *new_map;
  67         struct device_node *parent;
  68         int map_num = 1;
  69         int i, j;
  70
  71         /*
  72          * first find the group of this node and check if we need create
  73          * config maps for pins
  74          */
  75         grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
  76         if (!grp) {
  77                 dev_err(ipctl->dev, "unable to find group for node %s\n",
  78                         np->name);
  79                 return -EINVAL;
  80         }
  81
  82         for (i = 0; i < grp->num_pins; i++) {
  83                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
  84
  85                 if (!(pin->config & IMX_NO_PAD_CTL))
  86                         map_num++;
  87         }
  88
  89         new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
  90         if (!new_map)
  91                 return -ENOMEM;
  92
  93         *map = new_map;
  94         *num_maps = map_num;
  95
  96         /* create mux map */
  97         parent = of_get_parent(np);
  98         if (!parent) {
  99                 kfree(new_map);
 100                 return -EINVAL;
 101         }
 102         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 103         new_map[0].data.mux.function = parent->name;
 104         new_map[0].data.mux.group = np->name;
 105         of_node_put(parent);
 106
 107         /* create config map */
 108         new_map++;
 109         for (i = j = 0; i < grp->num_pins; i++) {
 110                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 111
 112                 if (!(pin->config & IMX_NO_PAD_CTL)) {
 113                         new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
 114                         new_map[j].data.configs.group_or_pin =
 115                                         pin_get_name(pctldev, pin->pin);
 116                         new_map[j].data.configs.configs = &pin->config;
 117                         new_map[j].data.configs.num_configs = 1;
 118                         j++;
 119                 }
 120         }
 121
 122         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 123                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 124
 125         return 0;
 126 }
 127
 128 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
 129                                 struct pinctrl_map *map, unsigned num_maps)
 130 {
 131         kfree(map);
 132 }
 133
 134 static const struct pinctrl_ops imx_pctrl_ops = {
 135         .get_groups_count = pinctrl_generic_get_group_count,
 136         .get_group_name = pinctrl_generic_get_group_name,
 137         .get_group_pins = pinctrl_generic_get_group_pins,
 138         .pin_dbg_show = imx_pin_dbg_show,
 139         .dt_node_to_map = imx_dt_node_to_map,
 140         .dt_free_map = imx_dt_free_map,
 141
 142 };
 143
 144 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
 145                        unsigned group)
 146 {
 147         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 148         const struct imx_pinctrl_soc_info *info = ipctl->info;
 149         const struct imx_pin_reg *pin_reg;
 150         unsigned int npins, pin_id;
 151         int i;
 152         struct group_desc *grp = NULL;
 153         struct function_desc *func = NULL;
 154
 155         /*
 156          * Configure the mux mode for each pin in the group for a specific
 157          * function.
 158          */
 159         grp = pinctrl_generic_get_group(pctldev, group);
 160         if (!grp)
 161                 return -EINVAL;
 162
 163         func = pinmux_generic_get_function(pctldev, selector);
 164         if (!func)
 165                 return -EINVAL;
 166
 167         npins = grp->num_pins;
 168
 169         dev_dbg(ipctl->dev, "enable function %s group %s\n",
 170                 func->name, grp->name);
 171
 172         for (i = 0; i < npins; i++) {
 173                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 174
 175                 pin_id = pin->pin;
 176                 pin_reg = &ipctl->pin_regs[pin_id];
 177
 178                 if (pin_reg->mux_reg == -1) {
 179                         dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
 180                                 info->pins[pin_id].name);
 181                         continue;
 182                 }
 183
 184                 if (info->flags & SHARE_MUX_CONF_REG) {
 185                         u32 reg;
 186                         reg = readl(ipctl->base + pin_reg->mux_reg);
 187                         reg &= ~info->mux_mask;
 188                         reg |= (pin->mux_mode << info->mux_shift);
 189                         writel(reg, ipctl->base + pin_reg->mux_reg);
 190                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 191                                 pin_reg->mux_reg, reg);
 192                 } else {
 193                         writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
 194                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 195                                 pin_reg->mux_reg, pin->mux_mode);
 196                 }
 197
 198                 /*
 199                  * If the select input value begins with 0xff, it's a quirky
 200                  * select input and the value should be interpreted as below.
 201                  *     31     23      15      7        0
 202                  *     | 0xff | shift | width | select |
 203                  * It's used to work around the problem that the select
 204                  * input for some pin is not implemented in the select
 205                  * input register but in some general purpose register.
 206                  * We encode the select input value, width and shift of
 207                  * the bit field into input_val cell of pin function ID
 208                  * in device tree, and then decode them here for setting
 209                  * up the select input bits in general purpose register.
 210                  */
 211                 if (pin->input_val >> 24 == 0xff) {
 212                         u32 val = pin->input_val;
 213                         u8 select = val & 0xff;
 214                         u8 width = (val >> 8) & 0xff;
 215                         u8 shift = (val >> 16) & 0xff;
 216                         u32 mask = ((1 << width) - 1) << shift;
 217                         /*
 218                          * The input_reg[i] here is actually some IOMUXC general
 219                          * purpose register, not regular select input register.
 220                          */
 221                         val = readl(ipctl->base + pin->input_reg);
 222                         val &= ~mask;
 223                         val |= select << shift;
 224                         writel(val, ipctl->base + pin->input_reg);
 225                 } else if (pin->input_reg) {
 226                         /*
 227                          * Regular select input register can never be at offset
 228                          * 0, and we only print register value for regular case.
 229                          */
 230                         if (ipctl->input_sel_base)
 231                                 writel(pin->input_val, ipctl->input_sel_base +
 232                                                 pin->input_reg);
 233                         else
 234                                 writel(pin->input_val, ipctl->base +
 235                                                 pin->input_reg);
 236                         dev_dbg(ipctl->dev,
 237                                 "==>select_input: offset 0x%x val 0x%x\n",
 238                                 pin->input_reg, pin->input_val);
 239                 }
 240         }
 241
 242         return 0;
 243 }
 244
 245 struct pinmux_ops imx_pmx_ops = {
 246         .get_functions_count = pinmux_generic_get_function_count,
 247         .get_function_name = pinmux_generic_get_function_name,
 248         .get_function_groups = pinmux_generic_get_function_groups,
 249         .set_mux = imx_pmx_set,
 250 };
 251
 252 /* decode generic config into raw register values */
 253 static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
 254                                               unsigned long *configs,
 255                                               unsigned int num_configs)
 256 {
 257         const struct imx_pinctrl_soc_info *info = ipctl->info;
 258         const struct imx_cfg_params_decode *decode;
 259         enum pin_config_param param;
 260         u32 raw_config = 0;
 261         u32 param_val;
 262         int i, j;
 263
 264         WARN_ON(num_configs > info->num_decodes);
 265
 266         for (i = 0; i < num_configs; i++) {
 267                 param = pinconf_to_config_param(configs[i]);
 268                 param_val = pinconf_to_config_argument(configs[i]);
 269                 decode = info->decodes;
 270                 for (j = 0; j < info->num_decodes; j++) {
 271                         if (param == decode->param) {
 272                                 if (decode->invert)
 273                                         param_val = !param_val;
 274                                 raw_config |= (param_val << decode->shift)
 275                                               & decode->mask;
 276                                 break;
 277                         }
 278                         decode++;
 279                 }
 280         }
 281
 282         if (info->fixup)
 283                 info->fixup(configs, num_configs, &raw_config);
 284
 285         return raw_config;
 286 }
 287
 288 static u32 imx_pinconf_parse_generic_config(struct device_node *np,
 289                                             struct imx_pinctrl *ipctl)
 290 {
 291         const struct imx_pinctrl_soc_info *info = ipctl->info;
 292         struct pinctrl_dev *pctl = ipctl->pctl;
 293         unsigned int num_configs;
 294         unsigned long *configs;
 295         int ret;
 296
 297         if (!info->generic_pinconf)
 298                 return 0;
 299
 300         ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
 301                                               &num_configs);
 302         if (ret)
 303                 return 0;
 304
 305         return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
 306 }
 307
 308 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
 309                              unsigned pin_id, unsigned long *config)
 310 {
 311         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 312         const struct imx_pinctrl_soc_info *info = ipctl->info;
 313         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 314
 315         if (pin_reg->conf_reg == -1) {
 316                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 317                         info->pins[pin_id].name);
 318                 return -EINVAL;
 319         }
 320
 321         *config = readl(ipctl->base + pin_reg->conf_reg);
 322
 323         if (info->flags & SHARE_MUX_CONF_REG)
 324                 *config &= ~info->mux_mask;
 325
 326         return 0;
 327 }
 328
 329 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
 330                              unsigned pin_id, unsigned long *configs,
 331                              unsigned num_configs)
 332 {
 333         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 334         const struct imx_pinctrl_soc_info *info = ipctl->info;
 335         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 336         int i;
 337
 338         if (pin_reg->conf_reg == -1) {
 339                 dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
 340                         info->pins[pin_id].name);
 341                 return -EINVAL;
 342         }
 343
 344         dev_dbg(ipctl->dev, "pinconf set pin %s\n",
 345                 info->pins[pin_id].name);
 346
 347         for (i = 0; i < num_configs; i++) {
 348                 if (info->flags & SHARE_MUX_CONF_REG) {
 349                         u32 reg;
 350                         reg = readl(ipctl->base + pin_reg->conf_reg);
 351                         reg &= info->mux_mask;
 352                         reg |= configs[i];
 353                         writel(reg, ipctl->base + pin_reg->conf_reg);
 354                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
 355                                 pin_reg->conf_reg, reg);
 356                 } else {
 357                         writel(configs[i], ipctl->base + pin_reg->conf_reg);
 358                         dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
 359                                 pin_reg->conf_reg, configs[i]);
 360                 }
 361         } /* for each config */
 362
 363         return 0;
 364 }
 365
 366 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 367                                    struct seq_file *s, unsigned pin_id)
 368 {
 369         struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
 370         const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
 371         unsigned long config;
 372
 373         if (!pin_reg || pin_reg->conf_reg == -1) {
 374                 seq_puts(s, "N/A");
 375                 return;
 376         }
 377
 378         config = readl(ipctl->base + pin_reg->conf_reg);
 379         seq_printf(s, "0x%lx", config);
 380 }
 381
 382 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 383                                          struct seq_file *s, unsigned group)
 384 {
 385         struct group_desc *grp;
 386         unsigned long config;
 387         const char *name;
 388         int i, ret;
 389
 390         if (group > pctldev->num_groups)
 391                 return;
 392
 393         seq_puts(s, "\n");
 394         grp = pinctrl_generic_get_group(pctldev, group);
 395         if (!grp)
 396                 return;
 397
 398         for (i = 0; i < grp->num_pins; i++) {
 399                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 400
 401                 name = pin_get_name(pctldev, pin->pin);
 402                 ret = imx_pinconf_get(pctldev, pin->pin, &config);
 403                 if (ret)
 404                         return;
 405                 seq_printf(s, "  %s: 0x%lx\n", name, config);
 406         }
 407 }
 408
 409 static const struct pinconf_ops imx_pinconf_ops = {
 410         .pin_config_get = imx_pinconf_get,
 411         .pin_config_set = imx_pinconf_set,
 412         .pin_config_dbg_show = imx_pinconf_dbg_show,
 413         .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
 414 };
 415
 416 /*
 417  * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
 418  * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
 419  * For generic_pinconf case, there's no extra u32 CONFIG.
 420  *
 421  * PIN_FUNC_ID format:
 422  * Default:
 423  *     <mux_reg conf_reg input_reg mux_mode input_val>
 424  * SHARE_MUX_CONF_REG:
 425  *     <mux_conf_reg input_reg mux_mode input_val>
 426  */
 427 #define FSL_PIN_SIZE 24
 428 #define FSL_PIN_SHARE_SIZE 20
 429
 430 static int imx_pinctrl_parse_groups(struct device_node *np,
 431                                     struct group_desc *grp,
 432                                     struct imx_pinctrl *ipctl,
 433                                     u32 index)
 434 {
 435         const struct imx_pinctrl_soc_info *info = ipctl->info;
 436         int size, pin_size;
 437         const __be32 *list;
 438         int i;
 439         u32 config;
 440
 441         dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
 442
 443         if (info->flags & SHARE_MUX_CONF_REG)
 444                 pin_size = FSL_PIN_SHARE_SIZE;
 445         else
 446                 pin_size = FSL_PIN_SIZE;
 447
 448         if (info->generic_pinconf)
 449                 pin_size -= 4;
 450
 451         /* Initialise group */
 452         grp->name = np->name;
 453
 454         /*
 455          * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
 456          * do sanity check and calculate pins number
 457          *
 458          * First try legacy 'fsl,pins' property, then fall back to the
 459          * generic 'pinmux'.
 460          *
 461          * Note: for generic 'pinmux' case, there's no CONFIG part in
 462          * the binding format.
 463          */
 464         list = of_get_property(np, "fsl,pins", &size);
 465         if (!list) {
 466                 list = of_get_property(np, "pinmux", &size);
 467                 if (!list) {
 468                         dev_err(ipctl->dev,
 469                                 "no fsl,pins and pins property in node %pOF\n", np);
 470                         return -EINVAL;
 471                 }
 472         }
 473
 474         /* we do not check return since it's safe node passed down */
 475         if (!size || size % pin_size) {
 476                 dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
 477                 return -EINVAL;
 478         }
 479
 480         /* first try to parse the generic pin config */
 481         config = imx_pinconf_parse_generic_config(np, ipctl);
 482
 483         grp->num_pins = size / pin_size;
 484         grp->data = devm_kzalloc(ipctl->dev, grp->num_pins *
 485                                  sizeof(struct imx_pin), GFP_KERNEL);
 486         grp->pins = devm_kzalloc(ipctl->dev, grp->num_pins *
 487                                  sizeof(unsigned int), GFP_KERNEL);
 488         if (!grp->pins || !grp->data)
 489                 return -ENOMEM;
 490
 491         for (i = 0; i < grp->num_pins; i++) {
 492                 u32 mux_reg = be32_to_cpu(*list++);
 493                 u32 conf_reg;
 494                 unsigned int pin_id;
 495                 struct imx_pin_reg *pin_reg;
 496                 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
 497
 498                 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
 499                         mux_reg = -1;
 500
 501                 if (info->flags & SHARE_MUX_CONF_REG) {
 502                         conf_reg = mux_reg;
 503                 } else {
 504                         conf_reg = be32_to_cpu(*list++);
 505                         if (!conf_reg)
 506                                 conf_reg = -1;
 507                 }
 508
 509                 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
 510                 pin_reg = &ipctl->pin_regs[pin_id];
 511                 pin->pin = pin_id;
 512                 grp->pins[i] = pin_id;
 513                 pin_reg->mux_reg = mux_reg;
 514                 pin_reg->conf_reg = conf_reg;
 515                 pin->input_reg = be32_to_cpu(*list++);
 516                 pin->mux_mode = be32_to_cpu(*list++);
 517                 pin->input_val = be32_to_cpu(*list++);
 518
 519                 if (info->generic_pinconf) {
 520                         /* generic pin config decoded */
 521                         pin->config = config;
 522                 } else {
 523                         /* legacy pin config read from devicetree */
 524                         config = be32_to_cpu(*list++);
 525
 526                         /* SION bit is in mux register */
 527                         if (config & IMX_PAD_SION)
 528                                 pin->mux_mode |= IOMUXC_CONFIG_SION;
 529                         pin->config = config & ~IMX_PAD_SION;
 530                 }
 531
 532                 dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
 533                                 pin->mux_mode, pin->config);
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int imx_pinctrl_parse_functions(struct device_node *np,
 540                                        struct imx_pinctrl *ipctl,
 541                                        u32 index)
 542 {
 543         struct pinctrl_dev *pctl = ipctl->pctl;
 544         struct device_node *child;
 545         struct function_desc *func;
 546         struct group_desc *grp;
 547         u32 i = 0;
 548
 549         dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
 550
 551         func = pinmux_generic_get_function(pctl, index);
 552         if (!func)
 553                 return -EINVAL;
 554
 555         /* Initialise function */
 556         func->name = np->name;
 557         func->num_group_names = of_get_child_count(np);
 558         if (func->num_group_names == 0) {
 559                 dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
 560                 return -EINVAL;
 561         }
 562         func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
 563                                          sizeof(char *), GFP_KERNEL);
 564         if (!func->group_names)
 565                 return -ENOMEM;
 566
 567         for_each_child_of_node(np, child) {
 568                 func->group_names[i] = child->name;
 569
 570                 grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
 571                                    GFP_KERNEL);
 572                 if (!grp)
 573                         return -ENOMEM;
 574
 575                 mutex_lock(&ipctl->mutex);
 576                 radix_tree_insert(&pctl->pin_group_tree,
 577                                   ipctl->group_index++, grp);
 578                 mutex_unlock(&ipctl->mutex);
 579
 580                 imx_pinctrl_parse_groups(child, grp, ipctl, i++);
 581         }
 582
 583         return 0;
 584 }
 585
 586 /*
 587  * Check if the DT contains pins in the direct child nodes. This indicates the
 588  * newer DT format to store pins. This function returns true if the first found
 589  * fsl,pins property is in a child of np. Otherwise false is returned.
 590  */
 591 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
 592 {
 593         struct device_node *function_np;
 594         struct device_node *pinctrl_np;
 595
 596         for_each_child_of_node(np, function_np) {
 597                 if (of_property_read_bool(function_np, "fsl,pins"))
 598                         return true;
 599
 600                 for_each_child_of_node(function_np, pinctrl_np) {
 601                         if (of_property_read_bool(pinctrl_np, "fsl,pins"))
 602                                 return false;
 603                 }
 604         }
 605
 606         return true;
 607 }
 608
 609 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
 610                                 struct imx_pinctrl *ipctl)
 611 {
 612         struct device_node *np = pdev->dev.of_node;
 613         struct device_node *child;
 614         struct pinctrl_dev *pctl = ipctl->pctl;
 615         u32 nfuncs = 0;
 616         u32 i = 0;
 617         bool flat_funcs;
 618
 619         if (!np)
 620                 return -ENODEV;
 621
 622         flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
 623         if (flat_funcs) {
 624                 nfuncs = 1;
 625         } else {
 626                 nfuncs = of_get_child_count(np);
 627                 if (nfuncs == 0) {
 628                         dev_err(&pdev->dev, "no functions defined\n");
 629                         return -EINVAL;
 630                 }
 631         }
 632
 633         for (i = 0; i < nfuncs; i++) {
 634                 struct function_desc *function;
 635
 636                 function = devm_kzalloc(&pdev->dev, sizeof(*function),
 637                                         GFP_KERNEL);
 638                 if (!function)
 639                         return -ENOMEM;
 640
 641                 mutex_lock(&ipctl->mutex);
 642                 radix_tree_insert(&pctl->pin_function_tree, i, function);
 643                 mutex_unlock(&ipctl->mutex);
 644         }
 645         pctl->num_functions = nfuncs;
 646
 647         ipctl->group_index = 0;
 648         if (flat_funcs) {
 649                 pctl->num_groups = of_get_child_count(np);
 650         } else {
 651                 pctl->num_groups = 0;
 652                 for_each_child_of_node(np, child)
 653                         pctl->num_groups += of_get_child_count(child);
 654         }
 655
 656         if (flat_funcs) {
 657                 imx_pinctrl_parse_functions(np, ipctl, 0);
 658         } else {
 659                 i = 0;
 660                 for_each_child_of_node(np, child)
 661                         imx_pinctrl_parse_functions(child, ipctl, i++);
 662         }
 663
 664         return 0;
 665 }
 666
 667 /*
 668  * imx_free_resources() - free memory used by this driver
 669  * @info: info driver instance
 670  */
 671 static void imx_free_resources(struct imx_pinctrl *ipctl)
 672 {
 673         if (ipctl->pctl)
 674                 pinctrl_unregister(ipctl->pctl);
 675 }
 676
 677 int imx_pinctrl_probe(struct platform_device *pdev,
 678                       const struct imx_pinctrl_soc_info *info)
 679 {
 680         struct regmap_config config = { .name = "gpr" };
 681         struct device_node *dev_np = pdev->dev.of_node;
 682         struct pinctrl_desc *imx_pinctrl_desc;
 683         struct device_node *np;
 684         struct imx_pinctrl *ipctl;
 685         struct resource *res;
 686         struct regmap *gpr;
 687         int ret, i;
 688
 689         if (!info || !info->pins || !info->npins) {
 690                 dev_err(&pdev->dev, "wrong pinctrl info\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (info->gpr_compatible) {
 695                 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
 696                 if (!IS_ERR(gpr))
 697                         regmap_attach_dev(&pdev->dev, gpr, &config);
 698         }
 699
 700         /* Create state holders etc for this driver */
 701         ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
 702         if (!ipctl)
 703                 return -ENOMEM;
 704
 705         ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
 706                                       info->npins, GFP_KERNEL);
 707         if (!ipctl->pin_regs)
 708                 return -ENOMEM;
 709
 710         for (i = 0; i < info->npins; i++) {
 711                 ipctl->pin_regs[i].mux_reg = -1;
 712                 ipctl->pin_regs[i].conf_reg = -1;
 713         }
 714
 715         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 716         ipctl->base = devm_ioremap_resource(&pdev->dev, res);
 717         if (IS_ERR(ipctl->base))
 718                 return PTR_ERR(ipctl->base);
 719
 720         if (of_property_read_bool(dev_np, "fsl,input-sel")) {
 721                 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
 722                 if (!np) {
 723                         dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
 724                         return -EINVAL;
 725                 }
 726
 727                 ipctl->input_sel_base = of_iomap(np, 0);
 728                 of_node_put(np);
 729                 if (!ipctl->input_sel_base) {
 730                         dev_err(&pdev->dev,
 731                                 "iomuxc input select base address not found\n");
 732                         return -ENOMEM;
 733                 }
 734         }
 735
 736         imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
 737                                         GFP_KERNEL);
 738         if (!imx_pinctrl_desc)
 739                 return -ENOMEM;
 740
 741         imx_pinctrl_desc->name = dev_name(&pdev->dev);
 742         imx_pinctrl_desc->pins = info->pins;
 743         imx_pinctrl_desc->npins = info->npins;
 744         imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
 745         imx_pinctrl_desc->pmxops = &imx_pmx_ops;
 746         imx_pinctrl_desc->confops = &imx_pinconf_ops;
 747         imx_pinctrl_desc->owner = THIS_MODULE;
 748
 749         /* for generic pinconf */
 750         imx_pinctrl_desc->custom_params = info->custom_params;
 751         imx_pinctrl_desc->num_custom_params = info->num_custom_params;
 752
 753         /* platform specific callback */
 754         imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
 755
 756         mutex_init(&ipctl->mutex);
 757
 758         ipctl->info = info;
 759         ipctl->dev = &pdev->dev;
 760         platform_set_drvdata(pdev, ipctl);
 761         ret = devm_pinctrl_register_and_init(&pdev->dev,
 762                                              imx_pinctrl_desc, ipctl,
 763                                              &ipctl->pctl);
 764         if (ret) {
 765                 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
 766                 goto free;
 767         }
 768
 769         ret = imx_pinctrl_probe_dt(pdev, ipctl);
 770         if (ret) {
 771                 dev_err(&pdev->dev, "fail to probe dt properties\n");
 772                 goto free;
 773         }
 774
 775         dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
 776
 777         return pinctrl_enable(ipctl->pctl);
 778
 779 free:
 780         imx_free_resources(ipctl);
 781
 782         return ret;
 783 }