drivers/pinctrl/actions/pinctrl-owl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * OWL SoC's Pinctrl driver
   4  *
   5  * Copyright (c) 2014 Actions Semi Inc.
   6  * Author: David Liu <liuwei@actions-semi.com>
   7  *
   8  * Copyright (c) 2018 Linaro Ltd.
   9  * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/machine.h>
  19 #include <linux/pinctrl/pinctrl.h>
  20 #include <linux/pinctrl/pinmux.h>
  21 #include <linux/pinctrl/pinconf.h>
  22 #include <linux/pinctrl/pinconf-generic.h>
  23 #include <linux/slab.h>
  24 #include <linux/spinlock.h>
  25
  26 #include "../core.h"
  27 #include "../pinctrl-utils.h"
  28 #include "pinctrl-owl.h"
  29
  30 /**
  31  * struct owl_pinctrl - pinctrl state of the device
  32  * @dev: device handle
  33  * @pctrldev: pinctrl handle
  34  * @lock: spinlock to protect registers
  35  * @soc: reference to soc_data
  36  * @base: pinctrl register base address
  37  */
  38 struct owl_pinctrl {
  39         struct device *dev;
  40         struct pinctrl_dev *pctrldev;
  41         raw_spinlock_t lock;
  42         struct clk *clk;
  43         const struct owl_pinctrl_soc_data *soc;
  44         void __iomem *base;
  45 };
  46
  47 static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
  48 {
  49         u32 reg_val;
  50
  51         reg_val = readl_relaxed(base);
  52
  53         reg_val = (reg_val & ~mask) | (val & mask);
  54
  55         writel_relaxed(reg_val, base);
  56 }
  57
  58 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
  59                                 u32 bit, u32 width)
  60 {
  61         u32 tmp, mask;
  62
  63         tmp = readl_relaxed(pctrl->base + reg);
  64         mask = (1 << width) - 1;
  65
  66         return (tmp >> bit) & mask;
  67 }
  68
  69 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
  70                                 u32 bit, u32 width)
  71 {
  72         u32 mask;
  73
  74         mask = (1 << width) - 1;
  75         mask = mask << bit;
  76
  77         owl_update_bits(pctrl->base + reg, mask, (arg << bit));
  78 }
  79
  80 static int owl_get_groups_count(struct pinctrl_dev *pctrldev)
  81 {
  82         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  83
  84         return pctrl->soc->ngroups;
  85 }
  86
  87 static const char *owl_get_group_name(struct pinctrl_dev *pctrldev,
  88                                 unsigned int group)
  89 {
  90         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
  91
  92         return pctrl->soc->groups[group].name;
  93 }
  94
  95 static int owl_get_group_pins(struct pinctrl_dev *pctrldev,
  96                                 unsigned int group,
  97                                 const unsigned int **pins,
  98                                 unsigned int *num_pins)
  99 {
 100         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 101
 102         *pins = pctrl->soc->groups[group].pads;
 103         *num_pins = pctrl->soc->groups[group].npads;
 104
 105         return 0;
 106 }
 107
 108 static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev,
 109                                 struct seq_file *s,
 110                                 unsigned int offset)
 111 {
 112         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 113
 114         seq_printf(s, "%s", dev_name(pctrl->dev));
 115 }
 116
 117 static struct pinctrl_ops owl_pinctrl_ops = {
 118         .get_groups_count = owl_get_groups_count,
 119         .get_group_name = owl_get_group_name,
 120         .get_group_pins = owl_get_group_pins,
 121         .pin_dbg_show = owl_pin_dbg_show,
 122         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 123         .dt_free_map = pinctrl_utils_free_map,
 124 };
 125
 126 static int owl_get_funcs_count(struct pinctrl_dev *pctrldev)
 127 {
 128         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 129
 130         return pctrl->soc->nfunctions;
 131 }
 132
 133 static const char *owl_get_func_name(struct pinctrl_dev *pctrldev,
 134                                 unsigned int function)
 135 {
 136         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 137
 138         return pctrl->soc->functions[function].name;
 139 }
 140
 141 static int owl_get_func_groups(struct pinctrl_dev *pctrldev,
 142                                 unsigned int function,
 143                                 const char * const **groups,
 144                                 unsigned int * const num_groups)
 145 {
 146         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 147
 148         *groups = pctrl->soc->functions[function].groups;
 149         *num_groups = pctrl->soc->functions[function].ngroups;
 150
 151         return 0;
 152 }
 153
 154 static inline int get_group_mfp_mask_val(const struct owl_pingroup *g,
 155                                 int function,
 156                                 u32 *mask,
 157                                 u32 *val)
 158 {
 159         int id;
 160         u32 option_num;
 161         u32 option_mask;
 162
 163         for (id = 0; id < g->nfuncs; id++) {
 164                 if (g->funcs[id] == function)
 165                         break;
 166         }
 167         if (WARN_ON(id == g->nfuncs))
 168                 return -EINVAL;
 169
 170         option_num = (1 << g->mfpctl_width);
 171         if (id > option_num)
 172                 id -= option_num;
 173
 174         option_mask = option_num - 1;
 175         *mask = (option_mask  << g->mfpctl_shift);
 176         *val = (id << g->mfpctl_shift);
 177
 178         return 0;
 179 }
 180
 181 static int owl_set_mux(struct pinctrl_dev *pctrldev,
 182                                 unsigned int function,
 183                                 unsigned int group)
 184 {
 185         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 186         const struct owl_pingroup *g;
 187         unsigned long flags;
 188         u32 val, mask;
 189
 190         g = &pctrl->soc->groups[group];
 191
 192         if (get_group_mfp_mask_val(g, function, &mask, &val))
 193                 return -EINVAL;
 194
 195         raw_spin_lock_irqsave(&pctrl->lock, flags);
 196
 197         owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
 198
 199         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 200
 201         return 0;
 202 }
 203
 204 static struct pinmux_ops owl_pinmux_ops = {
 205         .get_functions_count = owl_get_funcs_count,
 206         .get_function_name = owl_get_func_name,
 207         .get_function_groups = owl_get_func_groups,
 208         .set_mux = owl_set_mux,
 209 };
 210
 211 static int owl_pad_pinconf_reg(const struct owl_padinfo *info,
 212                                 unsigned int param,
 213                                 u32 *reg,
 214                                 u32 *bit,
 215                                 u32 *width)
 216 {
 217         switch (param) {
 218         case PIN_CONFIG_BIAS_BUS_HOLD:
 219         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 220         case PIN_CONFIG_BIAS_PULL_DOWN:
 221         case PIN_CONFIG_BIAS_PULL_UP:
 222                 if (!info->pullctl)
 223                         return -EINVAL;
 224                 *reg = info->pullctl->reg;
 225                 *bit = info->pullctl->shift;
 226                 *width = info->pullctl->width;
 227                 break;
 228         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 229                 if (!info->st)
 230                         return -EINVAL;
 231                 *reg = info->st->reg;
 232                 *bit = info->st->shift;
 233                 *width = info->st->width;
 234                 break;
 235         default:
 236                 return -ENOTSUPP;
 237         }
 238
 239         return 0;
 240 }
 241
 242 static int owl_pad_pinconf_arg2val(const struct owl_padinfo *info,
 243                                 unsigned int param,
 244                                 u32 *arg)
 245 {
 246         switch (param) {
 247         case PIN_CONFIG_BIAS_BUS_HOLD:
 248                 *arg = OWL_PINCONF_PULL_HOLD;
 249                 break;
 250         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 251                 *arg = OWL_PINCONF_PULL_HIZ;
 252                 break;
 253         case PIN_CONFIG_BIAS_PULL_DOWN:
 254                 *arg = OWL_PINCONF_PULL_DOWN;
 255                 break;
 256         case PIN_CONFIG_BIAS_PULL_UP:
 257                 *arg = OWL_PINCONF_PULL_UP;
 258                 break;
 259         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 260                 *arg = (*arg >= 1 ? 1 : 0);
 261                 break;
 262         default:
 263                 return -ENOTSUPP;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int owl_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
 270                                 unsigned int param,
 271                                 u32 *arg)
 272 {
 273         switch (param) {
 274         case PIN_CONFIG_BIAS_BUS_HOLD:
 275                 *arg = *arg == OWL_PINCONF_PULL_HOLD;
 276                 break;
 277         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 278                 *arg = *arg == OWL_PINCONF_PULL_HIZ;
 279                 break;
 280         case PIN_CONFIG_BIAS_PULL_DOWN:
 281                 *arg = *arg == OWL_PINCONF_PULL_DOWN;
 282                 break;
 283         case PIN_CONFIG_BIAS_PULL_UP:
 284                 *arg = *arg == OWL_PINCONF_PULL_UP;
 285                 break;
 286         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 287                 *arg = *arg == 1;
 288                 break;
 289         default:
 290                 return -ENOTSUPP;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int owl_pin_config_get(struct pinctrl_dev *pctrldev,
 297                                 unsigned int pin,
 298                                 unsigned long *config)
 299 {
 300         int ret = 0;
 301         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 302         const struct owl_padinfo *info;
 303         unsigned int param = pinconf_to_config_param(*config);
 304         u32 reg, bit, width, arg;
 305
 306         info = &pctrl->soc->padinfo[pin];
 307
 308         ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 309         if (ret)
 310                 return ret;
 311
 312         arg = owl_read_field(pctrl, reg, bit, width);
 313
 314         ret = owl_pad_pinconf_val2arg(info, param, &arg);
 315         if (ret)
 316                 return ret;
 317
 318         *config = pinconf_to_config_packed(param, arg);
 319
 320         return ret;
 321 }
 322
 323 static int owl_pin_config_set(struct pinctrl_dev *pctrldev,
 324                                 unsigned int pin,
 325                                 unsigned long *configs,
 326                                 unsigned int num_configs)
 327 {
 328         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 329         const struct owl_padinfo *info;
 330         unsigned long flags;
 331         unsigned int param;
 332         u32 reg, bit, width, arg;
 333         int ret, i;
 334
 335         info = &pctrl->soc->padinfo[pin];
 336
 337         for (i = 0; i < num_configs; i++) {
 338                 param = pinconf_to_config_param(configs[i]);
 339                 arg = pinconf_to_config_argument(configs[i]);
 340
 341                 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);
 342                 if (ret)
 343                         return ret;
 344
 345                 ret = owl_pad_pinconf_arg2val(info, param, &arg);
 346                 if (ret)
 347                         return ret;
 348
 349                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 350
 351                 owl_write_field(pctrl, reg, arg, bit, width);
 352
 353                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 354         }
 355
 356         return ret;
 357 }
 358
 359 static int owl_group_pinconf_reg(const struct owl_pingroup *g,
 360                                 unsigned int param,
 361                                 u32 *reg,
 362                                 u32 *bit,
 363                                 u32 *width)
 364 {
 365         switch (param) {
 366         case PIN_CONFIG_DRIVE_STRENGTH:
 367                 if (g->drv_reg < 0)
 368                         return -EINVAL;
 369                 *reg = g->drv_reg;
 370                 *bit = g->drv_shift;
 371                 *width = g->drv_width;
 372                 break;
 373         case PIN_CONFIG_SLEW_RATE:
 374                 if (g->sr_reg < 0)
 375                         return -EINVAL;
 376                 *reg = g->sr_reg;
 377                 *bit = g->sr_shift;
 378                 *width = g->sr_width;
 379                 break;
 380         default:
 381                 return -ENOTSUPP;
 382         }
 383
 384         return 0;
 385 }
 386
 387 static int owl_group_pinconf_arg2val(const struct owl_pingroup *g,
 388                                 unsigned int param,
 389                                 u32 *arg)
 390 {
 391         switch (param) {
 392         case PIN_CONFIG_DRIVE_STRENGTH:
 393                 switch (*arg) {
 394                 case 2:
 395                         *arg = OWL_PINCONF_DRV_2MA;
 396                         break;
 397                 case 4:
 398                         *arg = OWL_PINCONF_DRV_4MA;
 399                         break;
 400                 case 8:
 401                         *arg = OWL_PINCONF_DRV_8MA;
 402                         break;
 403                 case 12:
 404                         *arg = OWL_PINCONF_DRV_12MA;
 405                         break;
 406                 default:
 407                         return -EINVAL;
 408                 }
 409                 break;
 410         case PIN_CONFIG_SLEW_RATE:
 411                 if (*arg)
 412                         *arg = OWL_PINCONF_SLEW_FAST;
 413                 else
 414                         *arg = OWL_PINCONF_SLEW_SLOW;
 415                 break;
 416         default:
 417                 return -ENOTSUPP;
 418         }
 419
 420         return 0;
 421 }
 422
 423 static int owl_group_pinconf_val2arg(const struct owl_pingroup *g,
 424                                 unsigned int param,
 425                                 u32 *arg)
 426 {
 427         switch (param) {
 428         case PIN_CONFIG_DRIVE_STRENGTH:
 429                 switch (*arg) {
 430                 case OWL_PINCONF_DRV_2MA:
 431                         *arg = 2;
 432                         break;
 433                 case OWL_PINCONF_DRV_4MA:
 434                         *arg = 4;
 435                         break;
 436                 case OWL_PINCONF_DRV_8MA:
 437                         *arg = 8;
 438                         break;
 439                 case OWL_PINCONF_DRV_12MA:
 440                         *arg = 12;
 441                         break;
 442                 default:
 443                         return -EINVAL;
 444                 }
 445                 break;
 446         case PIN_CONFIG_SLEW_RATE:
 447                 if (*arg)
 448                         *arg = 1;
 449                 else
 450                         *arg = 0;
 451                 break;
 452         default:
 453                 return -ENOTSUPP;
 454         }
 455
 456         return 0;
 457 }
 458
 459 static int owl_group_config_get(struct pinctrl_dev *pctrldev,
 460                                 unsigned int group,
 461                                 unsigned long *config)
 462 {
 463         const struct owl_pingroup *g;
 464         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 465         unsigned int param = pinconf_to_config_param(*config);
 466         u32 reg, bit, width, arg;
 467         int ret;
 468
 469         g = &pctrl->soc->groups[group];
 470
 471         ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 472         if (ret)
 473                 return ret;
 474
 475         arg = owl_read_field(pctrl, reg, bit, width);
 476
 477         ret = owl_group_pinconf_val2arg(g, param, &arg);
 478         if (ret)
 479                 return ret;
 480
 481         *config = pinconf_to_config_packed(param, arg);
 482
 483         return ret;
 484
 485 }
 486
 487 static int owl_group_config_set(struct pinctrl_dev *pctrldev,
 488                                 unsigned int group,
 489                                 unsigned long *configs,
 490                                 unsigned int num_configs)
 491 {
 492         const struct owl_pingroup *g;
 493         struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
 494         unsigned long flags;
 495         unsigned int param;
 496         u32 reg, bit, width, arg;
 497         int ret, i;
 498
 499         g = &pctrl->soc->groups[group];
 500
 501         for (i = 0; i < num_configs; i++) {
 502                 param = pinconf_to_config_param(configs[i]);
 503                 arg = pinconf_to_config_argument(configs[i]);
 504
 505                 ret = owl_group_pinconf_reg(g, param, &reg, &bit, &width);
 506                 if (ret)
 507                         return ret;
 508
 509                 ret = owl_group_pinconf_arg2val(g, param, &arg);
 510                 if (ret)
 511                         return ret;
 512
 513                 /* Update register */
 514                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 515
 516                 owl_write_field(pctrl, reg, arg, bit, width);
 517
 518                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 519         }
 520
 521         return 0;
 522 }
 523
 524 static const struct pinconf_ops owl_pinconf_ops = {
 525         .is_generic = true,
 526         .pin_config_get = owl_pin_config_get,
 527         .pin_config_set = owl_pin_config_set,
 528         .pin_config_group_get = owl_group_config_get,
 529         .pin_config_group_set = owl_group_config_set,
 530 };
 531
 532 static struct pinctrl_desc owl_pinctrl_desc = {
 533         .pctlops = &owl_pinctrl_ops,
 534         .pmxops = &owl_pinmux_ops,
 535         .confops = &owl_pinconf_ops,
 536         .owner = THIS_MODULE,
 537 };
 538
 539 int owl_pinctrl_probe(struct platform_device *pdev,
 540                                 struct owl_pinctrl_soc_data *soc_data)
 541 {
 542         struct resource *res;
 543         struct owl_pinctrl *pctrl;
 544         int ret;
 545
 546         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 547         if (!pctrl)
 548                 return -ENOMEM;
 549
 550         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 551         pctrl->base = devm_ioremap_resource(&pdev->dev, res);
 552         if (IS_ERR(pctrl->base))
 553                 return PTR_ERR(pctrl->base);
 554
 555         /* enable GPIO/MFP clock */
 556         pctrl->clk = devm_clk_get(&pdev->dev, NULL);
 557         if (IS_ERR(pctrl->clk)) {
 558                 dev_err(&pdev->dev, "no clock defined\n");
 559                 return PTR_ERR(pctrl->clk);
 560         }
 561
 562         ret = clk_prepare_enable(pctrl->clk);
 563         if (ret) {
 564                 dev_err(&pdev->dev, "clk enable failed\n");
 565                 return ret;
 566         }
 567
 568         raw_spin_lock_init(&pctrl->lock);
 569
 570         owl_pinctrl_desc.name = dev_name(&pdev->dev);
 571         owl_pinctrl_desc.pins = soc_data->pins;
 572         owl_pinctrl_desc.npins = soc_data->npins;
 573
 574         pctrl->soc = soc_data;
 575         pctrl->dev = &pdev->dev;
 576
 577         pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
 578                                         &owl_pinctrl_desc, pctrl);
 579         if (IS_ERR(pctrl->pctrldev)) {
 580                 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
 581                 return PTR_ERR(pctrl->pctrldev);
 582         }
 583
 584         platform_set_drvdata(pdev, pctrl);
 585
 586         return 0;
 587 }