1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
4 * Written by Jean-Jacques Hiblot <jjhiblot@ti.com>
10 #include <generic-phy.h>
12 #include <asm/arch/sys_proto.h>
16 /* PLLCTRL Registers */
17 #define PLL_STATUS 0x00000004
18 #define PLL_GO 0x00000008
19 #define PLL_CONFIGURATION1 0x0000000C
20 #define PLL_CONFIGURATION2 0x00000010
21 #define PLL_CONFIGURATION3 0x00000014
22 #define PLL_CONFIGURATION4 0x00000020
24 #define PLL_REGM_MASK 0x001FFE00
25 #define PLL_REGM_SHIFT 9
26 #define PLL_REGM_F_MASK 0x0003FFFF
27 #define PLL_REGM_F_SHIFT 0
28 #define PLL_REGN_MASK 0x000001FE
29 #define PLL_REGN_SHIFT 1
30 #define PLL_SELFREQDCO_MASK 0x0000000E
31 #define PLL_SELFREQDCO_SHIFT 1
32 #define PLL_SD_MASK 0x0003FC00
33 #define PLL_SD_SHIFT 10
34 #define SET_PLL_GO 0x1
35 #define PLL_TICOPWDN BIT(16)
36 #define PLL_LDOPWDN BIT(15)
40 /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
41 #define SATA_PLL_SOFT_RESET (1<<18)
43 /* PHY POWER CONTROL Register */
44 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
45 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
47 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
48 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
50 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
51 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
54 #define PLL_IDLE_TIME 100 /* in milliseconds */
55 #define PLL_LOCK_TIME 100 /* in milliseconds */
57 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
62 void __iomem *pll_ctrl_base;
63 void __iomem *power_reg;
64 void __iomem *pll_reset_reg;
65 struct pipe3_dpll_map *dpll_map;
69 struct pipe3_dpll_params {
77 struct pipe3_dpll_map {
79 struct pipe3_dpll_params params;
84 struct pipe3_dpll_map *dpll_map;
87 static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
89 return readl(addr + offset);
92 static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
95 writel(data, addr + offset);
98 static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
102 struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
104 rate = get_sys_clk_freq();
106 for (; dpll_map->rate; dpll_map++) {
107 if (rate == dpll_map->rate)
108 return &dpll_map->params;
111 printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
116 static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
119 int timeout = PLL_LOCK_TIME;
123 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
128 if (!(val & PLL_LOCK)) {
129 printf("%s: DPLL failed to lock\n", __func__);
136 static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
139 struct pipe3_dpll_params *dpll_params;
141 dpll_params = omap_pipe3_get_dpll_params(pipe3);
143 printf("%s: Invalid DPLL parameters\n", __func__);
147 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
148 val &= ~PLL_REGN_MASK;
149 val |= dpll_params->n << PLL_REGN_SHIFT;
150 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
152 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
153 val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
154 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
155 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
157 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
158 val &= ~PLL_REGM_MASK;
159 val |= dpll_params->m << PLL_REGM_SHIFT;
160 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
162 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
163 val &= ~PLL_REGM_F_MASK;
164 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
165 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
167 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
169 val |= dpll_params->sd << PLL_SD_SHIFT;
170 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
172 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
174 return omap_pipe3_wait_lock(pipe3);
177 static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
181 val = readl(pipe3->power_reg);
183 rate = get_sys_clk_freq();
187 val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
188 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
189 val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
190 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
192 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
194 val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
195 val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
196 OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
199 writel(val, pipe3->power_reg);
202 static int pipe3_init(struct phy *phy)
206 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
208 /* Program the DPLL only if not locked */
209 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
210 if (!(val & PLL_LOCK)) {
211 ret = omap_pipe3_dpll_program(pipe3);
215 /* else just bring it out of IDLE mode */
216 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
218 if (val & PLL_IDLE) {
220 omap_pipe3_writel(pipe3->pll_ctrl_base,
221 PLL_CONFIGURATION2, val);
222 ret = omap_pipe3_wait_lock(pipe3);
230 static int pipe3_power_on(struct phy *phy)
232 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
234 /* Power up the PHY */
235 omap_control_pipe3_power(pipe3, 1);
240 static int pipe3_power_off(struct phy *phy)
242 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
244 /* Power down the PHY */
245 omap_control_pipe3_power(pipe3, 0);
250 static int pipe3_exit(struct phy *phy)
253 int timeout = PLL_IDLE_TIME;
254 struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
256 pipe3_power_off(phy);
258 /* Put DPLL in IDLE mode */
259 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
261 omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
263 /* wait for LDO and Oscillator to power down */
266 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
267 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
271 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
272 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
277 if (pipe3->pll_reset_reg) {
278 val = readl(pipe3->pll_reset_reg);
279 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
281 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
287 static void *get_reg(struct udevice *dev, const char *name)
289 struct udevice *syscon;
290 struct regmap *regmap;
295 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
298 pr_err("unable to find syscon device for %s (%d)\n",
303 regmap = syscon_get_regmap(syscon);
304 if (IS_ERR(regmap)) {
305 pr_err("unable to find regmap for %s (%ld)\n",
306 name, PTR_ERR(regmap));
310 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
312 if (len < 2*sizeof(fdt32_t)) {
313 pr_err("offset not available for %s\n", name);
317 base = regmap_get_range(regmap, 0);
321 return fdtdec_get_number(cell + 1, 1) + base;
324 static int pipe3_phy_probe(struct udevice *dev)
328 struct omap_pipe3 *pipe3 = dev_get_priv(dev);
329 struct pipe3_data *data;
331 addr = devfdt_get_addr_size_index(dev, 2, &sz);
332 if (addr == FDT_ADDR_T_NONE) {
333 pr_err("missing pll ctrl address\n");
337 pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
338 if (!pipe3->pll_ctrl_base) {
339 pr_err("unable to remap pll ctrl\n");
343 pipe3->power_reg = get_reg(dev, "syscon-phy-power");
344 if (!pipe3->power_reg)
347 data = (struct pipe3_data *)dev_get_driver_data(dev);
348 pipe3->mode = data->mode;
349 pipe3->dpll_map = data->dpll_map;
351 if (pipe3->mode == PIPE3_MODE_SATA) {
352 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
353 if (!pipe3->pll_reset_reg)
360 static struct pipe3_dpll_map dpll_map_sata[] = {
361 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
362 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
363 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
364 {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
365 {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
366 {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
367 { }, /* Terminator */
370 static struct pipe3_dpll_map dpll_map_usb[] = {
371 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
372 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
373 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
374 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
375 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
376 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
377 { }, /* Terminator */
380 static struct pipe3_data data_usb = {
381 .mode = PIPE3_MODE_USBSS,
382 .dpll_map = dpll_map_usb,
385 static struct pipe3_data data_sata = {
386 .mode = PIPE3_MODE_SATA,
387 .dpll_map = dpll_map_sata,
390 static const struct udevice_id pipe3_phy_ids[] = {
391 { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
392 { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
396 static struct phy_ops pipe3_phy_ops = {
398 .power_on = pipe3_power_on,
399 .power_off = pipe3_power_off,
403 U_BOOT_DRIVER(pipe3_phy) = {
406 .of_match = pipe3_phy_ids,
407 .ops = &pipe3_phy_ops,
408 .probe = pipe3_phy_probe,
409 .priv_auto_alloc_size = sizeof(struct omap_pipe3),