drivers/phy/ti-pipe3-phy.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   4  * Written by Jean-Jacques Hiblot  <jjhiblot@ti.com>
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <dm/device.h>
  10 #include <generic-phy.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/sys_proto.h>
  13 #include <syscon.h>
  14 #include <regmap.h>
  15 #include <linux/bitops.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18
  19 /* PLLCTRL Registers */
  20 #define PLL_STATUS              0x00000004
  21 #define PLL_GO                  0x00000008
  22 #define PLL_CONFIGURATION1      0x0000000C
  23 #define PLL_CONFIGURATION2      0x00000010
  24 #define PLL_CONFIGURATION3      0x00000014
  25 #define PLL_CONFIGURATION4      0x00000020
  26
  27 #define PLL_REGM_MASK           0x001FFE00
  28 #define PLL_REGM_SHIFT          9
  29 #define PLL_REGM_F_MASK         0x0003FFFF
  30 #define PLL_REGM_F_SHIFT        0
  31 #define PLL_REGN_MASK           0x000001FE
  32 #define PLL_REGN_SHIFT          1
  33 #define PLL_SELFREQDCO_MASK     0x0000000E
  34 #define PLL_SELFREQDCO_SHIFT    1
  35 #define PLL_SD_MASK             0x0003FC00
  36 #define PLL_SD_SHIFT            10
  37 #define SET_PLL_GO              0x1
  38 #define PLL_TICOPWDN            BIT(16)
  39 #define PLL_LDOPWDN             BIT(15)
  40 #define PLL_LOCK                0x2
  41 #define PLL_IDLE                0x1
  42
  43 /* Software rest for the SATA PLL (in CTRL_CORE_SMA_SW_0 register)*/
  44 #define SATA_PLL_SOFT_RESET (1<<18)
  45
  46 /* PHY POWER CONTROL Register */
  47 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   GENMASK(21, 14)
  48 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  49
  50 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  GENMASK(31, 22)
  51 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  52
  53 #define PIPE3_PHY_RX_POWERON       (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  54 #define PIPE3_PHY_TX_POWERON       (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
  55
  56 /* PHY RX Registers */
  57 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY        0x0000000C
  58 #define INTERFACE_MASK                  GENMASK(31, 27)
  59 #define INTERFACE_SHIFT                 27
  60 #define INTERFACE_MODE_USBSS            BIT(4)
  61 #define INTERFACE_MODE_SATA_1P5         BIT(3)
  62 #define INTERFACE_MODE_SATA_3P0         BIT(2)
  63 #define INTERFACE_MODE_PCIE             BIT(0)
  64
  65 #define LOSD_MASK                       GENMASK(17, 14)
  66 #define LOSD_SHIFT                      14
  67 #define MEM_PLLDIV                      GENMASK(6, 5)
  68
  69 #define PIPE3_PHY_RX_TRIM               0x0000001C
  70 #define MEM_DLL_TRIM_SEL_MASK           GENMASK(31, 30)
  71 #define MEM_DLL_TRIM_SHIFT              30
  72
  73 #define PIPE3_PHY_RX_DLL                0x00000024
  74 #define MEM_DLL_PHINT_RATE_MASK         GENMASK(31, 30)
  75 #define MEM_DLL_PHINT_RATE_SHIFT        30
  76
  77 #define PIPE3_PHY_RX_DIGITAL_MODES              0x00000028
  78 #define MEM_HS_RATE_MASK                GENMASK(28, 27)
  79 #define MEM_HS_RATE_SHIFT               27
  80 #define MEM_OVRD_HS_RATE                BIT(26)
  81 #define MEM_OVRD_HS_RATE_SHIFT          26
  82 #define MEM_CDR_FASTLOCK                BIT(23)
  83 #define MEM_CDR_FASTLOCK_SHIFT          23
  84 #define MEM_CDR_LBW_MASK                GENMASK(22, 21)
  85 #define MEM_CDR_LBW_SHIFT               21
  86 #define MEM_CDR_STEPCNT_MASK            GENMASK(20, 19)
  87 #define MEM_CDR_STEPCNT_SHIFT           19
  88 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
  89 #define MEM_CDR_STL_SHIFT               16
  90 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
  91 #define MEM_CDR_THR_SHIFT               13
  92 #define MEM_CDR_THR_MODE                BIT(12)
  93 #define MEM_CDR_THR_MODE_SHIFT          12
  94 #define MEM_CDR_2NDO_SDM_MODE           BIT(11)
  95 #define MEM_CDR_2NDO_SDM_MODE_SHIFT     11
  96
  97 #define PIPE3_PHY_RX_EQUALIZER          0x00000038
  98 #define MEM_EQLEV_MASK                  GENMASK(31, 16)
  99 #define MEM_EQLEV_SHIFT                 16
 100 #define MEM_EQFTC_MASK                  GENMASK(15, 11)
 101 #define MEM_EQFTC_SHIFT                 11
 102 #define MEM_EQCTL_MASK                  GENMASK(10, 7)
 103 #define MEM_EQCTL_SHIFT                 7
 104 #define MEM_OVRD_EQLEV                  BIT(2)
 105 #define MEM_OVRD_EQLEV_SHIFT            2
 106 #define MEM_OVRD_EQFTC                  BIT(1)
 107 #define MEM_OVRD_EQFTC_SHIFT            1
 108
 109 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES        0x44
 110 #define MEM_CDR_LOS_SOURCE_MASK         GENMASK(10, 9)
 111 #define MEM_CDR_LOS_SOURCE_SHIFT        9
 112
 113 #define PLL_IDLE_TIME   100     /* in milliseconds */
 114 #define PLL_LOCK_TIME   100     /* in milliseconds */
 115
 116 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
 117                   PIPE3_MODE_SATA,
 118                   PIPE3_MODE_USBSS };
 119
 120 struct pipe3_settings {
 121         u8 ana_interface;
 122         u8 ana_losd;
 123         u8 dig_fastlock;
 124         u8 dig_lbw;
 125         u8 dig_stepcnt;
 126         u8 dig_stl;
 127         u8 dig_thr;
 128         u8 dig_thr_mode;
 129         u8 dig_2ndo_sdm_mode;
 130         u8 dig_hs_rate;
 131         u8 dig_ovrd_hs_rate;
 132         u8 dll_trim_sel;
 133         u8 dll_phint_rate;
 134         u8 eq_lev;
 135         u8 eq_ftc;
 136         u8 eq_ctl;
 137         u8 eq_ovrd_lev;
 138         u8 eq_ovrd_ftc;
 139 };
 140
 141 struct omap_pipe3 {
 142         void __iomem            *pll_ctrl_base;
 143         void __iomem            *phy_rx;
 144         void __iomem            *power_reg;
 145         void __iomem            *pll_reset_reg;
 146         struct pipe3_dpll_map   *dpll_map;
 147         enum pipe3_mode         mode;
 148         struct pipe3_settings   settings;
 149 };
 150
 151 struct pipe3_dpll_params {
 152         u16     m;
 153         u8      n;
 154         u8      freq:3;
 155         u8      sd;
 156         u32     mf;
 157 };
 158
 159 struct pipe3_dpll_map {
 160         unsigned long rate;
 161         struct pipe3_dpll_params params;
 162 };
 163
 164 struct pipe3_data {
 165         enum pipe3_mode mode;
 166         struct pipe3_dpll_map *dpll_map;
 167         struct pipe3_settings settings;
 168 };
 169
 170 static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
 171 {
 172         return readl(addr + offset);
 173 }
 174
 175 static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
 176                 u32 data)
 177 {
 178         writel(data, addr + offset);
 179 }
 180
 181 static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
 182                                                                         *pipe3)
 183 {
 184         u32 rate;
 185         struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
 186
 187         rate = get_sys_clk_freq();
 188
 189         for (; dpll_map->rate; dpll_map++) {
 190                 if (rate == dpll_map->rate)
 191                         return &dpll_map->params;
 192         }
 193
 194         printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
 195                __func__, rate);
 196         return NULL;
 197 }
 198
 199 static int omap_pipe3_wait_lock(struct omap_pipe3 *pipe3)
 200 {
 201         u32 val;
 202         int timeout = PLL_LOCK_TIME;
 203
 204         do {
 205                 mdelay(1);
 206                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 207                 if (val & PLL_LOCK)
 208                         break;
 209         } while (--timeout);
 210
 211         if (!(val & PLL_LOCK)) {
 212                 printf("%s: DPLL failed to lock\n", __func__);
 213                 return -EBUSY;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static int omap_pipe3_dpll_program(struct omap_pipe3 *pipe3)
 220 {
 221         u32                     val;
 222         struct pipe3_dpll_params *dpll_params;
 223
 224         dpll_params = omap_pipe3_get_dpll_params(pipe3);
 225         if (!dpll_params) {
 226                 printf("%s: Invalid DPLL parameters\n", __func__);
 227                 return -EINVAL;
 228         }
 229
 230         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 231         val &= ~PLL_REGN_MASK;
 232         val |= dpll_params->n << PLL_REGN_SHIFT;
 233         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 234
 235         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 236         val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);
 237         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 238         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 239
 240         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);
 241         val &= ~PLL_REGM_MASK;
 242         val |= dpll_params->m << PLL_REGM_SHIFT;
 243         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);
 244
 245         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);
 246         val &= ~PLL_REGM_F_MASK;
 247         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 248         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);
 249
 250         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);
 251         val &= ~PLL_SD_MASK;
 252         val |= dpll_params->sd << PLL_SD_SHIFT;
 253         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);
 254
 255         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 256
 257         return omap_pipe3_wait_lock(pipe3);
 258 }
 259
 260 static void omap_control_pipe3_power(struct omap_pipe3 *pipe3, int on)
 261 {
 262         u32 val, rate;
 263
 264         val = readl(pipe3->power_reg);
 265
 266         rate = get_sys_clk_freq();
 267         rate = rate/1000000;
 268
 269         if (on) {
 270                 val &= ~(PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 271                          PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 272                 val |= rate << PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 273                 writel(val, pipe3->power_reg);
 274
 275                 /* Power up TX before RX for SATA & USB */
 276                 val |= PIPE3_PHY_TX_POWERON;
 277                 writel(val, pipe3->power_reg);
 278
 279                 val |= PIPE3_PHY_RX_POWERON;
 280                 writel(val, pipe3->power_reg);
 281         } else {
 282                 val &= ~PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 283                 writel(val, pipe3->power_reg);
 284         }
 285 }
 286
 287 static void ti_pipe3_calibrate(struct omap_pipe3 *phy)
 288 {
 289         u32 val;
 290         struct pipe3_settings *s = &phy->settings;
 291
 292         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
 293         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 294         val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
 295         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
 296
 297         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
 298         val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
 299                  MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
 300                  MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
 301         val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
 302                 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
 303                 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
 304                 s->dig_lbw << MEM_CDR_LBW_SHIFT |
 305                 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
 306                 s->dig_stl << MEM_CDR_STL_SHIFT |
 307                 s->dig_thr << MEM_CDR_THR_SHIFT |
 308                 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
 309                 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
 310         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
 311
 312         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
 313         val &= ~MEM_DLL_TRIM_SEL_MASK;
 314         val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
 315         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
 316
 317         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
 318         val &= ~MEM_DLL_PHINT_RATE_MASK;
 319         val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
 320         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
 321
 322         val = omap_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
 323         val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
 324                  MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 325         val |= s->eq_lev << MEM_EQLEV_SHIFT |
 326                 s->eq_ftc << MEM_EQFTC_SHIFT |
 327                 s->eq_ctl << MEM_EQCTL_SHIFT |
 328                 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
 329                 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
 330         omap_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
 331
 332         if (phy->mode == PIPE3_MODE_SATA) {
 333                 val = omap_pipe3_readl(phy->phy_rx,
 334                                        SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
 335                 val &= ~MEM_CDR_LOS_SOURCE_MASK;
 336                 omap_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
 337                                   val);
 338         }
 339 }
 340
 341 static int pipe3_init(struct phy *phy)
 342 {
 343         int ret;
 344         u32 val;
 345         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 346
 347         /* Program the DPLL only if not locked */
 348         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 349         if (!(val & PLL_LOCK)) {
 350                 ret = omap_pipe3_dpll_program(pipe3);
 351                 if (ret)
 352                         return ret;
 353
 354                 ti_pipe3_calibrate(pipe3);
 355         } else {
 356                 /* else just bring it out of IDLE mode */
 357                 val = omap_pipe3_readl(pipe3->pll_ctrl_base,
 358                                        PLL_CONFIGURATION2);
 359                 if (val & PLL_IDLE) {
 360                         val &= ~PLL_IDLE;
 361                         omap_pipe3_writel(pipe3->pll_ctrl_base,
 362                                           PLL_CONFIGURATION2, val);
 363                         ret = omap_pipe3_wait_lock(pipe3);
 364                         if (ret)
 365                                 return ret;
 366                 }
 367         }
 368         return 0;
 369 }
 370
 371 static int pipe3_power_on(struct phy *phy)
 372 {
 373         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 374
 375         /* Power up the PHY */
 376         omap_control_pipe3_power(pipe3, 1);
 377
 378         return 0;
 379 }
 380
 381 static int pipe3_power_off(struct phy *phy)
 382 {
 383         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 384
 385         /* Power down the PHY */
 386         omap_control_pipe3_power(pipe3, 0);
 387
 388         return 0;
 389 }
 390
 391 static int pipe3_exit(struct phy *phy)
 392 {
 393         u32 val;
 394         int timeout = PLL_IDLE_TIME;
 395         struct omap_pipe3 *pipe3 = dev_get_priv(phy->dev);
 396
 397         pipe3_power_off(phy);
 398
 399         /* Put DPLL in IDLE mode */
 400         val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);
 401         val |= PLL_IDLE;
 402         omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);
 403
 404         /* wait for LDO and Oscillator to power down */
 405         do {
 406                 mdelay(1);
 407                 val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);
 408                 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 409                         break;
 410         } while (--timeout);
 411
 412         if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 413                 pr_err("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
 414                       __func__, val);
 415                 return -EBUSY;
 416         }
 417
 418         if (pipe3->pll_reset_reg) {
 419                 val = readl(pipe3->pll_reset_reg);
 420                 writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 421                 mdelay(1);
 422                 writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);
 423         }
 424
 425         return 0;
 426 }
 427
 428 static void *get_reg(struct udevice *dev, const char *name)
 429 {
 430         struct udevice *syscon;
 431         struct regmap *regmap;
 432         const fdt32_t *cell;
 433         int len, err;
 434         void *base;
 435
 436         err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
 437                                            name, &syscon);
 438         if (err) {
 439                 pr_err("unable to find syscon device for %s (%d)\n",
 440                       name, err);
 441                 return NULL;
 442         }
 443
 444         regmap = syscon_get_regmap(syscon);
 445         if (IS_ERR(regmap)) {
 446                 pr_err("unable to find regmap for %s (%ld)\n",
 447                       name, PTR_ERR(regmap));
 448                 return NULL;
 449         }
 450
 451         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
 452                            &len);
 453         if (len < 2*sizeof(fdt32_t)) {
 454                 pr_err("offset not available for %s\n", name);
 455                 return NULL;
 456         }
 457
 458         base = regmap_get_range(regmap, 0);
 459         if (!base)
 460                 return NULL;
 461
 462         return fdtdec_get_number(cell + 1, 1) + base;
 463 }
 464
 465 static int pipe3_phy_probe(struct udevice *dev)
 466 {
 467         fdt_addr_t addr;
 468         fdt_size_t sz;
 469         struct omap_pipe3 *pipe3 = dev_get_priv(dev);
 470         struct pipe3_data *data;
 471
 472         /* PHY_RX */
 473         addr = devfdt_get_addr_size_index(dev, 0, &sz);
 474         if (addr == FDT_ADDR_T_NONE) {
 475                 pr_err("missing phy_rx address\n");
 476                 return -EINVAL;
 477         }
 478
 479         pipe3->phy_rx = map_physmem(addr, sz, MAP_NOCACHE);
 480         if (!pipe3->phy_rx) {
 481                 pr_err("unable to remap phy_rx\n");
 482                 return -EINVAL;
 483         }
 484
 485         /* PLLCTRL */
 486         addr = devfdt_get_addr_size_index(dev, 2, &sz);
 487         if (addr == FDT_ADDR_T_NONE) {
 488                 pr_err("missing pll ctrl address\n");
 489                 return -EINVAL;
 490         }
 491
 492         pipe3->pll_ctrl_base = map_physmem(addr, sz, MAP_NOCACHE);
 493         if (!pipe3->pll_ctrl_base) {
 494                 pr_err("unable to remap pll ctrl\n");
 495                 return -EINVAL;
 496         }
 497
 498         pipe3->power_reg = get_reg(dev, "syscon-phy-power");
 499         if (!pipe3->power_reg)
 500                 return -EINVAL;
 501
 502         data = (struct pipe3_data *)dev_get_driver_data(dev);
 503         pipe3->mode = data->mode;
 504         pipe3->dpll_map = data->dpll_map;
 505         pipe3->settings = data->settings;
 506
 507         if (pipe3->mode == PIPE3_MODE_SATA) {
 508                 pipe3->pll_reset_reg = get_reg(dev, "syscon-pllreset");
 509                 if (!pipe3->pll_reset_reg)
 510                         return -EINVAL;
 511         }
 512
 513         return 0;
 514 }
 515
 516 static struct pipe3_dpll_map dpll_map_sata[] = {
 517         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 518         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 519         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 520         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 521         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 522         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 523         { },                                    /* Terminator */
 524 };
 525
 526 static struct pipe3_dpll_map dpll_map_usb[] = {
 527         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 528         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 529         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 530         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 531         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 532         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 533         { },                                    /* Terminator */
 534 };
 535
 536 static struct pipe3_data data_usb = {
 537         .mode = PIPE3_MODE_USBSS,
 538         .dpll_map = dpll_map_usb,
 539         .settings = {
 540         /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */
 541                 .ana_interface = INTERFACE_MODE_USBSS,
 542                 .ana_losd = 0xa,
 543                 .dig_fastlock = 1,
 544                 .dig_lbw = 3,
 545                 .dig_stepcnt = 0,
 546                 .dig_stl = 0x3,
 547                 .dig_thr = 1,
 548                 .dig_thr_mode = 1,
 549                 .dig_2ndo_sdm_mode = 0,
 550                 .dig_hs_rate = 0,
 551                 .dig_ovrd_hs_rate = 1,
 552                 .dll_trim_sel = 0x2,
 553                 .dll_phint_rate = 0x3,
 554                 .eq_lev = 0,
 555                 .eq_ftc = 0,
 556                 .eq_ctl = 0x9,
 557                 .eq_ovrd_lev = 0,
 558                 .eq_ovrd_ftc = 0,
 559         },
 560 };
 561
 562 static struct pipe3_data data_sata = {
 563         .mode = PIPE3_MODE_SATA,
 564         .dpll_map = dpll_map_sata,
 565         .settings = {
 566         /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */
 567                 .ana_interface = INTERFACE_MODE_SATA_3P0,
 568                 .ana_losd = 0x5,
 569                 .dig_fastlock = 1,
 570                 .dig_lbw = 3,
 571                 .dig_stepcnt = 0,
 572                 .dig_stl = 0x3,
 573                 .dig_thr = 1,
 574                 .dig_thr_mode = 1,
 575                 .dig_2ndo_sdm_mode = 0,
 576                 .dig_hs_rate = 0,       /* Not in TRM preferred settings */
 577                 .dig_ovrd_hs_rate = 0,  /* Not in TRM preferred settings */
 578                 .dll_trim_sel = 0x1,
 579                 .dll_phint_rate = 0x2,  /* for 1.5 GHz DPLL clock */
 580                 .eq_lev = 0,
 581                 .eq_ftc = 0x1f,
 582                 .eq_ctl = 0,
 583                 .eq_ovrd_lev = 1,
 584                 .eq_ovrd_ftc = 1,
 585         },
 586 };
 587
 588 static const struct udevice_id pipe3_phy_ids[] = {
 589         { .compatible = "ti,phy-pipe3-sata", .data = (ulong)&data_sata },
 590         { .compatible = "ti,omap-usb3", .data = (ulong)&data_usb},
 591         { }
 592 };
 593
 594 static struct phy_ops pipe3_phy_ops = {
 595         .init = pipe3_init,
 596         .power_on = pipe3_power_on,
 597         .power_off = pipe3_power_off,
 598         .exit = pipe3_exit,
 599 };
 600
 601 U_BOOT_DRIVER(pipe3_phy) = {
 602         .name   = "pipe3_phy",
 603         .id     = UCLASS_PHY,
 604         .of_match = pipe3_phy_ids,
 605         .ops = &pipe3_phy_ops,
 606         .probe = pipe3_phy_probe,
 607         .priv_auto      = sizeof(struct omap_pipe3),
 608 };