drivers/phy/ti/phy-ti-pipe3.c

   1 /*
   2  * phy-ti-pipe3 - PIPE3 PHY driver.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/slab.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/of.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/io.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/delay.h>
  29 #include <linux/phy/omap_control_phy.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/mfd/syscon.h>
  32 #include <linux/regmap.h>
  33
  34 #define PLL_STATUS              0x00000004
  35 #define PLL_GO                  0x00000008
  36 #define PLL_CONFIGURATION1      0x0000000C
  37 #define PLL_CONFIGURATION2      0x00000010
  38 #define PLL_CONFIGURATION3      0x00000014
  39 #define PLL_CONFIGURATION4      0x00000020
  40
  41 #define PLL_REGM_MASK           0x001FFE00
  42 #define PLL_REGM_SHIFT          0x9
  43 #define PLL_REGM_F_MASK         0x0003FFFF
  44 #define PLL_REGM_F_SHIFT        0x0
  45 #define PLL_REGN_MASK           0x000001FE
  46 #define PLL_REGN_SHIFT          0x1
  47 #define PLL_SELFREQDCO_MASK     0x0000000E
  48 #define PLL_SELFREQDCO_SHIFT    0x1
  49 #define PLL_SD_MASK             0x0003FC00
  50 #define PLL_SD_SHIFT            10
  51 #define SET_PLL_GO              0x1
  52 #define PLL_LDOPWDN             BIT(15)
  53 #define PLL_TICOPWDN            BIT(16)
  54 #define PLL_LOCK                0x2
  55 #define PLL_IDLE                0x1
  56
  57 #define SATA_PLL_SOFT_RESET     BIT(18)
  58
  59 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK   0x003FC000
  60 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT  14
  61
  62 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK  0xFFC00000
  63 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
  64
  65 #define PIPE3_PHY_TX_RX_POWERON         0x3
  66 #define PIPE3_PHY_TX_RX_POWEROFF        0x0
  67
  68 #define PCIE_PCS_MASK                   0xFF0000
  69 #define PCIE_PCS_DELAY_COUNT_SHIFT      0x10
  70
  71 #define PCIEPHYRX_ANA_PROGRAMMABILITY   0x0000000C
  72 #define INTERFACE_MASK                  GENMASK(31, 27)
  73 #define INTERFACE_SHIFT                 27
  74 #define LOSD_MASK                       GENMASK(17, 14)
  75 #define LOSD_SHIFT                      14
  76 #define MEM_PLLDIV                      GENMASK(6, 5)
  77
  78 #define PCIEPHYRX_TRIM                  0x0000001C
  79 #define MEM_DLL_TRIM_SEL                GENMASK(31, 30)
  80 #define MEM_DLL_TRIM_SHIFT              30
  81
  82 #define PCIEPHYRX_DLL                   0x00000024
  83 #define MEM_DLL_PHINT_RATE              GENMASK(31, 30)
  84
  85 #define PCIEPHYRX_DIGITAL_MODES         0x00000028
  86 #define MEM_CDR_FASTLOCK                BIT(23)
  87 #define MEM_CDR_LBW                     GENMASK(22, 21)
  88 #define MEM_CDR_STEPCNT                 GENMASK(20, 19)
  89 #define MEM_CDR_STL_MASK                GENMASK(18, 16)
  90 #define MEM_CDR_STL_SHIFT               16
  91 #define MEM_CDR_THR_MASK                GENMASK(15, 13)
  92 #define MEM_CDR_THR_SHIFT               13
  93 #define MEM_CDR_THR_MODE                BIT(12)
  94 #define MEM_CDR_CDR_2NDO_SDM_MODE       BIT(11)
  95 #define MEM_OVRD_HS_RATE                BIT(26)
  96
  97 #define PCIEPHYRX_EQUALIZER             0x00000038
  98 #define MEM_EQLEV                       GENMASK(31, 16)
  99 #define MEM_EQFTC                       GENMASK(15, 11)
 100 #define MEM_EQCTL                       GENMASK(10, 7)
 101 #define MEM_EQCTL_SHIFT                 7
 102 #define MEM_OVRD_EQLEV                  BIT(2)
 103 #define MEM_OVRD_EQFTC                  BIT(1)
 104
 105 /*
 106  * This is an Empirical value that works, need to confirm the actual
 107  * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
 108  * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
 109  */
 110 #define PLL_IDLE_TIME   100     /* in milliseconds */
 111 #define PLL_LOCK_TIME   100     /* in milliseconds */
 112
 113 struct pipe3_dpll_params {
 114         u16     m;
 115         u8      n;
 116         u8      freq:3;
 117         u8      sd;
 118         u32     mf;
 119 };
 120
 121 struct pipe3_dpll_map {
 122         unsigned long rate;
 123         struct pipe3_dpll_params params;
 124 };
 125
 126 struct ti_pipe3 {
 127         void __iomem            *pll_ctrl_base;
 128         void __iomem            *phy_rx;
 129         void __iomem            *phy_tx;
 130         struct device           *dev;
 131         struct device           *control_dev;
 132         struct clk              *wkupclk;
 133         struct clk              *sys_clk;
 134         struct clk              *refclk;
 135         struct clk              *div_clk;
 136         struct pipe3_dpll_map   *dpll_map;
 137         struct regmap           *phy_power_syscon; /* ctrl. reg. acces */
 138         struct regmap           *pcs_syscon; /* ctrl. reg. acces */
 139         struct regmap           *dpll_reset_syscon; /* ctrl. reg. acces */
 140         unsigned int            dpll_reset_reg; /* reg. index within syscon */
 141         unsigned int            power_reg; /* power reg. index within syscon */
 142         unsigned int            pcie_pcs_reg; /* pcs reg. index in syscon */
 143         bool                    sata_refclk_enabled;
 144 };
 145
 146 static struct pipe3_dpll_map dpll_map_usb[] = {
 147         {12000000, {1250, 5, 4, 20, 0} },       /* 12 MHz */
 148         {16800000, {3125, 20, 4, 20, 0} },      /* 16.8 MHz */
 149         {19200000, {1172, 8, 4, 20, 65537} },   /* 19.2 MHz */
 150         {20000000, {1000, 7, 4, 10, 0} },       /* 20 MHz */
 151         {26000000, {1250, 12, 4, 20, 0} },      /* 26 MHz */
 152         {38400000, {3125, 47, 4, 20, 92843} },  /* 38.4 MHz */
 153         { },                                    /* Terminator */
 154 };
 155
 156 static struct pipe3_dpll_map dpll_map_sata[] = {
 157         {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
 158         {16800000, {625, 6, 4, 7, 0} },         /* 16.8 MHz */
 159         {19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
 160         {20000000, {750, 9, 4, 6, 0} },         /* 20 MHz */
 161         {26000000, {750, 12, 4, 6, 0} },        /* 26 MHz */
 162         {38400000, {625, 15, 4, 6, 0} },        /* 38.4 MHz */
 163         { },                                    /* Terminator */
 164 };
 165
 166 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
 167 {
 168         return __raw_readl(addr + offset);
 169 }
 170
 171 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
 172         u32 data)
 173 {
 174         __raw_writel(data, addr + offset);
 175 }
 176
 177 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
 178 {
 179         unsigned long rate;
 180         struct pipe3_dpll_map *dpll_map = phy->dpll_map;
 181
 182         rate = clk_get_rate(phy->sys_clk);
 183
 184         for (; dpll_map->rate; dpll_map++) {
 185                 if (rate == dpll_map->rate)
 186                         return &dpll_map->params;
 187         }
 188
 189         dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
 190
 191         return NULL;
 192 }
 193
 194 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
 195 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
 196
 197 static int ti_pipe3_power_off(struct phy *x)
 198 {
 199         u32 val;
 200         int ret;
 201         struct ti_pipe3 *phy = phy_get_drvdata(x);
 202
 203         if (!phy->phy_power_syscon) {
 204                 omap_control_phy_power(phy->control_dev, 0);
 205                 return 0;
 206         }
 207
 208         val = PIPE3_PHY_TX_RX_POWEROFF << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 209
 210         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 211                                  PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val);
 212         return ret;
 213 }
 214
 215 static int ti_pipe3_power_on(struct phy *x)
 216 {
 217         u32 val;
 218         u32 mask;
 219         int ret;
 220         unsigned long rate;
 221         struct ti_pipe3 *phy = phy_get_drvdata(x);
 222
 223         if (!phy->phy_power_syscon) {
 224                 omap_control_phy_power(phy->control_dev, 1);
 225                 return 0;
 226         }
 227
 228         rate = clk_get_rate(phy->sys_clk);
 229         if (!rate) {
 230                 dev_err(phy->dev, "Invalid clock rate\n");
 231                 return -EINVAL;
 232         }
 233         rate = rate / 1000000;
 234         mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 235                   OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
 236         val = PIPE3_PHY_TX_RX_POWERON << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 237         val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 238
 239         ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
 240                                  mask, val);
 241         return ret;
 242 }
 243
 244 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
 245 {
 246         u32             val;
 247         unsigned long   timeout;
 248
 249         timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
 250         do {
 251                 cpu_relax();
 252                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 253                 if (val & PLL_LOCK)
 254                         return 0;
 255         } while (!time_after(jiffies, timeout));
 256
 257         dev_err(phy->dev, "DPLL failed to lock\n");
 258         return -EBUSY;
 259 }
 260
 261 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
 262 {
 263         u32                     val;
 264         struct pipe3_dpll_params *dpll_params;
 265
 266         dpll_params = ti_pipe3_get_dpll_params(phy);
 267         if (!dpll_params)
 268                 return -EINVAL;
 269
 270         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 271         val &= ~PLL_REGN_MASK;
 272         val |= dpll_params->n << PLL_REGN_SHIFT;
 273         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 274
 275         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 276         val &= ~PLL_SELFREQDCO_MASK;
 277         val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
 278         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 279
 280         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
 281         val &= ~PLL_REGM_MASK;
 282         val |= dpll_params->m << PLL_REGM_SHIFT;
 283         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
 284
 285         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
 286         val &= ~PLL_REGM_F_MASK;
 287         val |= dpll_params->mf << PLL_REGM_F_SHIFT;
 288         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
 289
 290         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
 291         val &= ~PLL_SD_MASK;
 292         val |= dpll_params->sd << PLL_SD_SHIFT;
 293         ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
 294
 295         ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
 296
 297         return ti_pipe3_dpll_wait_lock(phy);
 298 }
 299
 300 static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
 301 {
 302         u32 val;
 303
 304         val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY);
 305         val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
 306         val = (0x1 << INTERFACE_SHIFT | 0xA << LOSD_SHIFT);
 307         ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY, val);
 308
 309         val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES);
 310         val &= ~(MEM_CDR_STEPCNT | MEM_CDR_STL_MASK | MEM_CDR_THR_MASK |
 311                  MEM_CDR_CDR_2NDO_SDM_MODE | MEM_OVRD_HS_RATE);
 312         val |= (MEM_CDR_FASTLOCK | MEM_CDR_LBW | 0x3 << MEM_CDR_STL_SHIFT |
 313                 0x1 << MEM_CDR_THR_SHIFT | MEM_CDR_THR_MODE);
 314         ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES, val);
 315
 316         val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_TRIM);
 317         val &= ~MEM_DLL_TRIM_SEL;
 318         val |= 0x2 << MEM_DLL_TRIM_SHIFT;
 319         ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_TRIM, val);
 320
 321         val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DLL);
 322         val |= MEM_DLL_PHINT_RATE;
 323         ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DLL, val);
 324
 325         val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_EQUALIZER);
 326         val &= ~(MEM_EQLEV | MEM_EQCTL | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
 327         val |= MEM_EQFTC | 0x1 << MEM_EQCTL_SHIFT;
 328         ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_EQUALIZER, val);
 329 }
 330
 331 static int ti_pipe3_init(struct phy *x)
 332 {
 333         struct ti_pipe3 *phy = phy_get_drvdata(x);
 334         u32 val;
 335         int ret = 0;
 336
 337         ti_pipe3_enable_clocks(phy);
 338         /*
 339          * Set pcie_pcs register to 0x96 for proper functioning of phy
 340          * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
 341          * 18-1804.
 342          */
 343         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 344                 if (!phy->pcs_syscon) {
 345                         omap_control_pcie_pcs(phy->control_dev, 0x96);
 346                         return 0;
 347                 }
 348
 349                 val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
 350                 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
 351                                          PCIE_PCS_MASK, val);
 352                 if (ret)
 353                         return ret;
 354
 355                 ti_pipe3_calibrate(phy);
 356
 357                 return 0;
 358         }
 359
 360         /* Bring it out of IDLE if it is IDLE */
 361         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 362         if (val & PLL_IDLE) {
 363                 val &= ~PLL_IDLE;
 364                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 365                 ret = ti_pipe3_dpll_wait_lock(phy);
 366         }
 367
 368         /* SATA has issues if re-programmed when locked */
 369         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 370         if ((val & PLL_LOCK) && of_device_is_compatible(phy->dev->of_node,
 371                                                         "ti,phy-pipe3-sata"))
 372                 return ret;
 373
 374         /* Program the DPLL */
 375         ret = ti_pipe3_dpll_program(phy);
 376         if (ret) {
 377                 ti_pipe3_disable_clocks(phy);
 378                 return -EINVAL;
 379         }
 380
 381         return ret;
 382 }
 383
 384 static int ti_pipe3_exit(struct phy *x)
 385 {
 386         struct ti_pipe3 *phy = phy_get_drvdata(x);
 387         u32 val;
 388         unsigned long timeout;
 389
 390         /* If dpll_reset_syscon is not present we wont power down SATA DPLL
 391          * due to Errata i783
 392          */
 393         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") &&
 394             !phy->dpll_reset_syscon)
 395                 return 0;
 396
 397         /* PCIe doesn't have internal DPLL */
 398         if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) {
 399                 /* Put DPLL in IDLE mode */
 400                 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
 401                 val |= PLL_IDLE;
 402                 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
 403
 404                 /* wait for LDO and Oscillator to power down */
 405                 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
 406                 do {
 407                         cpu_relax();
 408                         val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
 409                         if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
 410                                 break;
 411                 } while (!time_after(jiffies, timeout));
 412
 413                 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
 414                         dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
 415                                 val);
 416                         return -EBUSY;
 417                 }
 418         }
 419
 420         /* i783: SATA needs control bit toggle after PLL unlock */
 421         if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) {
 422                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 423                                    SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
 424                 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
 425                                    SATA_PLL_SOFT_RESET, 0);
 426         }
 427
 428         ti_pipe3_disable_clocks(phy);
 429
 430         return 0;
 431 }
 432 static const struct phy_ops ops = {
 433         .init           = ti_pipe3_init,
 434         .exit           = ti_pipe3_exit,
 435         .power_on       = ti_pipe3_power_on,
 436         .power_off      = ti_pipe3_power_off,
 437         .owner          = THIS_MODULE,
 438 };
 439
 440 static const struct of_device_id ti_pipe3_id_table[];
 441
 442 static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
 443 {
 444         struct clk *clk;
 445         struct device *dev = phy->dev;
 446         struct device_node *node = dev->of_node;
 447
 448         phy->refclk = devm_clk_get(dev, "refclk");
 449         if (IS_ERR(phy->refclk)) {
 450                 dev_err(dev, "unable to get refclk\n");
 451                 /* older DTBs have missing refclk in SATA PHY
 452                  * so don't bail out in case of SATA PHY.
 453                  */
 454                 if (!of_device_is_compatible(node, "ti,phy-pipe3-sata"))
 455                         return PTR_ERR(phy->refclk);
 456         }
 457
 458         if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 459                 phy->wkupclk = devm_clk_get(dev, "wkupclk");
 460                 if (IS_ERR(phy->wkupclk)) {
 461                         dev_err(dev, "unable to get wkupclk\n");
 462                         return PTR_ERR(phy->wkupclk);
 463                 }
 464         } else {
 465                 phy->wkupclk = ERR_PTR(-ENODEV);
 466         }
 467
 468         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie") ||
 469             phy->phy_power_syscon) {
 470                 phy->sys_clk = devm_clk_get(dev, "sysclk");
 471                 if (IS_ERR(phy->sys_clk)) {
 472                         dev_err(dev, "unable to get sysclk\n");
 473                         return -EINVAL;
 474                 }
 475         }
 476
 477         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 478                 clk = devm_clk_get(dev, "dpll_ref");
 479                 if (IS_ERR(clk)) {
 480                         dev_err(dev, "unable to get dpll ref clk\n");
 481                         return PTR_ERR(clk);
 482                 }
 483                 clk_set_rate(clk, 1500000000);
 484
 485                 clk = devm_clk_get(dev, "dpll_ref_m2");
 486                 if (IS_ERR(clk)) {
 487                         dev_err(dev, "unable to get dpll ref m2 clk\n");
 488                         return PTR_ERR(clk);
 489                 }
 490                 clk_set_rate(clk, 100000000);
 491
 492                 clk = devm_clk_get(dev, "phy-div");
 493                 if (IS_ERR(clk)) {
 494                         dev_err(dev, "unable to get phy-div clk\n");
 495                         return PTR_ERR(clk);
 496                 }
 497                 clk_set_rate(clk, 100000000);
 498
 499                 phy->div_clk = devm_clk_get(dev, "div-clk");
 500                 if (IS_ERR(phy->div_clk)) {
 501                         dev_err(dev, "unable to get div-clk\n");
 502                         return PTR_ERR(phy->div_clk);
 503                 }
 504         } else {
 505                 phy->div_clk = ERR_PTR(-ENODEV);
 506         }
 507
 508         return 0;
 509 }
 510
 511 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
 512 {
 513         struct device *dev = phy->dev;
 514         struct device_node *node = dev->of_node;
 515         struct device_node *control_node;
 516         struct platform_device *control_pdev;
 517
 518         phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
 519                                                         "syscon-phy-power");
 520         if (IS_ERR(phy->phy_power_syscon)) {
 521                 dev_dbg(dev,
 522                         "can't get syscon-phy-power, using control device\n");
 523                 phy->phy_power_syscon = NULL;
 524         } else {
 525                 if (of_property_read_u32_index(node,
 526                                                "syscon-phy-power", 1,
 527                                                &phy->power_reg)) {
 528                         dev_err(dev, "couldn't get power reg. offset\n");
 529                         return -EINVAL;
 530                 }
 531         }
 532
 533         if (!phy->phy_power_syscon) {
 534                 control_node = of_parse_phandle(node, "ctrl-module", 0);
 535                 if (!control_node) {
 536                         dev_err(dev, "Failed to get control device phandle\n");
 537                         return -EINVAL;
 538                 }
 539
 540                 control_pdev = of_find_device_by_node(control_node);
 541                 if (!control_pdev) {
 542                         dev_err(dev, "Failed to get control device\n");
 543                         return -EINVAL;
 544                 }
 545
 546                 phy->control_dev = &control_pdev->dev;
 547         }
 548
 549         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) {
 550                 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
 551                                                                   "syscon-pcs");
 552                 if (IS_ERR(phy->pcs_syscon)) {
 553                         dev_dbg(dev,
 554                                 "can't get syscon-pcs, using omap control\n");
 555                         phy->pcs_syscon = NULL;
 556                 } else {
 557                         if (of_property_read_u32_index(node,
 558                                                        "syscon-pcs", 1,
 559                                                        &phy->pcie_pcs_reg)) {
 560                                 dev_err(dev,
 561                                         "couldn't get pcie pcs reg. offset\n");
 562                                 return -EINVAL;
 563                         }
 564                 }
 565         }
 566
 567         if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 568                 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
 569                                                         "syscon-pllreset");
 570                 if (IS_ERR(phy->dpll_reset_syscon)) {
 571                         dev_info(dev,
 572                                  "can't get syscon-pllreset, sata dpll won't idle\n");
 573                         phy->dpll_reset_syscon = NULL;
 574                 } else {
 575                         if (of_property_read_u32_index(node,
 576                                                        "syscon-pllreset", 1,
 577                                                        &phy->dpll_reset_reg)) {
 578                                 dev_err(dev,
 579                                         "couldn't get pllreset reg. offset\n");
 580                                 return -EINVAL;
 581                         }
 582                 }
 583         }
 584
 585         return 0;
 586 }
 587
 588 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
 589 {
 590         struct resource *res;
 591         struct device *dev = phy->dev;
 592         struct device_node *node = dev->of_node;
 593         struct platform_device *pdev = to_platform_device(dev);
 594
 595         if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie"))
 596                 return 0;
 597
 598         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 599                                            "phy_rx");
 600         phy->phy_rx = devm_ioremap_resource(dev, res);
 601         if (IS_ERR(phy->phy_rx))
 602                 return PTR_ERR(phy->phy_rx);
 603
 604         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 605                                            "phy_tx");
 606         phy->phy_tx = devm_ioremap_resource(dev, res);
 607
 608         return PTR_ERR_OR_ZERO(phy->phy_tx);
 609 }
 610
 611 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
 612 {
 613         struct resource *res;
 614         const struct of_device_id *match;
 615         struct device *dev = phy->dev;
 616         struct device_node *node = dev->of_node;
 617         struct platform_device *pdev = to_platform_device(dev);
 618
 619         if (of_device_is_compatible(node, "ti,phy-pipe3-pcie"))
 620                 return 0;
 621
 622         match = of_match_device(ti_pipe3_id_table, dev);
 623         if (!match)
 624                 return -EINVAL;
 625
 626         phy->dpll_map = (struct pipe3_dpll_map *)match->data;
 627         if (!phy->dpll_map) {
 628                 dev_err(dev, "no DPLL data\n");
 629                 return -EINVAL;
 630         }
 631
 632         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 633                                            "pll_ctrl");
 634         phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
 635         return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
 636 }
 637
 638 static int ti_pipe3_probe(struct platform_device *pdev)
 639 {
 640         struct ti_pipe3 *phy;
 641         struct phy *generic_phy;
 642         struct phy_provider *phy_provider;
 643         struct device_node *node = pdev->dev.of_node;
 644         struct device *dev = &pdev->dev;
 645         int ret;
 646
 647         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 648         if (!phy)
 649                 return -ENOMEM;
 650
 651         phy->dev                = dev;
 652
 653         ret = ti_pipe3_get_pll_base(phy);
 654         if (ret)
 655                 return ret;
 656
 657         ret = ti_pipe3_get_tx_rx_base(phy);
 658         if (ret)
 659                 return ret;
 660
 661         ret = ti_pipe3_get_sysctrl(phy);
 662         if (ret)
 663                 return ret;
 664
 665         ret = ti_pipe3_get_clk(phy);
 666         if (ret)
 667                 return ret;
 668
 669         platform_set_drvdata(pdev, phy);
 670         pm_runtime_enable(dev);
 671
 672         /*
 673          * Prevent auto-disable of refclk for SATA PHY due to Errata i783
 674          */
 675         if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) {
 676                 if (!IS_ERR(phy->refclk)) {
 677                         clk_prepare_enable(phy->refclk);
 678                         phy->sata_refclk_enabled = true;
 679                 }
 680         }
 681
 682         generic_phy = devm_phy_create(dev, NULL, &ops);
 683         if (IS_ERR(generic_phy))
 684                 return PTR_ERR(generic_phy);
 685
 686         phy_set_drvdata(generic_phy, phy);
 687
 688         ti_pipe3_power_off(generic_phy);
 689
 690         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 691         return PTR_ERR_OR_ZERO(phy_provider);
 692 }
 693
 694 static int ti_pipe3_remove(struct platform_device *pdev)
 695 {
 696         pm_runtime_disable(&pdev->dev);
 697
 698         return 0;
 699 }
 700
 701 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
 702 {
 703         int ret = 0;
 704
 705         if (!IS_ERR(phy->refclk)) {
 706                 ret = clk_prepare_enable(phy->refclk);
 707                 if (ret) {
 708                         dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
 709                         return ret;
 710                 }
 711         }
 712
 713         if (!IS_ERR(phy->wkupclk)) {
 714                 ret = clk_prepare_enable(phy->wkupclk);
 715                 if (ret) {
 716                         dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
 717                         goto disable_refclk;
 718                 }
 719         }
 720
 721         if (!IS_ERR(phy->div_clk)) {
 722                 ret = clk_prepare_enable(phy->div_clk);
 723                 if (ret) {
 724                         dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
 725                         goto disable_wkupclk;
 726                 }
 727         }
 728
 729         return 0;
 730
 731 disable_wkupclk:
 732         if (!IS_ERR(phy->wkupclk))
 733                 clk_disable_unprepare(phy->wkupclk);
 734
 735 disable_refclk:
 736         if (!IS_ERR(phy->refclk))
 737                 clk_disable_unprepare(phy->refclk);
 738
 739         return ret;
 740 }
 741
 742 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
 743 {
 744         if (!IS_ERR(phy->wkupclk))
 745                 clk_disable_unprepare(phy->wkupclk);
 746         if (!IS_ERR(phy->refclk)) {
 747                 clk_disable_unprepare(phy->refclk);
 748                 /*
 749                  * SATA refclk needs an additional disable as we left it
 750                  * on in probe to avoid Errata i783
 751                  */
 752                 if (phy->sata_refclk_enabled) {
 753                         clk_disable_unprepare(phy->refclk);
 754                         phy->sata_refclk_enabled = false;
 755                 }
 756         }
 757
 758         if (!IS_ERR(phy->div_clk))
 759                 clk_disable_unprepare(phy->div_clk);
 760 }
 761
 762 static const struct of_device_id ti_pipe3_id_table[] = {
 763         {
 764                 .compatible = "ti,phy-usb3",
 765                 .data = dpll_map_usb,
 766         },
 767         {
 768                 .compatible = "ti,omap-usb3",
 769                 .data = dpll_map_usb,
 770         },
 771         {
 772                 .compatible = "ti,phy-pipe3-sata",
 773                 .data = dpll_map_sata,
 774         },
 775         {
 776                 .compatible = "ti,phy-pipe3-pcie",
 777         },
 778         {}
 779 };
 780 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
 781
 782 static struct platform_driver ti_pipe3_driver = {
 783         .probe          = ti_pipe3_probe,
 784         .remove         = ti_pipe3_remove,
 785         .driver         = {
 786                 .name   = "ti-pipe3",
 787                 .of_match_table = ti_pipe3_id_table,
 788         },
 789 };
 790
 791 module_platform_driver(ti_pipe3_driver);
 792
 793 MODULE_ALIAS("platform:ti_pipe3");
 794 MODULE_AUTHOR("Texas Instruments Inc.");
 795 MODULE_DESCRIPTION("TI PIPE3 phy driver");
 796 MODULE_LICENSE("GPL v2");