1 // SPDX-License-Identifier: GPL-2.0
3 * STMicroelectronics STM32 USB PHY Controller driver
5 * Copyright (C) 2018 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
8 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/reset.h>
18 #include <linux/units.h>
20 #define STM32_USBPHYC_PLL 0x0
21 #define STM32_USBPHYC_MISC 0x8
22 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
23 #define STM32_USBPHYC_VERSION 0x3F4
25 /* STM32_USBPHYC_PLL bit fields */
26 #define PLLNDIV GENMASK(6, 0)
27 #define PLLFRACIN GENMASK(25, 10)
29 #define PLLSTRB BIT(27)
30 #define PLLSTRBYP BIT(28)
31 #define PLLFRACCTL BIT(29)
32 #define PLLDITHEN0 BIT(30)
33 #define PLLDITHEN1 BIT(31)
35 /* STM32_USBPHYC_MISC bit fields */
36 #define SWITHOST BIT(0)
38 /* STM32_USBPHYC_MONITOR bit fields */
39 #define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
40 #define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
41 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
42 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
44 /* STM32_USBPHYC_VERSION bit fields */
45 #define MINREV GENMASK(3, 0)
46 #define MAJREV GENMASK(7, 4)
48 #define PLL_FVCO_MHZ 2880
49 #define PLL_INFF_MIN_RATE_HZ 19200000
50 #define PLL_INFF_MAX_RATE_HZ 38400000
57 struct stm32_usbphyc_phy {
59 struct stm32_usbphyc *usbphyc;
60 struct regulator *vbus;
65 struct stm32_usbphyc {
69 struct reset_control *rst;
70 struct stm32_usbphyc_phy **phys;
72 struct regulator *vdda1v1;
73 struct regulator *vdda1v8;
75 struct clk_hw clk48_hw;
79 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
81 writel_relaxed(readl_relaxed(reg) | bits, reg);
84 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
86 writel_relaxed(readl_relaxed(reg) & ~bits, reg);
89 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
93 ret = regulator_enable(usbphyc->vdda1v1);
97 ret = regulator_enable(usbphyc->vdda1v8);
104 regulator_disable(usbphyc->vdda1v1);
109 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
113 ret = regulator_disable(usbphyc->vdda1v8);
117 ret = regulator_disable(usbphyc->vdda1v1);
124 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
125 struct pll_params *pll_params)
127 unsigned long long fvco, ndiv, frac;
130 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
133 * | NDIV = integer part of input bits to set the LDF
134 * |_FRACT = fractional part of input bits to set the LDF
135 * => PLLNDIV = integer part of (FVCO / (INFF*2))
136 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
137 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
139 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
142 do_div(ndiv, (clk_rate * 2));
143 pll_params->ndiv = (u8)ndiv;
145 frac = fvco * (1 << 16);
146 do_div(frac, (clk_rate * 2));
147 frac = frac - (ndiv * (1 << 16));
148 pll_params->frac = (u16)frac;
151 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
153 struct pll_params pll_params;
154 u32 clk_rate = clk_get_rate(usbphyc->clk);
158 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
159 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
160 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
165 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
166 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
167 frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
169 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
172 usbphyc_pll |= PLLFRACCTL | frac;
174 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
176 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
177 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
178 FIELD_GET(PLLFRACIN, usbphyc_pll));
183 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
185 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
188 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
190 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
191 if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
192 dev_err(usbphyc->dev, "PLL not reset\n");
194 return stm32_usbphyc_regulators_disable(usbphyc);
197 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
199 /* Check if a phy port is still active or clk48 in use */
200 if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
203 return __stm32_usbphyc_pll_disable(usbphyc);
206 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
208 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
209 bool pllen = readl_relaxed(pll_reg) & PLLEN;
213 * Check if a phy port or clk48 prepare has configured the pll
214 * and ensure the PLL is enabled
216 if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
221 * PLL shouldn't be enabled without known consumer,
222 * disable it and reinit n_pll_cons
224 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
226 ret = __stm32_usbphyc_pll_disable(usbphyc);
231 ret = stm32_usbphyc_regulators_enable(usbphyc);
235 ret = stm32_usbphyc_pll_init(usbphyc);
239 stm32_usbphyc_set_bits(pll_reg, PLLEN);
244 stm32_usbphyc_regulators_disable(usbphyc);
247 atomic_dec(&usbphyc->n_pll_cons);
252 static int stm32_usbphyc_phy_init(struct phy *phy)
254 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
255 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
256 u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
257 u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
258 STM32_USBPHYC_MON_SEL_LOCKP);
262 ret = stm32_usbphyc_pll_enable(usbphyc);
266 /* Check that PLL Lock input to PHY is High */
267 writel_relaxed(monsel, usbphyc->base + reg_mon);
268 ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
269 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
272 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
273 (u32)(monout & STM32_USBPHYC_MON_OUT));
277 usbphyc_phy->active = true;
282 stm32_usbphyc_pll_disable(usbphyc);
287 static int stm32_usbphyc_phy_exit(struct phy *phy)
289 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
290 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
292 usbphyc_phy->active = false;
294 return stm32_usbphyc_pll_disable(usbphyc);
297 static int stm32_usbphyc_phy_power_on(struct phy *phy)
299 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
301 if (usbphyc_phy->vbus)
302 return regulator_enable(usbphyc_phy->vbus);
307 static int stm32_usbphyc_phy_power_off(struct phy *phy)
309 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
311 if (usbphyc_phy->vbus)
312 return regulator_disable(usbphyc_phy->vbus);
317 static const struct phy_ops stm32_usbphyc_phy_ops = {
318 .init = stm32_usbphyc_phy_init,
319 .exit = stm32_usbphyc_phy_exit,
320 .power_on = stm32_usbphyc_phy_power_on,
321 .power_off = stm32_usbphyc_phy_power_off,
322 .owner = THIS_MODULE,
325 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
327 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
329 return stm32_usbphyc_pll_enable(usbphyc);
332 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
334 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
336 stm32_usbphyc_pll_disable(usbphyc);
339 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
344 static const struct clk_ops usbphyc_clk48_ops = {
345 .prepare = stm32_usbphyc_clk48_prepare,
346 .unprepare = stm32_usbphyc_clk48_unprepare,
347 .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
350 static void stm32_usbphyc_clk48_unregister(void *data)
352 struct stm32_usbphyc *usbphyc = data;
354 of_clk_del_provider(usbphyc->dev->of_node);
355 clk_hw_unregister(&usbphyc->clk48_hw);
358 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
360 struct device_node *node = usbphyc->dev->of_node;
361 struct clk_init_data init = { };
364 init.name = "ck_usbo_48m";
365 init.ops = &usbphyc_clk48_ops;
367 usbphyc->clk48_hw.init = &init;
369 ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
373 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
375 clk_hw_unregister(&usbphyc->clk48_hw);
380 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
384 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
387 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
389 usbphyc->switch_setup = utmi_switch;
392 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
393 struct of_phandle_args *args)
395 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
396 struct stm32_usbphyc_phy *usbphyc_phy = NULL;
397 struct device_node *phynode = args->np;
400 for (port = 0; port < usbphyc->nphys; port++) {
401 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
402 usbphyc_phy = usbphyc->phys[port];
407 dev_err(dev, "failed to find phy\n");
408 return ERR_PTR(-EINVAL);
411 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
412 ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
413 dev_err(dev, "invalid number of cells for phy port%d\n",
415 return ERR_PTR(-EINVAL);
418 /* Configure the UTMI switch for PHY port#2 */
419 if (usbphyc_phy->index == 1) {
420 if (usbphyc->switch_setup < 0) {
421 stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
423 if (args->args[0] != usbphyc->switch_setup) {
424 dev_err(dev, "phy port1 already used\n");
425 return ERR_PTR(-EBUSY);
430 return usbphyc_phy->phy;
433 static int stm32_usbphyc_probe(struct platform_device *pdev)
435 struct stm32_usbphyc *usbphyc;
436 struct device *dev = &pdev->dev;
437 struct device_node *child, *np = dev->of_node;
438 struct phy_provider *phy_provider;
442 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
446 dev_set_drvdata(dev, usbphyc);
448 usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
449 if (IS_ERR(usbphyc->base))
450 return PTR_ERR(usbphyc->base);
452 usbphyc->clk = devm_clk_get(dev, NULL);
453 if (IS_ERR(usbphyc->clk))
454 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
456 ret = clk_prepare_enable(usbphyc->clk);
458 dev_err(dev, "clk enable failed: %d\n", ret);
462 usbphyc->rst = devm_reset_control_get(dev, NULL);
463 if (!IS_ERR(usbphyc->rst)) {
464 reset_control_assert(usbphyc->rst);
466 reset_control_deassert(usbphyc->rst);
468 ret = PTR_ERR(usbphyc->rst);
469 if (ret == -EPROBE_DEFER)
472 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
476 * Wait for minimum width of powerdown pulse (ENABLE = Low):
477 * we have to ensure the PLL is disabled before phys initialization.
479 if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
480 pllen, !(pllen & PLLEN), 5, 50)) {
481 dev_warn(usbphyc->dev, "PLL not reset\n");
486 usbphyc->switch_setup = -EINVAL;
487 usbphyc->nphys = of_get_child_count(np);
488 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
489 sizeof(*usbphyc->phys), GFP_KERNEL);
490 if (!usbphyc->phys) {
495 usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
496 if (IS_ERR(usbphyc->vdda1v1)) {
497 ret = PTR_ERR(usbphyc->vdda1v1);
498 if (ret != -EPROBE_DEFER)
499 dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret);
503 usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
504 if (IS_ERR(usbphyc->vdda1v8)) {
505 ret = PTR_ERR(usbphyc->vdda1v8);
506 if (ret != -EPROBE_DEFER)
507 dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret);
511 for_each_child_of_node(np, child) {
512 struct stm32_usbphyc_phy *usbphyc_phy;
516 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
519 if (ret != -EPROBE_DEFER)
520 dev_err(dev, "failed to create phy%d: %d\n",
525 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
532 ret = of_property_read_u32(child, "reg", &index);
533 if (ret || index > usbphyc->nphys) {
534 dev_err(&phy->dev, "invalid reg property: %d\n", ret);
538 usbphyc->phys[port] = usbphyc_phy;
539 phy_set_bus_width(phy, 8);
540 phy_set_drvdata(phy, usbphyc_phy);
542 usbphyc->phys[port]->phy = phy;
543 usbphyc->phys[port]->usbphyc = usbphyc;
544 usbphyc->phys[port]->index = index;
545 usbphyc->phys[port]->active = false;
547 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
548 if (IS_ERR(usbphyc->phys[port]->vbus)) {
549 ret = PTR_ERR(usbphyc->phys[port]->vbus);
550 if (ret == -EPROBE_DEFER)
552 usbphyc->phys[port]->vbus = NULL;
558 phy_provider = devm_of_phy_provider_register(dev,
559 stm32_usbphyc_of_xlate);
560 if (IS_ERR(phy_provider)) {
561 ret = PTR_ERR(phy_provider);
562 dev_err(dev, "failed to register phy provider: %d\n", ret);
566 ret = stm32_usbphyc_clk48_register(usbphyc);
568 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
572 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
573 dev_info(dev, "registered rev:%lu.%lu\n",
574 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
581 clk_disable_unprepare(usbphyc->clk);
586 static int stm32_usbphyc_remove(struct platform_device *pdev)
588 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
591 /* Ensure PHYs are not active, to allow PLL disabling */
592 for (port = 0; port < usbphyc->nphys; port++)
593 if (usbphyc->phys[port]->active)
594 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
596 stm32_usbphyc_clk48_unregister(usbphyc);
598 clk_disable_unprepare(usbphyc->clk);
603 static const struct of_device_id stm32_usbphyc_of_match[] = {
604 { .compatible = "st,stm32mp1-usbphyc", },
607 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
609 static struct platform_driver stm32_usbphyc_driver = {
610 .probe = stm32_usbphyc_probe,
611 .remove = stm32_usbphyc_remove,
613 .of_match_table = stm32_usbphyc_of_match,
614 .name = "stm32-usbphyc",
617 module_platform_driver(stm32_usbphyc_driver);
619 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
620 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
621 MODULE_LICENSE("GPL v2");