drivers/phy/qualcomm/phy-qcom-qmp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef QCOM_PHY_QMP_H_
   7 #define QCOM_PHY_QMP_H_
   8
   9 #include "phy-qcom-qmp-qserdes-com.h"
  10 #include "phy-qcom-qmp-qserdes-txrx.h"
  11
  12 #include "phy-qcom-qmp-qserdes-com-v3.h"
  13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
  14
  15 #include "phy-qcom-qmp-qserdes-com-v4.h"
  16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
  17
  18 #include "phy-qcom-qmp-qserdes-com-v5.h"
  19 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
  20
  21 #include "phy-qcom-qmp-qserdes-pll.h"
  22
  23 #include "phy-qcom-qmp-pcs-v2.h"
  24
  25 #include "phy-qcom-qmp-pcs-v3.h"
  26 #include "phy-qcom-qmp-pcs-misc-v3.h"
  27
  28 #include "phy-qcom-qmp-pcs-v4.h"
  29 #include "phy-qcom-qmp-pcs-pcie-v4.h"
  30 #include "phy-qcom-qmp-pcs-usb-v4.h"
  31 #include "phy-qcom-qmp-pcs-ufs-v4.h"
  32
  33 #include "phy-qcom-qmp-pcs-v5.h"
  34 #include "phy-qcom-qmp-pcs-pcie-v5.h"
  35 #include "phy-qcom-qmp-pcs-usb-v5.h"
  36 #include "phy-qcom-qmp-pcs-ufs-v5.h"
  37
  38 /* Only for QMP V3 & V4 PHY - DP COM registers */
  39 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                    0x00
  40 #define QPHY_V3_DP_COM_SW_RESET                         0x04
  41 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL                  0x08
  42 #define QPHY_V3_DP_COM_SWI_CTRL                         0x0c
  43 #define QPHY_V3_DP_COM_TYPEC_CTRL                       0x10
  44 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL                 0x14
  45 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL                  0x1c
  46
  47 /* QSERDES V3 COM bits */
  48 # define QSERDES_V3_COM_BIAS_EN                         0x0001
  49 # define QSERDES_V3_COM_BIAS_EN_MUX                     0x0002
  50 # define QSERDES_V3_COM_CLKBUF_R_EN                     0x0004
  51 # define QSERDES_V3_COM_CLKBUF_L_EN                     0x0008
  52 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL                0x0010
  53 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L               0x0020
  54 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R               0x0040
  55
  56 /* QSERDES V3 TX bits */
  57 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK               0x001f
  58 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN             0x0020
  59 # define DP_PHY_TXn_TX_DRV_LVL_MASK                     0x001f
  60 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN                   0x0020
  61
  62 /* QMP PHY - DP PHY registers */
  63 #define QSERDES_DP_PHY_REVISION_ID0                     0x000
  64 #define QSERDES_DP_PHY_REVISION_ID1                     0x004
  65 #define QSERDES_DP_PHY_REVISION_ID2                     0x008
  66 #define QSERDES_DP_PHY_REVISION_ID3                     0x00c
  67 #define QSERDES_DP_PHY_CFG                              0x010
  68 #define QSERDES_DP_PHY_PD_CTL                           0x018
  69 # define DP_PHY_PD_CTL_PWRDN                            0x001
  70 # define DP_PHY_PD_CTL_PSR_PWRDN                        0x002
  71 # define DP_PHY_PD_CTL_AUX_PWRDN                        0x004
  72 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN                   0x008
  73 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN                   0x010
  74 # define DP_PHY_PD_CTL_PLL_PWRDN                        0x020
  75 # define DP_PHY_PD_CTL_DP_CLAMP_EN                      0x040
  76 #define QSERDES_DP_PHY_MODE                             0x01c
  77 #define QSERDES_DP_PHY_AUX_CFG0                         0x020
  78 #define QSERDES_DP_PHY_AUX_CFG1                         0x024
  79 #define QSERDES_DP_PHY_AUX_CFG2                         0x028
  80 #define QSERDES_DP_PHY_AUX_CFG3                         0x02c
  81 #define QSERDES_DP_PHY_AUX_CFG4                         0x030
  82 #define QSERDES_DP_PHY_AUX_CFG5                         0x034
  83 #define QSERDES_DP_PHY_AUX_CFG6                         0x038
  84 #define QSERDES_DP_PHY_AUX_CFG7                         0x03c
  85 #define QSERDES_DP_PHY_AUX_CFG8                         0x040
  86 #define QSERDES_DP_PHY_AUX_CFG9                         0x044
  87
  88 /* Only for QMP V3 PHY - DP PHY registers */
  89 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK            0x048
  90 # define PHY_AUX_STOP_ERR_MASK                          0x01
  91 # define PHY_AUX_DEC_ERR_MASK                           0x02
  92 # define PHY_AUX_SYNC_ERR_MASK                          0x04
  93 # define PHY_AUX_ALIGN_ERR_MASK                         0x08
  94 # define PHY_AUX_REQ_ERR_MASK                           0x10
  95
  96 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR           0x04c
  97 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG                  0x050
  98
  99 #define QSERDES_V3_DP_PHY_VCO_DIV                       0x064
 100 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL              0x06c
 101 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL              0x088
 102
 103 #define QSERDES_V3_DP_PHY_SPARE0                        0x0ac
 104 #define DP_PHY_SPARE0_MASK                              0x0f
 105 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT            0x04(0x0004)
 106
 107 #define QSERDES_V3_DP_PHY_STATUS                        0x0c0
 108
 109
 110 /* Only for QMP V4_20 PHY - TX registers */
 111 #define QSERDES_V4_20_TX_LANE_MODE_1                    0x88
 112 #define QSERDES_V4_20_TX_LANE_MODE_2                    0x8c
 113 #define QSERDES_V4_20_TX_LANE_MODE_3                    0x90
 114 #define QSERDES_V4_20_TX_VMODE_CTRL1                    0xc4
 115 #define QSERDES_V4_20_TX_PI_QEC_CTRL                    0xe0
 116
 117 /* Only for QMP V4 PHY - DP PHY registers */
 118 #define QSERDES_V4_DP_PHY_CFG_1                         0x014
 119 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK            0x054
 120 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR           0x058
 121 #define QSERDES_V4_DP_PHY_VCO_DIV                       0x070
 122 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL              0x078
 123 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL              0x09c
 124 #define QSERDES_V4_DP_PHY_SPARE0                        0x0c8
 125 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS          0x0d8
 126 #define QSERDES_V4_DP_PHY_STATUS                        0x0dc
 127
 128 /* Only for QMP V4_20 PHY - RX registers */
 129 #define QSERDES_V4_20_RX_FO_GAIN_RATE2                  0x008
 130 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS               0x058
 131 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE         0x0ac
 132 #define QSERDES_V4_20_RX_DFE_3                          0x110
 133 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1                0x134
 134 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2                0x138
 135 #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2                 0x150
 136 #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1    0x178
 137 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1            0x1c8
 138 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2            0x1cc
 139 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3            0x1d0
 140 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4            0x1d4
 141 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0               0x1d8
 142 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1               0x1dc
 143 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2               0x1e0
 144 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3               0x1e4
 145 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4               0x1e8
 146 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0               0x1ec
 147 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1               0x1f0
 148 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2               0x1f4
 149 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3               0x1f8
 150 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4               0x1fc
 151 #define QSERDES_V4_20_RX_PHPRE_CTRL                     0x200
 152 #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET       0x20c
 153 #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2              0x23c
 154
 155 /* PCIE GEN3 COM registers */
 156 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER                 0x14
 157 #define PCIE_GEN3_QHP_COM_SSC_PER1                      0x20
 158 #define PCIE_GEN3_QHP_COM_SSC_PER2                      0x24
 159 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1                0x28
 160 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2                0x2c
 161 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1          0x34
 162 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1          0x38
 163 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN            0x54
 164 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1                   0x58
 165 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0               0x6c
 166 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0               0x70
 167 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1               0x78
 168 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1               0x7c
 169 #define PCIE_GEN3_QHP_COM_BGV_TRIM                      0x98
 170 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0                 0xb4
 171 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1                 0xb8
 172 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0               0xc0
 173 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1               0xc4
 174 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0               0xcc
 175 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1               0xd0
 176 #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL                 0xdc
 177 #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2                 0xf0
 178 #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN                   0xf8
 179 #define PCIE_GEN3_QHP_COM_DEC_START_MODE0               0x100
 180 #define PCIE_GEN3_QHP_COM_DEC_START_MODE1               0x108
 181 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0         0x11c
 182 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0         0x120
 183 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0         0x124
 184 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1         0x128
 185 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1         0x12c
 186 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1         0x130
 187 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0         0x150
 188 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1         0x158
 189 #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP                  0x178
 190 #define PCIE_GEN3_QHP_COM_BG_CTRL                       0x1c8
 191 #define PCIE_GEN3_QHP_COM_CLK_SELECT                    0x1cc
 192 #define PCIE_GEN3_QHP_COM_HSCLK_SEL1                    0x1d0
 193 #define PCIE_GEN3_QHP_COM_CORECLK_DIV                   0x1e0
 194 #define PCIE_GEN3_QHP_COM_CORE_CLK_EN                   0x1e8
 195 #define PCIE_GEN3_QHP_COM_CMN_CONFIG                    0x1f0
 196 #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL              0x1fc
 197 #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1             0x21c
 198 #define PCIE_GEN3_QHP_COM_CMN_MODE                      0x224
 199 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1                  0x228
 200 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2                  0x22c
 201
 202 /* PCIE GEN3 QHP Lane registers */
 203 #define PCIE_GEN3_QHP_L0_DRVR_CTRL0                     0xc
 204 #define PCIE_GEN3_QHP_L0_DRVR_CTRL1                     0x10
 205 #define PCIE_GEN3_QHP_L0_DRVR_CTRL2                     0x14
 206 #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN                    0x18
 207 #define PCIE_GEN3_QHP_L0_TX_BAND_MODE                   0x60
 208 #define PCIE_GEN3_QHP_L0_LANE_MODE                      0x64
 209 #define PCIE_GEN3_QHP_L0_PARALLEL_RATE                  0x7c
 210 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0                 0xc0
 211 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1                 0xc4
 212 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2                 0xc8
 213 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1              0xd0
 214 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2              0xd4
 215 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0               0xd8
 216 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1               0xdc
 217 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2               0xe0
 218 #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE                0xfc
 219 #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE                 0x100
 220 #define PCIE_GEN3_QHP_L0_RXENGINE_EN0                   0x108
 221 #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME                0x114
 222 #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME            0x118
 223 #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME               0x11c
 224 #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME                0x120
 225 #define PCIE_GEN3_QHP_L0_VGA_GAIN                       0x124
 226 #define PCIE_GEN3_QHP_L0_DFE_GAIN                       0x128
 227 #define PCIE_GEN3_QHP_L0_EQ_GAIN                        0x130
 228 #define PCIE_GEN3_QHP_L0_OFFSET_GAIN                    0x134
 229 #define PCIE_GEN3_QHP_L0_PRE_GAIN                       0x138
 230 #define PCIE_GEN3_QHP_L0_VGA_INITVAL                    0x13c
 231 #define PCIE_GEN3_QHP_L0_EQ_INTVAL                      0x154
 232 #define PCIE_GEN3_QHP_L0_EDAC_INITVAL                   0x160
 233 #define PCIE_GEN3_QHP_L0_RXEQ_INITB0                    0x168
 234 #define PCIE_GEN3_QHP_L0_RXEQ_INITB1                    0x16c
 235 #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1               0x178
 236 #define PCIE_GEN3_QHP_L0_RXEQ_CTRL                      0x180
 237 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0             0x184
 238 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1             0x188
 239 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2             0x18c
 240 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0             0x190
 241 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1             0x194
 242 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2             0x198
 243 #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG                 0x19c
 244 #define PCIE_GEN3_QHP_L0_RX_BAND                        0x1a4
 245 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0            0x1c0
 246 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1            0x1c4
 247 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2            0x1c8
 248 #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES                 0x230
 249 #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL                   0x234
 250 #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL          0x238
 251 #define PCIE_GEN3_QHP_L0_DCC_GAIN                       0x2a4
 252 #define PCIE_GEN3_QHP_L0_RSM_START                      0x2a8
 253 #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL                   0x2ac
 254 #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL                  0x2b0
 255 #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0                 0x2b8
 256 #define PCIE_GEN3_QHP_L0_TS0_TIMER                      0x2c0
 257 #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE               0x2c4
 258 #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET            0x2cc
 259
 260 /* PCIE GEN3 PCS registers */
 261 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB          0x2c
 262 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB          0x40
 263 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB            0x54
 264 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB            0x68
 265 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG            0x15c
 266 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5           0x16c
 267 #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG              0x174
 268
 269 /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
 270 #define QPHY_V4_20_PCS_RX_SIGDET_LVL                    0x188
 271 #define QPHY_V4_20_PCS_EQ_CONFIG2                       0x1d8
 272 #define QPHY_V4_20_PCS_EQ_CONFIG4                       0x1e0
 273 #define QPHY_V4_20_PCS_EQ_CONFIG5                       0x1e4
 274
 275 /* Only for QMP V4 PHY - PCS_MISC registers */
 276 #define QPHY_V4_PCS_MISC_TYPEC_CTRL                     0x00
 277 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL               0x04
 278 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1               0x08
 279 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE                   0x0c
 280 #define QPHY_V4_PCS_MISC_TYPEC_STATUS                   0x10
 281 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS             0x14
 282
 283 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1                  0x0a0
 284 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME            0x0f0
 285 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME            0x0f4
 286 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2               0x0fc
 287 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5               0x108
 288 #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2             0x824
 289 #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2             0x828
 290
 291 /* Only for QMP V5_20 PHY - TX registers */
 292 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX        0x30
 293 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX        0x34
 294 #define QSERDES_V5_20_TX_LANE_MODE_1                    0x78
 295 #define QSERDES_V5_20_TX_LANE_MODE_2                    0x7c
 296
 297 /* Only for QMP V5_20 PHY - RX registers */
 298 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2             0x008
 299 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3             0x00c
 300 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS               0x020
 301 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1   0x02c
 302 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3   0x030
 303 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET               0x07c
 304 #define QSERDES_V5_20_RX_DFE_3                          0x090
 305 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1                0x0b4
 306 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1          0x0c4
 307 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2          0x0c8
 308 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL                0x0dc
 309 #define QSERDES_V5_20_RX_GM_CAL                         0x0ec
 310 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4          0x108
 311 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1            0x164
 312 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2            0x168
 313 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3            0x16c
 314 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5            0x174
 315 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6            0x178
 316 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0               0x17c
 317 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1               0x180
 318 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2               0x184
 319 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3               0x188
 320 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4               0x18c
 321 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5               0x190
 322 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6               0x194
 323 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0               0x198
 324 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1               0x19c
 325 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2               0x1a0
 326 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3               0x1a4
 327 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4               0x1a8
 328 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5               0x1ac
 329 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6               0x1b0
 330 #define QSERDES_V5_20_RX_PHPRE_CTRL                     0x1b4
 331 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET       0x1c0
 332 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
 333 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3   0x1f8
 334 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
 335 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3   0x200
 336 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
 337 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3   0x208
 338 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3   0x210
 339 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3   0x218
 340 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3   0x220
 341
 342 /* Only for QMP V5_20 PHY - PCIe PCS registers */
 343 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE       0x01c
 344 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS            0x090
 345 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1                  0x0a0
 346 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5               0x108
 347 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN                 0x15c
 348 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3        0x184
 349
 350 #endif