phy: qcom-qmp: move PCS V4 registers to separate headers

[platform/kernel/linux-starfive.git] / drivers / phy / qualcomm / phy-qcom-qmp.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_H_
#define QCOM_PHY_QMP_H_

#include "phy-qcom-qmp-qserdes-com.h"
#include "phy-qcom-qmp-qserdes-txrx.h"

#include "phy-qcom-qmp-qserdes-com-v3.h"
#include "phy-qcom-qmp-qserdes-txrx-v3.h"

#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-txrx-v4.h"

#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"

#include "phy-qcom-qmp-qserdes-pll.h"

#include "phy-qcom-qmp-pcs-v2.h"

#include "phy-qcom-qmp-pcs-v3.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"

#include "phy-qcom-qmp-pcs-v4.h"
#include "phy-qcom-qmp-pcs-pcie-v4.h"
#include "phy-qcom-qmp-pcs-usb-v4.h"
#include "phy-qcom-qmp-pcs-ufs-v4.h"

/* Only for QMP V3 & V4 PHY - DP COM registers */
#define QPHY_V3_DP_COM_PHY_MODE_CTRL                    0x00
#define QPHY_V3_DP_COM_SW_RESET                         0x04
#define QPHY_V3_DP_COM_POWER_DOWN_CTRL                  0x08
#define QPHY_V3_DP_COM_SWI_CTRL                         0x0c
#define QPHY_V3_DP_COM_TYPEC_CTRL                       0x10
#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL                 0x14
#define QPHY_V3_DP_COM_RESET_OVRD_CTRL                  0x1c

/* QSERDES V3 COM bits */
# define QSERDES_V3_COM_BIAS_EN                         0x0001
# define QSERDES_V3_COM_BIAS_EN_MUX                     0x0002
# define QSERDES_V3_COM_CLKBUF_R_EN                     0x0004
# define QSERDES_V3_COM_CLKBUF_L_EN                     0x0008
# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL                0x0010
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L               0x0020
# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R               0x0040

/* QSERDES V3 TX bits */
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK               0x001f
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN             0x0020
# define DP_PHY_TXn_TX_DRV_LVL_MASK                     0x001f
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN                   0x0020

/* QMP PHY - DP PHY registers */
#define QSERDES_DP_PHY_REVISION_ID0                     0x000
#define QSERDES_DP_PHY_REVISION_ID1                     0x004
#define QSERDES_DP_PHY_REVISION_ID2                     0x008
#define QSERDES_DP_PHY_REVISION_ID3                     0x00c
#define QSERDES_DP_PHY_CFG                              0x010
#define QSERDES_DP_PHY_PD_CTL                           0x018
# define DP_PHY_PD_CTL_PWRDN                            0x001
# define DP_PHY_PD_CTL_PSR_PWRDN                        0x002
# define DP_PHY_PD_CTL_AUX_PWRDN                        0x004
# define DP_PHY_PD_CTL_LANE_0_1_PWRDN                   0x008
# define DP_PHY_PD_CTL_LANE_2_3_PWRDN                   0x010
# define DP_PHY_PD_CTL_PLL_PWRDN                        0x020
# define DP_PHY_PD_CTL_DP_CLAMP_EN                      0x040
#define QSERDES_DP_PHY_MODE                             0x01c
#define QSERDES_DP_PHY_AUX_CFG0                         0x020
#define QSERDES_DP_PHY_AUX_CFG1                         0x024
#define QSERDES_DP_PHY_AUX_CFG2                         0x028
#define QSERDES_DP_PHY_AUX_CFG3                         0x02c
#define QSERDES_DP_PHY_AUX_CFG4                         0x030
#define QSERDES_DP_PHY_AUX_CFG5                         0x034
#define QSERDES_DP_PHY_AUX_CFG6                         0x038
#define QSERDES_DP_PHY_AUX_CFG7                         0x03c
#define QSERDES_DP_PHY_AUX_CFG8                         0x040
#define QSERDES_DP_PHY_AUX_CFG9                         0x044

/* Only for QMP V3 PHY - DP PHY registers */
#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK            0x048
# define PHY_AUX_STOP_ERR_MASK                          0x01
# define PHY_AUX_DEC_ERR_MASK                           0x02
# define PHY_AUX_SYNC_ERR_MASK                          0x04
# define PHY_AUX_ALIGN_ERR_MASK                         0x08
# define PHY_AUX_REQ_ERR_MASK                           0x10

#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR           0x04c
#define QSERDES_V3_DP_PHY_AUX_BIST_CFG                  0x050

#define QSERDES_V3_DP_PHY_VCO_DIV                       0x064
#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL              0x06c
#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL              0x088

#define QSERDES_V3_DP_PHY_SPARE0                        0x0ac
#define DP_PHY_SPARE0_MASK                              0x0f
#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT            0x04(0x0004)

#define QSERDES_V3_DP_PHY_STATUS                        0x0c0


/* Only for QMP V4_20 PHY - TX registers */
#define QSERDES_V4_20_TX_LANE_MODE_1                    0x88
#define QSERDES_V4_20_TX_LANE_MODE_2                    0x8c
#define QSERDES_V4_20_TX_LANE_MODE_3                    0x90
#define QSERDES_V4_20_TX_VMODE_CTRL1                    0xc4
#define QSERDES_V4_20_TX_PI_QEC_CTRL                    0xe0

/* Only for QMP V4 PHY - DP PHY registers */
#define QSERDES_V4_DP_PHY_CFG_1                         0x014
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK            0x054
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR           0x058
#define QSERDES_V4_DP_PHY_VCO_DIV                       0x070
#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL              0x078
#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL              0x09c
#define QSERDES_V4_DP_PHY_SPARE0                        0x0c8
#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS          0x0d8
#define QSERDES_V4_DP_PHY_STATUS                        0x0dc

/* Only for QMP V4_20 PHY - RX registers */
#define QSERDES_V4_20_RX_FO_GAIN_RATE2                  0x008
#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS               0x058
#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE         0x0ac
#define QSERDES_V4_20_RX_DFE_3                          0x110
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1                0x134
#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2                0x138
#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2                 0x150
#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1    0x178
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1            0x1c8
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2            0x1cc
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3            0x1d0
#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4            0x1d4
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0               0x1d8
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1               0x1dc
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2               0x1e0
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3               0x1e4
#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4               0x1e8
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0               0x1ec
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1               0x1f0
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2               0x1f4
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3               0x1f8
#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4               0x1fc
#define QSERDES_V4_20_RX_PHPRE_CTRL                     0x200
#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET       0x20c
#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2              0x23c

/* PCIE GEN3 COM registers */
#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER                 0x14
#define PCIE_GEN3_QHP_COM_SSC_PER1                      0x20
#define PCIE_GEN3_QHP_COM_SSC_PER2                      0x24
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1                0x28
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2                0x2c
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1          0x34
#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1          0x38
#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN            0x54
#define PCIE_GEN3_QHP_COM_CLK_ENABLE1                   0x58
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0               0x6c
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0               0x70
#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1               0x78
#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1               0x7c
#define PCIE_GEN3_QHP_COM_BGV_TRIM                      0x98
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0                 0xb4
#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1                 0xb8
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0               0xc0
#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1               0xc4
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0               0xcc
#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1               0xd0
#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL                 0xdc
#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2                 0xf0
#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN                   0xf8
#define PCIE_GEN3_QHP_COM_DEC_START_MODE0               0x100
#define PCIE_GEN3_QHP_COM_DEC_START_MODE1               0x108
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0         0x11c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0         0x120
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0         0x124
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1         0x128
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1         0x12c
#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1         0x130
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0         0x150
#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1         0x158
#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP                  0x178
#define PCIE_GEN3_QHP_COM_BG_CTRL                       0x1c8
#define PCIE_GEN3_QHP_COM_CLK_SELECT                    0x1cc
#define PCIE_GEN3_QHP_COM_HSCLK_SEL1                    0x1d0
#define PCIE_GEN3_QHP_COM_CORECLK_DIV                   0x1e0
#define PCIE_GEN3_QHP_COM_CORE_CLK_EN                   0x1e8
#define PCIE_GEN3_QHP_COM_CMN_CONFIG                    0x1f0
#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL              0x1fc
#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1             0x21c
#define PCIE_GEN3_QHP_COM_CMN_MODE                      0x224
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1                  0x228
#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2                  0x22c

/* PCIE GEN3 QHP Lane registers */
#define PCIE_GEN3_QHP_L0_DRVR_CTRL0                     0xc
#define PCIE_GEN3_QHP_L0_DRVR_CTRL1                     0x10
#define PCIE_GEN3_QHP_L0_DRVR_CTRL2                     0x14
#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN                    0x18
#define PCIE_GEN3_QHP_L0_TX_BAND_MODE                   0x60
#define PCIE_GEN3_QHP_L0_LANE_MODE                      0x64
#define PCIE_GEN3_QHP_L0_PARALLEL_RATE                  0x7c
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0                 0xc0
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1                 0xc4
#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2                 0xc8
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1              0xd0
#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2              0xd4
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0               0xd8
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1               0xdc
#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2               0xe0
#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE                0xfc
#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE                 0x100
#define PCIE_GEN3_QHP_L0_RXENGINE_EN0                   0x108
#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME                0x114
#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME            0x118
#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME               0x11c
#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME                0x120
#define PCIE_GEN3_QHP_L0_VGA_GAIN                       0x124
#define PCIE_GEN3_QHP_L0_DFE_GAIN                       0x128
#define PCIE_GEN3_QHP_L0_EQ_GAIN                        0x130
#define PCIE_GEN3_QHP_L0_OFFSET_GAIN                    0x134
#define PCIE_GEN3_QHP_L0_PRE_GAIN                       0x138
#define PCIE_GEN3_QHP_L0_VGA_INITVAL                    0x13c
#define PCIE_GEN3_QHP_L0_EQ_INTVAL                      0x154
#define PCIE_GEN3_QHP_L0_EDAC_INITVAL                   0x160
#define PCIE_GEN3_QHP_L0_RXEQ_INITB0                    0x168
#define PCIE_GEN3_QHP_L0_RXEQ_INITB1                    0x16c
#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1               0x178
#define PCIE_GEN3_QHP_L0_RXEQ_CTRL                      0x180
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0             0x184
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1             0x188
#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2             0x18c
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0             0x190
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1             0x194
#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2             0x198
#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG                 0x19c
#define PCIE_GEN3_QHP_L0_RX_BAND                        0x1a4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0            0x1c0
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1            0x1c4
#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2            0x1c8
#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES                 0x230
#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL                   0x234
#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL          0x238
#define PCIE_GEN3_QHP_L0_DCC_GAIN                       0x2a4
#define PCIE_GEN3_QHP_L0_RSM_START                      0x2a8
#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL                   0x2ac
#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL                  0x2b0
#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0                 0x2b8
#define PCIE_GEN3_QHP_L0_TS0_TIMER                      0x2c0
#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE               0x2c4
#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET            0x2cc

/* PCIE GEN3 PCS registers */
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB          0x2c
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB          0x40
#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB            0x54
#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB            0x68
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG            0x15c
#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5           0x16c
#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG              0x174

/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */
#define QPHY_V4_20_PCS_RX_SIGDET_LVL                    0x188
#define QPHY_V4_20_PCS_EQ_CONFIG2                       0x1d8
#define QPHY_V4_20_PCS_EQ_CONFIG4                       0x1e0
#define QPHY_V4_20_PCS_EQ_CONFIG5                       0x1e4

/* Only for QMP V4 PHY - PCS_MISC registers */
#define QPHY_V4_PCS_MISC_TYPEC_CTRL                     0x00
#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL               0x04
#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1               0x08
#define QPHY_V4_PCS_MISC_CLAMP_ENABLE                   0x0c
#define QPHY_V4_PCS_MISC_TYPEC_STATUS                   0x10
#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS             0x14

#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1                  0x0a0
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME            0x0f0
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME            0x0f4
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2               0x0fc
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5               0x108
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2             0x824
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2             0x828

/* Only for QMP V5_20 PHY - TX registers */
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX        0x30
#define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX        0x34
#define QSERDES_V5_20_TX_LANE_MODE_1                    0x78
#define QSERDES_V5_20_TX_LANE_MODE_2                    0x7c

/* Only for QMP V5_20 PHY - RX registers */
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2             0x008
#define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3             0x00c
#define QSERDES_V5_20_RX_UCDR_PI_CONTROLS               0x020
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1   0x02c
#define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3   0x030
#define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET               0x07c
#define QSERDES_V5_20_RX_DFE_3                          0x090
#define QSERDES_V5_20_RX_DFE_DAC_ENABLE1                0x0b4
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1          0x0c4
#define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2          0x0c8
#define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL                0x0dc
#define QSERDES_V5_20_RX_GM_CAL                         0x0ec
#define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4          0x108
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1            0x164
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2            0x168
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3            0x16c
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5            0x174
#define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6            0x178
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B0               0x17c
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B1               0x180
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B2               0x184
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B3               0x188
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B4               0x18c
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B5               0x190
#define QSERDES_V5_20_RX_RX_MODE_RATE2_B6               0x194
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B0               0x198
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B1               0x19c
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B2               0x1a0
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B3               0x1a4
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B4               0x1a8
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B5               0x1ac
#define QSERDES_V5_20_RX_RX_MODE_RATE3_B6               0x1b0
#define QSERDES_V5_20_RX_PHPRE_CTRL                     0x1b4
#define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET       0x1c0
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3   0x1f8
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3   0x200
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3   0x208
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3   0x210
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3   0x218
#define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3   0x220

/* Only for QMP V5 PHY - USB/PCIe PCS registers */
#define QPHY_V5_PCS_REFGEN_REQ_CONFIG1                  0x0dc
#define QPHY_V5_PCS_G3S2_PRE_GAIN                       0x170
#define QPHY_V5_PCS_RX_SIGDET_LVL                       0x188
#define QPHY_V5_PCS_RATE_SLEW_CNTRL1                    0x198
#define QPHY_V5_PCS_EQ_CONFIG2                          0x1e0
#define QPHY_V5_PCS_EQ_CONFIG3                          0x1e4

/* Only for QMP V5 PHY - PCS_PCIE registers */
#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE          0x20
#define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1            0x54
#define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS               0x94
#define QPHY_V5_PCS_PCIE_EQ_CONFIG2                     0xa8

/* Only for QMP V5_20 PHY - PCIe PCS registers */
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE       0x01c
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS            0x090
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1                  0x0a0
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5               0x108
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN                 0x15c
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3        0x184

/* Only for QMP V5 PHY - UFS PCS registers */
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB    0x00c
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB    0x010
#define QPHY_V5_PCS_UFS_PLL_CNTL                        0x02c
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL            0x030
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL            0x038
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY            0x074
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY            0x0b4
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL                0x124
#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME             0x150
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1                 0x154
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2                 0x158
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND                0x160
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND                 0x168
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1               0x1d8
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1                0x1e0

/* Only for QMP V5 PHY - USB3 have different offsets than V4 */
#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1            0x000
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS         0x004
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL           0x008
#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2          0x00c
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS  0x010
#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR          0x014
#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL        0x018
#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART                0x01c
#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL             0x020
#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START       0x024
#define QPHY_V5_PCS_USB3_LFPS_CONFIG1                   0x028
#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME         0x02c
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME         0x030
#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME         0x034
#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2      0x038
#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2       0x03c
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L             0x040
#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H             0x044
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD           0x048
#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY              0x04c
#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH         0x050
#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL             0x054
#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL       0x058
#define QPHY_V5_PCS_USB3_TEST_CONTROL                   0x05c
#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL          0x060

#endif