drivers/phy/qualcomm/phy-qcom-qmp-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regulator/consumer.h>
  19 #include <linux/reset.h>
  20 #include <linux/slab.h>
  21
  22 #include "phy-qcom-qmp.h"
  23 #include "phy-qcom-qmp-pcs-misc-v3.h"
  24 #include "phy-qcom-qmp-pcs-usb-v4.h"
  25 #include "phy-qcom-qmp-pcs-usb-v5.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 /* QPHY_START_CONTROL bits */
  32 #define SERDES_START                            BIT(0)
  33 #define PCS_START                               BIT(1)
  34 /* QPHY_PCS_STATUS bit */
  35 #define PHYSTATUS                               BIT(6)
  36
  37 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  38 /* DP PHY soft reset */
  39 #define SW_DPPHY_RESET                          BIT(0)
  40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  41 #define SW_DPPHY_RESET_MUX                      BIT(1)
  42 /* USB3 PHY soft reset */
  43 #define SW_USB3PHY_RESET                        BIT(2)
  44 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  46
  47 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  48 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  49 #define DP_MODE                                 BIT(1) /* enables DP mode */
  50
  51 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  52 #define ARCVR_DTCT_EN                           BIT(0)
  53 #define ALFPS_DTCT_EN                           BIT(1)
  54 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  55
  56 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  57 #define IRQ_CLEAR                               BIT(0)
  58
  59 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  60 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  61
  62 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  63
  64 struct qmp_phy_init_tbl {
  65         unsigned int offset;
  66         unsigned int val;
  67         /*
  68          * mask of lanes for which this register is written
  69          * for cases when second lane needs different values
  70          */
  71         u8 lane_mask;
  72 };
  73
  74 #define QMP_PHY_INIT_CFG(o, v)          \
  75         {                               \
  76                 .offset = o,            \
  77                 .val = v,               \
  78                 .lane_mask = 0xff,      \
  79         }
  80
  81 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  82         {                               \
  83                 .offset = o,            \
  84                 .val = v,               \
  85                 .lane_mask = l,         \
  86         }
  87
  88 /* set of registers with offsets different per-PHY */
  89 enum qphy_reg_layout {
  90         /* PCS registers */
  91         QPHY_SW_RESET,
  92         QPHY_START_CTRL,
  93         QPHY_PCS_STATUS,
  94         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  95         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
  96         QPHY_PCS_POWER_DOWN_CONTROL,
  97         /* Keep last to ensure regs_layout arrays are properly initialized */
  98         QPHY_LAYOUT_SIZE
  99 };
 100
 101 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 102         [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
 103         [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
 104         [QPHY_PCS_STATUS]               = QPHY_V2_PCS_USB_PCS_STATUS,
 105         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
 106         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
 107         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
 108 };
 109
 110 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 111         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 112         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 113         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 114         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 115         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 116         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 117 };
 118
 119 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 120         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 121         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 122         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 123         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 124
 125         /* In PCS_USB */
 126         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 127         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 128 };
 129
 130 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 131         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
 132         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
 133         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
 134         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
 135
 136         /* In PCS_USB */
 137         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 138         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 139 };
 140
 141 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
 142         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 143         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 144         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 145         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 146         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 147         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 148         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 149         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 150         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 151         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 152         /* PLL and Loop filter settings */
 153         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
 154         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
 155         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
 156         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
 157         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
 158         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 159         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 160         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
 161         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
 162         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
 163         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 164         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 165         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 166         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 167         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 168         /* SSC settings */
 169         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 170         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
 171         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 172         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 173         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 174         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
 175         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
 176 };
 177
 178 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
 179         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 180         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 181         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 182 };
 183
 184 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
 185         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 186         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 187         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
 188         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 189         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 190         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 191         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 192         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 193         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 194         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
 195 };
 196
 197 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
 198         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 199         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 200         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 201         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 202         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 203         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 204         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 205         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 206         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 207         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 208         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 209         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 210         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 211         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 212         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 213         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 214         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 215         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 216         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 217         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 218         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 219         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 220         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 221 };
 222
 223 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 224         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 225         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 226         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 227         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 228         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 229         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 230         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 231         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 232         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 233         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 234         /* PLL and Loop filter settings */
 235         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 236         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 237         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 238         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 239         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 240         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 241         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 242         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 243         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 244         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 245         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 246         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 247         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 248         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 249         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 250         /* SSC settings */
 251         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 252         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 253         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 258 };
 259
 260 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 261         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 262         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 263         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 264         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 265         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 266         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 267         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 268         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 269         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 270 };
 271
 272 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 273         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 274         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 275         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 276         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 277         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 278         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 279         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 280         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 281         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 282         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 283         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 284         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 285         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 287         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 296 };
 297
 298 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 299         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 300         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 301         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 302         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 303         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 304         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 305         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 306         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 307         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 308         /* PLL and Loop filter settings */
 309         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 310         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 311         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 312         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 313         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 325         /* SSC settings */
 326         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 333 };
 334
 335 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 336         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 337         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 338         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 339 };
 340
 341 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 342         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 343         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 344         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 345         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 346         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 347         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 348         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 349         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 350         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 351         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 352 };
 353
 354 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 355         /* FLL settings */
 356         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
 357         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
 358         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
 359         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 360         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
 361
 362         /* Lock Det settings */
 363         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 364         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 365         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
 366         QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
 367 };
 368
 369 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 370         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 371         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 372         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 373         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 374         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 375         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 376         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 377         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 378         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 379         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 380         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 381         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 382         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 383         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 384         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 385         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 386         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 387         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 388         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 389         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 390         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 391         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 392         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 393         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 394         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 395         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 396         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 397         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 398         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 399         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 400         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 401         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 402         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 403         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 404         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 405         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 406 };
 407
 408 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 409         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 410         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 411         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 412         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 413         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 414 };
 415
 416 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 417         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 418         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 419         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 420         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 421         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 422         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 423         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 424         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 425         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 426         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 427         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 428 };
 429
 430 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 431         /* FLL settings */
 432         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 433         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 434         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 435         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 436         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 437
 438         /* Lock Det settings */
 439         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 440         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 441         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 442         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 443
 444         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 445         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 446         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 447         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 448         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 449         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 450         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 451         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 452         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 453         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 454         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 455         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 456         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 457         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 458         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 459         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 460         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 461         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 462         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 463
 464         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 465         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 466         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 467         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 468         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 469         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 470         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 471         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 472         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 473         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 474         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 475
 476         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 477         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 478 };
 479
 480 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 481         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 487         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 488         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 489         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 490         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 491         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 492         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 493         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 494         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 495         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 496         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 497         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 498         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 499         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 500         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 501         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 502         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 503         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 504         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 505         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 506         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 507         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 508         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 509         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 510         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 511         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 512         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 513         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 514         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 515         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 516         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 517         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 518         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 519 };
 520
 521 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 522         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 523         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 524         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 525         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 526 };
 527
 528 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 529         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 532         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 534         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 535         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 536         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 537         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 538         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 539         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 540         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 541         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 542         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 546 };
 547
 548 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 549         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 550         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 551         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 552         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 553         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 554         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 555         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 556         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 557         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 558         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 559         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 560         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 561         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 562         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 563         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 564         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 565         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 566         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 567         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 568         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 569         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 570         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 571         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 572         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 573         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 574         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 575         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 576         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 577         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 578         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 579         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 580         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 581         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 582         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 583         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 584         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 585         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 586         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 587 };
 588
 589 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
 590         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 591         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 592         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 593         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 594         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 595         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 596         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 597         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 598         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 599         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 600         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 601         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 602         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 603         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 604         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 605         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 606         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 607         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 608         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 609         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 610         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 611         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 612         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 613         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 614         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 615         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 616         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 617         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 618         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 619         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 620         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 621         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 622         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 623         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 624         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 625         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 626         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 627         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 628         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 629         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 630 };
 631
 632 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
 633         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 634         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
 635         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 636         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
 637 };
 638
 639 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
 640         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 641         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 642         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
 643         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
 644         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
 645         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 646         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 647         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 648         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 649         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 650         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 651         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 652         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 653         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 654         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 655         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 656         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 657         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 658         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 659         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
 660         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 661         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 662         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 663         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 664         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 665         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 666         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 667         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 668         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 669         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 670         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 671         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 672         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 673         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
 674         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 675         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 676 };
 677
 678 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
 679         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 680         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 681         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 682         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 683         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 684         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 685         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 686         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
 687         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 688         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 689         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 690         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 691         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 692         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 693 };
 694
 695 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
 696         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 697         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 698 };
 699
 700 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
 701         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 702         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 703         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
 704         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 705         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 706         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 707 };
 708
 709 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
 710         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 711         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
 712         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 713         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 714         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 715         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 716         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 717         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 718         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 719         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 720         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 721         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 722         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 723         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 724         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 725         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 726         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 727         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 728         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 729         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
 730         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 731         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 732         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 733         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 734         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 735         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 736         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 737         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 738         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 739         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 740         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 741         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 742         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 743         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 744         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 745         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 746 };
 747
 748 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
 749         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 750         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 751         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 752         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 753         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 754         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 755         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 756         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 757         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 758         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 759         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 760         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 761         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 762         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 763 };
 764
 765 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
 766         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 767         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 768 };
 769
 770 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
 771         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 772         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 773         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
 774         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 775         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
 776 };
 777
 778 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
 779         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
 780         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 781         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 782         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 783         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 784         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 785         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 786         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 787         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 789         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 790         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
 791         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 792         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 798         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
 799         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 800         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 801         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 802         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 803         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 804         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 806         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 807         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 808         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 809         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 810         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 811         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 815 };
 816
 817 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
 818         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 819         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 820         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 821         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 822         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 823         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 824         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
 825 };
 826
 827 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
 828         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 829         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 830         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 831         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 832         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 833         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 834         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 835         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 836         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 837         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 838         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 839         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 840         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 841         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 842         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 843         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 844         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 845         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 846         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 847         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 848         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 849         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 850         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 851         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 852         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 853         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 854         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 855         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 856         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 857         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 858         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 859 };
 860
 861 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
 862         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
 863         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
 864         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 865         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 866         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 867         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
 868         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 869 };
 870
 871 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
 872         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
 873         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
 874         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
 875         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
 876         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
 877         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 878         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
 879         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
 880         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 881         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 882         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 883         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 884         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 885         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 886         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 887         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 888         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 889         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 890         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 891         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 892         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 893         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 894         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 895         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 896         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 897         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 898         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 899         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 900         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 901         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 902         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
 903 };
 904
 905 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
 906         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 907         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 908         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 909         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 910         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 911         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 912         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 913         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 914         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 915         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 916         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 917         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 918         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 919         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 920 };
 921
 922 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
 923         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 924         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 925 };
 926
 927 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
 928         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 929         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 930         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 931         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 932         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
 933         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
 934         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 935         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 936         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 937         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 938         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 939         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 940         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 941         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 942         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 943         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 944         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 945         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 946         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
 947         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 948         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 949         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 950         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
 951         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 952         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 953         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 954         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 955         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 956         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 957         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 958         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 959         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 960         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 961         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 962         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 963         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 964         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
 965         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
 966 };
 967
 968 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
 969         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 970         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 971         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 972         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 973         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
 974 };
 975
 976 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
 977         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 978         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 979         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 980         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 981         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 982         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 983         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 984         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 985         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 986         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 987         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 988         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 989         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
 990         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 991         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 992         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 993         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
 994 };
 995
 996 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
 997         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 998         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 999         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1000         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1001         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1002         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1003         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1004         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1005         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1006         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1007         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1008         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1009         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1010         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1011         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1012         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1013         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1014         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1015         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1016         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1017         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1018 };
1019
1020 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1021         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1022         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1023         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1024         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1025         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1026         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1027         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1028         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1029         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1030         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1031         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1032         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1033         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1034         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1035         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1036         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1037         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1038         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1039         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1040         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1041         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1042         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1043         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1044         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1045         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1046         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1047         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1048         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1049         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1050         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1051         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1052         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1053         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1054         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1055         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1056         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1057         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1058         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1059         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1060 };
1061
1062 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1063         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1064         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1068         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1069         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1070 };
1071
1072 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1073         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1074         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1075         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1076         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1083         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1084         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1085         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1086         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1090         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1091         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1092         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1093         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1094         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1095         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1096         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1097         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1098         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1099         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1100         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1101         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1102         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1103         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1104 };
1105
1106 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1107         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1108         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1109         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1110         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1111         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1112         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1113         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1114         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1115         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1116         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1117         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1118         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1119         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1120         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1121         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1122         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1123 };
1124
1125 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1126         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1127         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1128         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1129         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1130         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1131         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1132         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1133         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1134         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1135         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1136         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1137         QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1138         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1139         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1140         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1141         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1142         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1143 };
1144
1145 struct qmp_usb_offsets {
1146         u16 serdes;
1147         u16 pcs;
1148         u16 pcs_misc;
1149         u16 pcs_usb;
1150         u16 tx;
1151         u16 rx;
1152         /* for PHYs with >= 2 lanes */
1153         u16 tx2;
1154         u16 rx2;
1155 };
1156
1157 /* struct qmp_phy_cfg - per-PHY initialization config */
1158 struct qmp_phy_cfg {
1159         int lanes;
1160
1161         const struct qmp_usb_offsets *offsets;
1162
1163         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1164         const struct qmp_phy_init_tbl *serdes_tbl;
1165         int serdes_tbl_num;
1166         const struct qmp_phy_init_tbl *tx_tbl;
1167         int tx_tbl_num;
1168         const struct qmp_phy_init_tbl *rx_tbl;
1169         int rx_tbl_num;
1170         const struct qmp_phy_init_tbl *pcs_tbl;
1171         int pcs_tbl_num;
1172         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1173         int pcs_usb_tbl_num;
1174
1175         /* clock ids to be requested */
1176         const char * const *clk_list;
1177         int num_clks;
1178         /* resets to be requested */
1179         const char * const *reset_list;
1180         int num_resets;
1181         /* regulators to be requested */
1182         const char * const *vreg_list;
1183         int num_vregs;
1184
1185         /* array of registers with different offsets */
1186         const unsigned int *regs;
1187
1188         /* true, if PHY needs delay after POWER_DOWN */
1189         bool has_pwrdn_delay;
1190
1191         /* Offset from PCS to PCS_USB region */
1192         unsigned int pcs_usb_offset;
1193 };
1194
1195 struct qmp_usb {
1196         struct device *dev;
1197
1198         const struct qmp_phy_cfg *cfg;
1199
1200         void __iomem *serdes;
1201         void __iomem *pcs;
1202         void __iomem *pcs_misc;
1203         void __iomem *pcs_usb;
1204         void __iomem *tx;
1205         void __iomem *rx;
1206         void __iomem *tx2;
1207         void __iomem *rx2;
1208
1209         struct clk *pipe_clk;
1210         struct clk_bulk_data *clks;
1211         struct reset_control_bulk_data *resets;
1212         struct regulator_bulk_data *vregs;
1213
1214         enum phy_mode mode;
1215
1216         struct phy *phy;
1217
1218         struct clk_fixed_rate pipe_clk_fixed;
1219 };
1220
1221 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1222 {
1223         u32 reg;
1224
1225         reg = readl(base + offset);
1226         reg |= val;
1227         writel(reg, base + offset);
1228
1229         /* ensure that above write is through */
1230         readl(base + offset);
1231 }
1232
1233 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1234 {
1235         u32 reg;
1236
1237         reg = readl(base + offset);
1238         reg &= ~val;
1239         writel(reg, base + offset);
1240
1241         /* ensure that above write is through */
1242         readl(base + offset);
1243 }
1244
1245 /* list of clocks required by phy */
1246 static const char * const msm8996_phy_clk_l[] = {
1247         "aux", "cfg_ahb", "ref",
1248 };
1249
1250 static const char * const qmp_v3_phy_clk_l[] = {
1251         "aux", "cfg_ahb", "ref", "com_aux",
1252 };
1253
1254 static const char * const qmp_v4_phy_clk_l[] = {
1255         "aux", "ref", "com_aux",
1256 };
1257
1258 static const char * const qmp_v4_ref_phy_clk_l[] = {
1259         "aux", "ref_clk_src", "ref", "com_aux",
1260 };
1261
1262 /* usb3 phy on sdx55 doesn't have com_aux clock */
1263 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1264         "aux", "cfg_ahb", "ref"
1265 };
1266
1267 static const char * const qcm2290_usb3phy_clk_l[] = {
1268         "cfg_ahb", "ref", "com_aux",
1269 };
1270
1271 /* list of resets */
1272 static const char * const msm8996_usb3phy_reset_l[] = {
1273         "phy", "common",
1274 };
1275
1276 static const char * const qcm2290_usb3phy_reset_l[] = {
1277         "phy_phy", "phy",
1278 };
1279
1280 /* list of regulators */
1281 static const char * const qmp_phy_vreg_l[] = {
1282         "vdda-phy", "vdda-pll",
1283 };
1284
1285 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1286         .serdes         = 0,
1287         .pcs            = 0x800,
1288         .pcs_usb        = 0x800,
1289         .tx             = 0x200,
1290         .rx             = 0x400,
1291 };
1292
1293 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1294         .serdes         = 0,
1295         .pcs            = 0xc00,
1296         .pcs_misc       = 0xa00,
1297         .tx             = 0x200,
1298         .rx             = 0x400,
1299         .tx2            = 0x600,
1300         .rx2            = 0x800,
1301 };
1302
1303 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1304         .serdes         = 0,
1305         .pcs            = 0x0200,
1306         .pcs_usb        = 0x1200,
1307         .tx             = 0x0e00,
1308         .rx             = 0x1000,
1309 };
1310
1311 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1312         .lanes                  = 1,
1313
1314         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
1315         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1316         .tx_tbl                 = msm8996_usb3_tx_tbl,
1317         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1318         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1319         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1320         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1321         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1322         .clk_list               = msm8996_phy_clk_l,
1323         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1324         .reset_list             = msm8996_usb3phy_reset_l,
1325         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1326         .vreg_list              = qmp_phy_vreg_l,
1327         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1328         .regs                   = qmp_v3_usb3phy_regs_layout,
1329 };
1330
1331 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1332         .lanes                  = 1,
1333
1334         .offsets                = &qmp_usb_offsets_ipq9574,
1335
1336         .serdes_tbl             = ipq9574_usb3_serdes_tbl,
1337         .serdes_tbl_num         = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1338         .tx_tbl                 = ipq9574_usb3_tx_tbl,
1339         .tx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1340         .rx_tbl                 = ipq9574_usb3_rx_tbl,
1341         .rx_tbl_num             = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1342         .pcs_tbl                = ipq9574_usb3_pcs_tbl,
1343         .pcs_tbl_num            = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1344         .clk_list               = msm8996_phy_clk_l,
1345         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1346         .reset_list             = qcm2290_usb3phy_reset_l,
1347         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1348         .vreg_list              = qmp_phy_vreg_l,
1349         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1350         .regs                   = qmp_v3_usb3phy_regs_layout,
1351 };
1352
1353 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1354         .lanes                  = 1,
1355
1356         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1357         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1358         .tx_tbl                 = msm8996_usb3_tx_tbl,
1359         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1360         .rx_tbl                 = msm8996_usb3_rx_tbl,
1361         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1362         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1363         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1364         .clk_list               = msm8996_phy_clk_l,
1365         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1366         .reset_list             = msm8996_usb3phy_reset_l,
1367         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1368         .vreg_list              = qmp_phy_vreg_l,
1369         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1370         .regs                   = qmp_v2_usb3phy_regs_layout,
1371 };
1372
1373 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1374         .lanes                  = 1,
1375
1376         .offsets                = &qmp_usb_offsets_v5,
1377
1378         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1379         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1380         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1381         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1382         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1383         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1384         .pcs_tbl                = sa8775p_usb3_uniphy_pcs_tbl,
1385         .pcs_tbl_num            = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1386         .clk_list               = qmp_v4_phy_clk_l,
1387         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1388         .reset_list             = qcm2290_usb3phy_reset_l,
1389         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1390         .vreg_list              = qmp_phy_vreg_l,
1391         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1392         .regs                   = qmp_v5_usb3phy_regs_layout,
1393 };
1394
1395 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1396         .lanes                  = 1,
1397
1398         .offsets                = &qmp_usb_offsets_v5,
1399
1400         .serdes_tbl             = sc8280xp_usb3_uniphy_serdes_tbl,
1401         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1402         .tx_tbl                 = sc8280xp_usb3_uniphy_tx_tbl,
1403         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1404         .rx_tbl                 = sc8280xp_usb3_uniphy_rx_tbl,
1405         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1406         .pcs_tbl                = sc8280xp_usb3_uniphy_pcs_tbl,
1407         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1408         .clk_list               = qmp_v4_phy_clk_l,
1409         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1410         .reset_list             = qcm2290_usb3phy_reset_l,
1411         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1412         .vreg_list              = qmp_phy_vreg_l,
1413         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1414         .regs                   = qmp_v5_usb3phy_regs_layout,
1415 };
1416
1417 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1418         .lanes                  = 1,
1419
1420         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1421         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1422         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1423         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1424         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1425         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1426         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1427         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1428         .clk_list               = qmp_v3_phy_clk_l,
1429         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1430         .reset_list             = msm8996_usb3phy_reset_l,
1431         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1432         .vreg_list              = qmp_phy_vreg_l,
1433         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1434         .regs                   = qmp_v3_usb3phy_regs_layout,
1435
1436         .has_pwrdn_delay        = true,
1437 };
1438
1439 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1440         .lanes                  = 2,
1441
1442         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1443         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1444         .tx_tbl                 = msm8998_usb3_tx_tbl,
1445         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1446         .rx_tbl                 = msm8998_usb3_rx_tbl,
1447         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1448         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1449         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1450         .clk_list               = msm8996_phy_clk_l,
1451         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1452         .reset_list             = msm8996_usb3phy_reset_l,
1453         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1454         .vreg_list              = qmp_phy_vreg_l,
1455         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1456         .regs                   = qmp_v3_usb3phy_regs_layout,
1457 };
1458
1459 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1460         .lanes                  = 1,
1461
1462         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1463         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1464         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
1465         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1466         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
1467         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1468         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
1469         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1470         .pcs_usb_tbl            = sm8150_usb3_uniphy_pcs_usb_tbl,
1471         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1472         .clk_list               = qmp_v4_ref_phy_clk_l,
1473         .num_clks               = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1474         .reset_list             = msm8996_usb3phy_reset_l,
1475         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1476         .vreg_list              = qmp_phy_vreg_l,
1477         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1478         .regs                   = qmp_v4_usb3phy_regs_layout,
1479         .pcs_usb_offset         = 0x600,
1480
1481         .has_pwrdn_delay        = true,
1482 };
1483
1484 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1485         .lanes                  = 1,
1486
1487         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1488         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1489         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
1490         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1491         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
1492         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1493         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1494         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1495         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1496         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1497         .clk_list               = qmp_v4_ref_phy_clk_l,
1498         .num_clks               = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1499         .reset_list             = msm8996_usb3phy_reset_l,
1500         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1501         .vreg_list              = qmp_phy_vreg_l,
1502         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1503         .regs                   = qmp_v4_usb3phy_regs_layout,
1504         .pcs_usb_offset         = 0x600,
1505
1506         .has_pwrdn_delay        = true,
1507 };
1508
1509 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1510         .lanes                  = 1,
1511
1512         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1513         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1514         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
1515         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1516         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
1517         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1518         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1519         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1520         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1521         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1522         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
1523         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1524         .reset_list             = msm8996_usb3phy_reset_l,
1525         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1526         .vreg_list              = qmp_phy_vreg_l,
1527         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1528         .regs                   = qmp_v4_usb3phy_regs_layout,
1529         .pcs_usb_offset         = 0x600,
1530
1531         .has_pwrdn_delay        = true,
1532 };
1533
1534 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1535         .lanes                  = 1,
1536
1537         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1538         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1539         .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
1540         .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1541         .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
1542         .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1543         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1544         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1545         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1546         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1547         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
1548         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1549         .reset_list             = msm8996_usb3phy_reset_l,
1550         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1551         .vreg_list              = qmp_phy_vreg_l,
1552         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1553         .regs                   = qmp_v5_usb3phy_regs_layout,
1554         .pcs_usb_offset         = 0x1000,
1555
1556         .has_pwrdn_delay        = true,
1557 };
1558
1559 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1560         .lanes                  = 1,
1561
1562         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1563         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1564         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
1565         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1566         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
1567         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1568         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1569         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1570         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1571         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1572         .clk_list               = qmp_v4_ref_phy_clk_l,
1573         .num_clks               = ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1574         .reset_list             = msm8996_usb3phy_reset_l,
1575         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1576         .vreg_list              = qmp_phy_vreg_l,
1577         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1578         .regs                   = qmp_v5_usb3phy_regs_layout,
1579         .pcs_usb_offset         = 0x1000,
1580
1581         .has_pwrdn_delay        = true,
1582 };
1583
1584 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1585         .lanes                  = 2,
1586
1587         .offsets                = &qmp_usb_offsets_v3,
1588
1589         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
1590         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1591         .tx_tbl                 = qcm2290_usb3_tx_tbl,
1592         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1593         .rx_tbl                 = qcm2290_usb3_rx_tbl,
1594         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1595         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
1596         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1597         .clk_list               = qcm2290_usb3phy_clk_l,
1598         .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
1599         .reset_list             = qcm2290_usb3phy_reset_l,
1600         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1601         .vreg_list              = qmp_phy_vreg_l,
1602         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1603         .regs                   = qmp_v3_usb3phy_regs_layout,
1604 };
1605
1606 static void qmp_usb_configure_lane(void __iomem *base,
1607                                         const struct qmp_phy_init_tbl tbl[],
1608                                         int num,
1609                                         u8 lane_mask)
1610 {
1611         int i;
1612         const struct qmp_phy_init_tbl *t = tbl;
1613
1614         if (!t)
1615                 return;
1616
1617         for (i = 0; i < num; i++, t++) {
1618                 if (!(t->lane_mask & lane_mask))
1619                         continue;
1620
1621                 writel(t->val, base + t->offset);
1622         }
1623 }
1624
1625 static void qmp_usb_configure(void __iomem *base,
1626                                    const struct qmp_phy_init_tbl tbl[],
1627                                    int num)
1628 {
1629         qmp_usb_configure_lane(base, tbl, num, 0xff);
1630 }
1631
1632 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1633 {
1634         const struct qmp_phy_cfg *cfg = qmp->cfg;
1635         void __iomem *serdes = qmp->serdes;
1636         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1637         int serdes_tbl_num = cfg->serdes_tbl_num;
1638
1639         qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1640
1641         return 0;
1642 }
1643
1644 static int qmp_usb_init(struct phy *phy)
1645 {
1646         struct qmp_usb *qmp = phy_get_drvdata(phy);
1647         const struct qmp_phy_cfg *cfg = qmp->cfg;
1648         void __iomem *pcs = qmp->pcs;
1649         int ret;
1650
1651         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1652         if (ret) {
1653                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1654                 return ret;
1655         }
1656
1657         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1658         if (ret) {
1659                 dev_err(qmp->dev, "reset assert failed\n");
1660                 goto err_disable_regulators;
1661         }
1662
1663         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
1664         if (ret) {
1665                 dev_err(qmp->dev, "reset deassert failed\n");
1666                 goto err_disable_regulators;
1667         }
1668
1669         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1670         if (ret)
1671                 goto err_assert_reset;
1672
1673         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1674
1675         return 0;
1676
1677 err_assert_reset:
1678         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1679 err_disable_regulators:
1680         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1681
1682         return ret;
1683 }
1684
1685 static int qmp_usb_exit(struct phy *phy)
1686 {
1687         struct qmp_usb *qmp = phy_get_drvdata(phy);
1688         const struct qmp_phy_cfg *cfg = qmp->cfg;
1689
1690         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1691
1692         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1693
1694         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1695
1696         return 0;
1697 }
1698
1699 static int qmp_usb_power_on(struct phy *phy)
1700 {
1701         struct qmp_usb *qmp = phy_get_drvdata(phy);
1702         const struct qmp_phy_cfg *cfg = qmp->cfg;
1703         void __iomem *tx = qmp->tx;
1704         void __iomem *rx = qmp->rx;
1705         void __iomem *pcs = qmp->pcs;
1706         void __iomem *status;
1707         unsigned int val;
1708         int ret;
1709
1710         qmp_usb_serdes_init(qmp);
1711
1712         ret = clk_prepare_enable(qmp->pipe_clk);
1713         if (ret) {
1714                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1715                 return ret;
1716         }
1717
1718         /* Tx, Rx, and PCS configurations */
1719         qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1720         qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1721
1722         if (cfg->lanes >= 2) {
1723                 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1724                 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1725         }
1726
1727         qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1728
1729         if (cfg->has_pwrdn_delay)
1730                 usleep_range(10, 20);
1731
1732         /* Pull PHY out of reset state */
1733         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1734
1735         /* start SerDes and Phy-Coding-Sublayer */
1736         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1737
1738         status = pcs + cfg->regs[QPHY_PCS_STATUS];
1739         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1740                                  PHY_INIT_COMPLETE_TIMEOUT);
1741         if (ret) {
1742                 dev_err(qmp->dev, "phy initialization timed-out\n");
1743                 goto err_disable_pipe_clk;
1744         }
1745
1746         return 0;
1747
1748 err_disable_pipe_clk:
1749         clk_disable_unprepare(qmp->pipe_clk);
1750
1751         return ret;
1752 }
1753
1754 static int qmp_usb_power_off(struct phy *phy)
1755 {
1756         struct qmp_usb *qmp = phy_get_drvdata(phy);
1757         const struct qmp_phy_cfg *cfg = qmp->cfg;
1758
1759         clk_disable_unprepare(qmp->pipe_clk);
1760
1761         /* PHY reset */
1762         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1763
1764         /* stop SerDes and Phy-Coding-Sublayer */
1765         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1766                         SERDES_START | PCS_START);
1767
1768         /* Put PHY into POWER DOWN state: active low */
1769         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1770                         SW_PWRDN);
1771
1772         return 0;
1773 }
1774
1775 static int qmp_usb_enable(struct phy *phy)
1776 {
1777         int ret;
1778
1779         ret = qmp_usb_init(phy);
1780         if (ret)
1781                 return ret;
1782
1783         ret = qmp_usb_power_on(phy);
1784         if (ret)
1785                 qmp_usb_exit(phy);
1786
1787         return ret;
1788 }
1789
1790 static int qmp_usb_disable(struct phy *phy)
1791 {
1792         int ret;
1793
1794         ret = qmp_usb_power_off(phy);
1795         if (ret)
1796                 return ret;
1797         return qmp_usb_exit(phy);
1798 }
1799
1800 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1801 {
1802         struct qmp_usb *qmp = phy_get_drvdata(phy);
1803
1804         qmp->mode = mode;
1805
1806         return 0;
1807 }
1808
1809 static const struct phy_ops qmp_usb_phy_ops = {
1810         .init           = qmp_usb_enable,
1811         .exit           = qmp_usb_disable,
1812         .set_mode       = qmp_usb_set_mode,
1813         .owner          = THIS_MODULE,
1814 };
1815
1816 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1817 {
1818         const struct qmp_phy_cfg *cfg = qmp->cfg;
1819         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1820         void __iomem *pcs_misc = qmp->pcs_misc;
1821         u32 intr_mask;
1822
1823         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1824             qmp->mode == PHY_MODE_USB_DEVICE_SS)
1825                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1826         else
1827                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1828
1829         /* Clear any pending interrupts status */
1830         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1831         /* Writing 1 followed by 0 clears the interrupt */
1832         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1833
1834         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1835                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1836
1837         /* Enable required PHY autonomous mode interrupts */
1838         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1839
1840         /* Enable i/o clamp_n for autonomous mode */
1841         if (pcs_misc)
1842                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1843 }
1844
1845 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1846 {
1847         const struct qmp_phy_cfg *cfg = qmp->cfg;
1848         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1849         void __iomem *pcs_misc = qmp->pcs_misc;
1850
1851         /* Disable i/o clamp_n on resume for normal mode */
1852         if (pcs_misc)
1853                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1854
1855         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1856                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1857
1858         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1859         /* Writing 1 followed by 0 clears the interrupt */
1860         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1861 }
1862
1863 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1864 {
1865         struct qmp_usb *qmp = dev_get_drvdata(dev);
1866         const struct qmp_phy_cfg *cfg = qmp->cfg;
1867
1868         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1869
1870         if (!qmp->phy->init_count) {
1871                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1872                 return 0;
1873         }
1874
1875         qmp_usb_enable_autonomous_mode(qmp);
1876
1877         clk_disable_unprepare(qmp->pipe_clk);
1878         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1879
1880         return 0;
1881 }
1882
1883 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1884 {
1885         struct qmp_usb *qmp = dev_get_drvdata(dev);
1886         const struct qmp_phy_cfg *cfg = qmp->cfg;
1887         int ret = 0;
1888
1889         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1890
1891         if (!qmp->phy->init_count) {
1892                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1893                 return 0;
1894         }
1895
1896         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1897         if (ret)
1898                 return ret;
1899
1900         ret = clk_prepare_enable(qmp->pipe_clk);
1901         if (ret) {
1902                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1903                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1904                 return ret;
1905         }
1906
1907         qmp_usb_disable_autonomous_mode(qmp);
1908
1909         return 0;
1910 }
1911
1912 static const struct dev_pm_ops qmp_usb_pm_ops = {
1913         SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1914                            qmp_usb_runtime_resume, NULL)
1915 };
1916
1917 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
1918 {
1919         const struct qmp_phy_cfg *cfg = qmp->cfg;
1920         struct device *dev = qmp->dev;
1921         int num = cfg->num_vregs;
1922         int i;
1923
1924         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1925         if (!qmp->vregs)
1926                 return -ENOMEM;
1927
1928         for (i = 0; i < num; i++)
1929                 qmp->vregs[i].supply = cfg->vreg_list[i];
1930
1931         return devm_regulator_bulk_get(dev, num, qmp->vregs);
1932 }
1933
1934 static int qmp_usb_reset_init(struct qmp_usb *qmp)
1935 {
1936         const struct qmp_phy_cfg *cfg = qmp->cfg;
1937         struct device *dev = qmp->dev;
1938         int i;
1939         int ret;
1940
1941         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
1942                                    sizeof(*qmp->resets), GFP_KERNEL);
1943         if (!qmp->resets)
1944                 return -ENOMEM;
1945
1946         for (i = 0; i < cfg->num_resets; i++)
1947                 qmp->resets[i].id = cfg->reset_list[i];
1948
1949         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
1950         if (ret)
1951                 return dev_err_probe(dev, ret, "failed to get resets\n");
1952
1953         return 0;
1954 }
1955
1956 static int qmp_usb_clk_init(struct qmp_usb *qmp)
1957 {
1958         const struct qmp_phy_cfg *cfg = qmp->cfg;
1959         struct device *dev = qmp->dev;
1960         int num = cfg->num_clks;
1961         int i;
1962
1963         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1964         if (!qmp->clks)
1965                 return -ENOMEM;
1966
1967         for (i = 0; i < num; i++)
1968                 qmp->clks[i].id = cfg->clk_list[i];
1969
1970         return devm_clk_bulk_get(dev, num, qmp->clks);
1971 }
1972
1973 static void phy_clk_release_provider(void *res)
1974 {
1975         of_clk_del_provider(res);
1976 }
1977
1978 /*
1979  * Register a fixed rate pipe clock.
1980  *
1981  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1982  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1983  * by the PHY driver for its operations.
1984  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1985  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
1986  * Below picture shows this relationship.
1987  *
1988  *         +---------------+
1989  *         |   PHY block   |<<---------------------------------------+
1990  *         |               |                                         |
1991  *         |   +-------+   |                   +-----+               |
1992  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
1993  *    clk  |   +-------+   |                   +-----+
1994  *         +---------------+
1995  */
1996 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
1997 {
1998         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
1999         struct clk_init_data init = { };
2000         int ret;
2001
2002         ret = of_property_read_string(np, "clock-output-names", &init.name);
2003         if (ret) {
2004                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2005                 return ret;
2006         }
2007
2008         init.ops = &clk_fixed_rate_ops;
2009
2010         /* controllers using QMP phys use 125MHz pipe clock interface */
2011         fixed->fixed_rate = 125000000;
2012         fixed->hw.init = &init;
2013
2014         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2015         if (ret)
2016                 return ret;
2017
2018         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2019         if (ret)
2020                 return ret;
2021
2022         /*
2023          * Roll a devm action because the clock provider is the child node, but
2024          * the child node is not actually a device.
2025          */
2026         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2027 }
2028
2029 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2030                                         int index, bool exclusive)
2031 {
2032         struct resource res;
2033
2034         if (!exclusive) {
2035                 if (of_address_to_resource(np, index, &res))
2036                         return IOMEM_ERR_PTR(-EINVAL);
2037
2038                 return devm_ioremap(dev, res.start, resource_size(&res));
2039         }
2040
2041         return devm_of_iomap(dev, np, index, NULL);
2042 }
2043
2044 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2045 {
2046         struct platform_device *pdev = to_platform_device(qmp->dev);
2047         const struct qmp_phy_cfg *cfg = qmp->cfg;
2048         struct device *dev = qmp->dev;
2049         bool exclusive = true;
2050
2051         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2052         if (IS_ERR(qmp->serdes))
2053                 return PTR_ERR(qmp->serdes);
2054
2055         /*
2056          * FIXME: These bindings should be fixed to not rely on overlapping
2057          *        mappings for PCS.
2058          */
2059         if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2060                 exclusive = false;
2061         if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2062                 exclusive = false;
2063
2064         /*
2065          * Get memory resources for the PHY:
2066          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2067          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2068          * For single lane PHYs: pcs_misc (optional) -> 3.
2069          */
2070         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2071         if (IS_ERR(qmp->tx))
2072                 return PTR_ERR(qmp->tx);
2073
2074         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2075         if (IS_ERR(qmp->rx))
2076                 return PTR_ERR(qmp->rx);
2077
2078         qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2079         if (IS_ERR(qmp->pcs))
2080                 return PTR_ERR(qmp->pcs);
2081
2082         if (cfg->pcs_usb_offset)
2083                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2084
2085         if (cfg->lanes >= 2) {
2086                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2087                 if (IS_ERR(qmp->tx2))
2088                         return PTR_ERR(qmp->tx2);
2089
2090                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2091                 if (IS_ERR(qmp->rx2))
2092                         return PTR_ERR(qmp->rx2);
2093
2094                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2095         } else {
2096                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2097         }
2098
2099         if (IS_ERR(qmp->pcs_misc)) {
2100                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2101                 qmp->pcs_misc = NULL;
2102         }
2103
2104         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2105         if (IS_ERR(qmp->pipe_clk)) {
2106                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2107                                      "failed to get pipe clock\n");
2108         }
2109
2110         return 0;
2111 }
2112
2113 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2114 {
2115         struct platform_device *pdev = to_platform_device(qmp->dev);
2116         const struct qmp_phy_cfg *cfg = qmp->cfg;
2117         const struct qmp_usb_offsets *offs = cfg->offsets;
2118         struct device *dev = qmp->dev;
2119         void __iomem *base;
2120
2121         if (!offs)
2122                 return -EINVAL;
2123
2124         base = devm_platform_ioremap_resource(pdev, 0);
2125         if (IS_ERR(base))
2126                 return PTR_ERR(base);
2127
2128         qmp->serdes = base + offs->serdes;
2129         qmp->pcs = base + offs->pcs;
2130         qmp->pcs_misc = base + offs->pcs_misc;
2131         qmp->pcs_usb = base + offs->pcs_usb;
2132         qmp->tx = base + offs->tx;
2133         qmp->rx = base + offs->rx;
2134
2135         if (cfg->lanes >= 2) {
2136                 qmp->tx2 = base + offs->tx2;
2137                 qmp->rx2 = base + offs->rx2;
2138         }
2139
2140         qmp->pipe_clk = devm_clk_get(dev, "pipe");
2141         if (IS_ERR(qmp->pipe_clk)) {
2142                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2143                                      "failed to get pipe clock\n");
2144         }
2145
2146         return 0;
2147 }
2148
2149 static int qmp_usb_probe(struct platform_device *pdev)
2150 {
2151         struct device *dev = &pdev->dev;
2152         struct phy_provider *phy_provider;
2153         struct device_node *np;
2154         struct qmp_usb *qmp;
2155         int ret;
2156
2157         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2158         if (!qmp)
2159                 return -ENOMEM;
2160
2161         qmp->dev = dev;
2162
2163         qmp->cfg = of_device_get_match_data(dev);
2164         if (!qmp->cfg)
2165                 return -EINVAL;
2166
2167         ret = qmp_usb_clk_init(qmp);
2168         if (ret)
2169                 return ret;
2170
2171         ret = qmp_usb_reset_init(qmp);
2172         if (ret)
2173                 return ret;
2174
2175         ret = qmp_usb_vreg_init(qmp);
2176         if (ret)
2177                 return ret;
2178
2179         /* Check for legacy binding with child node. */
2180         np = of_get_next_available_child(dev->of_node, NULL);
2181         if (np) {
2182                 ret = qmp_usb_parse_dt_legacy(qmp, np);
2183         } else {
2184                 np = of_node_get(dev->of_node);
2185                 ret = qmp_usb_parse_dt(qmp);
2186         }
2187         if (ret)
2188                 goto err_node_put;
2189
2190         pm_runtime_set_active(dev);
2191         ret = devm_pm_runtime_enable(dev);
2192         if (ret)
2193                 goto err_node_put;
2194         /*
2195          * Prevent runtime pm from being ON by default. Users can enable
2196          * it using power/control in sysfs.
2197          */
2198         pm_runtime_forbid(dev);
2199
2200         ret = phy_pipe_clk_register(qmp, np);
2201         if (ret)
2202                 goto err_node_put;
2203
2204         qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2205         if (IS_ERR(qmp->phy)) {
2206                 ret = PTR_ERR(qmp->phy);
2207                 dev_err(dev, "failed to create PHY: %d\n", ret);
2208                 goto err_node_put;
2209         }
2210
2211         phy_set_drvdata(qmp->phy, qmp);
2212
2213         of_node_put(np);
2214
2215         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2216
2217         return PTR_ERR_OR_ZERO(phy_provider);
2218
2219 err_node_put:
2220         of_node_put(np);
2221         return ret;
2222 }
2223
2224 static const struct of_device_id qmp_usb_of_match_table[] = {
2225         {
2226                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2227                 .data = &ipq8074_usb3phy_cfg,
2228         }, {
2229                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2230                 .data = &ipq8074_usb3phy_cfg,
2231         }, {
2232                 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2233                 .data = &ipq9574_usb3phy_cfg,
2234         }, {
2235                 .compatible = "qcom,msm8996-qmp-usb3-phy",
2236                 .data = &msm8996_usb3phy_cfg,
2237         }, {
2238                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2239                 .data = &msm8998_usb3phy_cfg,
2240         }, {
2241                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2242                 .data = &qcm2290_usb3phy_cfg,
2243         }, {
2244                 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2245                 .data = &sa8775p_usb3_uniphy_cfg,
2246         }, {
2247                 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2248                 .data = &sc8280xp_usb3_uniphy_cfg,
2249         }, {
2250                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2251                 .data = &qmp_v3_usb3_uniphy_cfg,
2252         }, {
2253                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2254                 .data = &sdx55_usb3_uniphy_cfg,
2255         }, {
2256                 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2257                 .data = &sdx65_usb3_uniphy_cfg,
2258         }, {
2259                 .compatible = "qcom,sm6115-qmp-usb3-phy",
2260                 .data = &qcm2290_usb3phy_cfg,
2261         }, {
2262                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2263                 .data = &sm8150_usb3_uniphy_cfg,
2264         }, {
2265                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2266                 .data = &sm8250_usb3_uniphy_cfg,
2267         }, {
2268                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2269                 .data = &sm8350_usb3_uniphy_cfg,
2270         },
2271         { },
2272 };
2273 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2274
2275 static struct platform_driver qmp_usb_driver = {
2276         .probe          = qmp_usb_probe,
2277         .driver = {
2278                 .name   = "qcom-qmp-usb-phy",
2279                 .pm     = &qmp_usb_pm_ops,
2280                 .of_match_table = qmp_usb_of_match_table,
2281         },
2282 };
2283
2284 module_platform_driver(qmp_usb_driver);
2285
2286 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2287 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2288 MODULE_LICENSE("GPL v2");