drivers/phy/qualcomm/phy-qcom-qmp-pcie.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/module.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_address.h>
  18 #include <linux/phy/pcie.h>
  19 #include <linux/phy/phy.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/reset.h>
  24 #include <linux/slab.h>
  25
  26 #include "phy-qcom-qmp.h"
  27 #include "phy-qcom-qmp-pcs-misc-v3.h"
  28 #include "phy-qcom-qmp-pcs-pcie-v4.h"
  29 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
  30 #include "phy-qcom-qmp-pcs-pcie-v5.h"
  31 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
  32 #include "phy-qcom-qmp-pcs-pcie-v6.h"
  33 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
  34 #include "phy-qcom-qmp-pcie-qhp.h"
  35
  36 /* QPHY_SW_RESET bit */
  37 #define SW_RESET                                BIT(0)
  38 /* QPHY_POWER_DOWN_CONTROL */
  39 #define SW_PWRDN                                BIT(0)
  40 #define REFCLK_DRV_DSBL                         BIT(1)
  41 /* QPHY_START_CONTROL bits */
  42 #define SERDES_START                            BIT(0)
  43 #define PCS_START                               BIT(1)
  44 /* QPHY_PCS_STATUS bit */
  45 #define PHYSTATUS                               BIT(6)
  46 #define PHYSTATUS_4_20                          BIT(7)
  47
  48 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  49
  50 struct qmp_phy_init_tbl {
  51         unsigned int offset;
  52         unsigned int val;
  53         /*
  54          * mask of lanes for which this register is written
  55          * for cases when second lane needs different values
  56          */
  57         u8 lane_mask;
  58 };
  59
  60 #define QMP_PHY_INIT_CFG(o, v)          \
  61         {                               \
  62                 .offset = o,            \
  63                 .val = v,               \
  64                 .lane_mask = 0xff,      \
  65         }
  66
  67 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  68         {                               \
  69                 .offset = o,            \
  70                 .val = v,               \
  71                 .lane_mask = l,         \
  72         }
  73
  74 /* set of registers with offsets different per-PHY */
  75 enum qphy_reg_layout {
  76         /* PCS registers */
  77         QPHY_SW_RESET,
  78         QPHY_START_CTRL,
  79         QPHY_PCS_STATUS,
  80         QPHY_PCS_POWER_DOWN_CONTROL,
  81         /* Keep last to ensure regs_layout arrays are properly initialized */
  82         QPHY_LAYOUT_SIZE
  83 };
  84
  85 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
  86         [QPHY_SW_RESET]                 = QPHY_V2_PCS_SW_RESET,
  87         [QPHY_START_CTRL]               = QPHY_V2_PCS_START_CONTROL,
  88         [QPHY_PCS_STATUS]               = QPHY_V2_PCS_PCI_PCS_STATUS,
  89         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V2_PCS_POWER_DOWN_CONTROL,
  90 };
  91
  92 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
  93         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
  94         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
  95         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
  96         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
  97 };
  98
  99 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
 100         [QPHY_SW_RESET]                 = 0x00,
 101         [QPHY_START_CTRL]               = 0x08,
 102         [QPHY_PCS_STATUS]               = 0x2ac,
 103         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
 104 };
 105
 106 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
 107         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 108         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 109         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 110         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 111 };
 112
 113 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
 114         [QPHY_SW_RESET]                 = QPHY_V5_PCS_SW_RESET,
 115         [QPHY_START_CTRL]               = QPHY_V5_PCS_START_CONTROL,
 116         [QPHY_PCS_STATUS]               = QPHY_V5_PCS_PCS_STATUS1,
 117         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V5_PCS_POWER_DOWN_CONTROL,
 118 };
 119
 120 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
 121         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 122         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 123         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
 124         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 125         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 129         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 130         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 131         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
 139         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
 140         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
 141         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
 146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
 148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 149         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 150         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 151         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
 152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 157         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 159         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 160         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 161         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 162         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 163 };
 164
 165 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
 166         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 167         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 168         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 169         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 170 };
 171
 172 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
 173         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 174         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
 175         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 176         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
 177         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 178         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 179         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 180         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 181         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 182         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
 183         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 184         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 185         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 186         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 187 };
 188
 189 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
 190         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 191         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 192         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 193         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 194         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 195         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 196         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 197         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 198         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
 199         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 200 };
 201
 202 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
 203         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
 204         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
 205         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
 206         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
 207         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
 208         QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
 209         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 210         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 211         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 212         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 213         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 214         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
 215         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
 216         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
 217         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
 218         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 219         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
 220         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
 221         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 222         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 223         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 224         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 225         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 226         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 227         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 228         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 229         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
 230         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
 231         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
 232         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
 233         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
 234         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
 235         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
 236         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
 237         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
 238         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
 239         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 240         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 241         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 242         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 243         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 244         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
 245         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
 246         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 247         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 248         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 249 };
 250
 251 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
 252         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 253         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
 254         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 255 };
 256
 257 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
 258         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 259         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
 260         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 261         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 262         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
 263         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 264         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
 265         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 266         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 267         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 268         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 269         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 270         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 271         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 272         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
 273         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
 274         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
 275         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
 276         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
 277         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
 278         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
 279         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 280         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
 281         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 282         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
 283         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
 284         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 285         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
 286         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 287         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 288 };
 289
 290 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
 291         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
 292         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 293         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 294         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 295         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 296         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 297         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
 298 };
 299
 300 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
 301         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
 302         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 303         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 304         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 305         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 306         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 307         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
 308         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
 309         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
 310 };
 311
 312 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
 313         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
 314         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
 315         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
 316         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
 317         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
 318         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
 319         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
 320         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
 321         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
 322         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
 323         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
 324         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
 325         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
 326         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
 327         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
 328         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
 329         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 330         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
 331         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 332         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 333         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
 334         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
 335         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
 336         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
 337         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
 338         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
 339         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
 340         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 341         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 342         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
 343         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 344         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
 345         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
 346         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 347         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
 348         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
 349         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
 350         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
 351         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
 352         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
 353 };
 354
 355 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
 356         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 357         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
 358         QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
 359         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 360         QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
 361         QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
 362 };
 363
 364 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
 365         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
 366         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 367         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
 368         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
 369         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
 370         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 371         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
 372 };
 373
 374 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
 375         QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
 376         QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
 377         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
 378         QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
 379         QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
 380         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
 381         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
 382         QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 383         QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
 384         QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
 385         QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
 386 };
 387
 388 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
 389         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
 390         QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
 391         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
 392         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
 393         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
 394         QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
 395         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
 396         QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
 397         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
 398         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
 399         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 400         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
 401         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
 402         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
 403         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
 404         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
 405         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
 406         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
 407         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
 408         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
 409         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
 410         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
 411         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
 412         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
 413         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
 414         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
 415         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
 416         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
 417         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 418         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
 419         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
 420         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
 421         QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
 422         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
 423         QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
 424         QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
 425         QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
 426         QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
 427         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
 428         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
 429         QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
 430         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 431         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
 432         QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
 433         QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
 434         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
 435         QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
 436         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
 437         QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
 438         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
 439         QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
 440         QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
 441         QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
 442         QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
 443         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
 444         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
 445         QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
 446 };
 447
 448 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
 449         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 450         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 451         QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
 452         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
 453 };
 454
 455 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
 456         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 457         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 458         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 459         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
 460         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
 461         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
 462         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 463         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 464         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 465         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
 466         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 467         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
 468         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
 469         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
 470         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
 471         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
 472         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
 473         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
 474         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
 475         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
 476         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
 477         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
 478         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
 479         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
 480         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
 481         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
 482         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 483         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 484         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 485         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
 486 };
 487
 488 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
 489         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
 490         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
 491         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 492         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
 493         QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
 494         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
 495         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
 496         QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
 497         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
 498         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 499         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 500 };
 501
 502 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
 503         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
 504         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 505         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 506         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
 507         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 508         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
 509         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
 510         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 511         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
 512         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
 513         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 514         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
 515         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 516 };
 517
 518 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
 519         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 520         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 521         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
 522         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 523         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
 524         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
 525         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 526         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 527         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 528         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
 529         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
 530         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 531         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 532         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 533         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
 534         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
 535         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 536         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 537         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 538         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 539         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 540         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
 541         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
 542         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 546         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 547         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
 548         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 549         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 550         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
 551         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 552         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 553         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
 554         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 555         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
 556         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 557         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
 558         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 559         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
 560         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
 561 };
 562
 563 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
 564         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
 565         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 566         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 567         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
 568 };
 569
 570 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
 571         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 572         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
 573         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 574         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 575         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
 576         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
 577         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
 578         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
 579         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
 580         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
 581         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
 582         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
 583         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 584         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
 585         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
 586         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
 587 };
 588
 589 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
 590         QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
 591
 592         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 593         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 594         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 595         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 596         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 597
 598         QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
 599         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
 600         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 601         QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
 602         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
 603         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
 604         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
 605
 606         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
 607         QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
 608         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 609
 610         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
 611 };
 612
 613 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
 614         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
 615         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
 616         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
 617         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
 618         QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 619 };
 620
 621 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
 622         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
 623         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
 624         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
 625         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
 626         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
 627         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
 628         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 629         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 630         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
 631         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
 632         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
 633         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
 634         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
 635         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
 636         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
 637         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
 638         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
 639         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
 640         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
 641         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
 642         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
 643         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
 644         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
 645         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
 646         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
 647         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
 648         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
 649         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
 650         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
 651         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
 652         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 653         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
 654         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
 655         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
 656         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
 657         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
 658         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
 659         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
 660         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
 661         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
 662         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
 663         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
 664         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
 665         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
 666         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
 667 };
 668
 669 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
 670         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
 671         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
 672         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
 673         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
 674         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
 675         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
 676         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
 677         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
 678         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
 679         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
 680         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
 681         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
 682         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
 683         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
 684         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
 685         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
 686         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
 687         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
 688         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
 689         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
 690         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
 691         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
 692         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
 693         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
 694         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
 695         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
 696         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
 697         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
 698         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
 699         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
 700         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
 701         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
 702         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
 703         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
 704         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
 705         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
 706         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
 707         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
 708         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
 709         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
 710         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
 711         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
 712         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
 713         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
 714         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
 715         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
 716         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
 717         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
 718         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
 719         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
 720         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
 721         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
 722         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
 723         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
 724         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
 725         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
 726 };
 727
 728 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = {
 729 };
 730
 731 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
 732         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
 733         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
 734         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
 735         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
 736         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
 737         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
 738         QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
 739 };
 740
 741 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
 742         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
 743         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
 744         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 745         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 746         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
 747         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 748         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
 749         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
 750         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 751         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 752         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 753         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
 754         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
 755         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
 756         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
 757         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
 758         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
 759         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 760         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
 761         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 762         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
 763         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
 764         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 765         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 766         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 767         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 768         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 769         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 770         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 771         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 772         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 773         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
 774         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
 775         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
 776         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 777         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 778         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 779         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 780         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 781         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 782         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 783         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
 784 };
 785
 786 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
 787         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
 789 };
 790
 791 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
 792         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
 798         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
 799         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 800         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 801         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
 802         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
 803         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 804         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
 806         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
 807         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
 808         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
 809         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
 810         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
 811         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
 815         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 816         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
 817         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
 818         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
 819         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
 820         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 821         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 822         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 823         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
 824         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 825         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
 826         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
 827         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
 828 };
 829
 830 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
 831         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 832         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 833         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
 834         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
 835         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
 836 };
 837
 838 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
 839         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 840         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 841         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
 842         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 843         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
 844         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
 845         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 846 };
 847
 848 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
 849         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
 850         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
 851         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
 852         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 853         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 854         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
 855         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
 856         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
 857         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
 858         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
 859         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
 860         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
 861         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
 862         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
 863         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
 864         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
 865         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
 866         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
 867         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
 868         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
 869         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
 870         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
 871         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
 872         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
 873         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
 874         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
 875         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
 876         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
 877         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
 878         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
 879         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
 880         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
 881         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
 882         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
 883         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
 884         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
 885         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
 886         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 887         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
 888         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
 889         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 890 };
 891
 892 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
 893         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
 894 };
 895
 896 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
 897         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
 898 };
 899
 900 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
 901         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
 902 };
 903
 904 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
 905         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
 906         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
 907         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 908         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
 909         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
 910 };
 911
 912 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
 913         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
 914         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
 915         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
 916         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
 917         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
 918         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
 919         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
 920         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
 921         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
 922         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
 923         QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
 924         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
 925         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
 926         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 927         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 928         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 929         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
 930         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 931 };
 932
 933 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
 934         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
 935         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
 936         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
 937 };
 938
 939 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
 940         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 941         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
 942         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
 943         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 944 };
 945
 946 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
 947         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
 948         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
 949         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
 950         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
 951         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 952         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
 953 };
 954
 955 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
 956         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
 957         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
 958         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
 959         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
 960         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
 961         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
 962         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
 963         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
 964         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
 965         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
 966         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
 967         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 968         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 969         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 970         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 971         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
 972         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 973 };
 974
 975 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
 976         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
 977         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
 978         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
 979         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
 980 };
 981
 982 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
 983         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
 984         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
 985         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
 986         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
 987 };
 988
 989 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
 990         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
 991         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
 992         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 993         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 994         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
 995         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 996         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
 997         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
 998         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 999         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1000         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
1001         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
1002         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
1003         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1004         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1005         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1006         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1007         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1008         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1009         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1010         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1011         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1012         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1013         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1014         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1015         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1016         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1017         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1018         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1019         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1020         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1021         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1022         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1023         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1024         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1025         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1026         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1027         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1028         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1029         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1030         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1031 };
1032
1033 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1034         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1035 };
1036
1037 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1038         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1039         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1040         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1041 };
1042
1043 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1044         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1045         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1046         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1047         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1048         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1049         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1050         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1051         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1052         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1053         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1054         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1055         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1056         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1057         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1058         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1059         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1060         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1061         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1062         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1063         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1064         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1065         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1066         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1067         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1068         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1069         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1070         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1071         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1072         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1073         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1074 };
1075
1076 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1077         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1078         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1079         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1080         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1081         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1082         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1083 };
1084
1085 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1086         QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1087         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1088         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1089 };
1090
1091 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1092         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1093         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1094 };
1095
1096 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1097         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1098         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1099         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1100         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1101         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1102         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1103         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1104 };
1105
1106 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1107         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1108         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1109 };
1110
1111 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1112         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1113 };
1114
1115 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1116         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1117         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1118         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1119         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1120 };
1121
1122 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1123         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1124         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1125 };
1126
1127 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1128         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1129         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1130 };
1131
1132 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1133         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1134         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1135         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1136         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1137         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1138         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1139         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1140         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1141         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1142         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1143         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1144         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1145         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1146         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1147         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1148         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1149         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1150         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1151         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1152         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1153         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1154         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1155         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1156         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1157         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1158         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1159         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1160         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1161         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1162         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1163         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1164         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1165         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1166         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1167         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1168         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1169         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1170         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1171         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1172 };
1173
1174 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1175         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1176         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1177         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1178         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1179         QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1180 };
1181
1182 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1183         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1184         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1185         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1186         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1187         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1188         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1189         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1190         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1191         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1192         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1193         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1194         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1195         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1196         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1197         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1198         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1199         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1200         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1201         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1202         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1203         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1204         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1205         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1206         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1207         QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1208 };
1209
1210 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1211         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1212         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1213         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1214         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1215 };
1216
1217 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1218         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1219         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1220         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1221         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1222         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1223         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1224         QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1225 };
1226
1227 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
1228         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1229         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1230         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1231         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1232         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1233         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1234         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1235         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1236         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1237         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1238         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1239         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1240         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1241         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1242         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1243         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1244         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1245         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1246         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1247         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1248         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1249         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1250         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1251         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1252         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1253         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1254         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1255         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1256         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1257         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1258         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1259         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1260         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1261         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1262         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1263         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1264         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1265         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1266         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1267         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1268         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1269 };
1270
1271 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1272         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1273 };
1274
1275 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1276         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1277         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1278         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1279         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1280         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1281 };
1282
1283 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
1284         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1285         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1286         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1287         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1288         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1289         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1290         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1291         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1292         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1293         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1294         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1295         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1296         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1297         QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1298 };
1299
1300 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1301         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1302         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1303         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1304         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1305         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1306         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1307         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1308         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1309 };
1310
1311 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
1312         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1313         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1314         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1315 };
1316
1317 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1318         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1319         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1320         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1321         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1322 };
1323
1324 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1325         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1326         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1327         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1328         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1329         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1330 };
1331
1332 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1333         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1334         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1335         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1336         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1337 };
1338
1339 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1340         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1341         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1342         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1343 };
1344
1345 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1346         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1347         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1348         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1349         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1350         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1351         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1352 };
1353
1354 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1355         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1356 };
1357
1358 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
1359         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1360         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1361         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1362         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1363         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1364         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1365         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1366         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1367         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1368         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1369         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1370         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1371         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1372 };
1373
1374 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
1375         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1376         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1377         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1378         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1379         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1380         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1381         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1382         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1383         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1384         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1385         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1386         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1387         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1388         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1389         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1390         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1391         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1392         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1393         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1394         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
1395         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1396         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1397         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1398         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1399         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
1400         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1401         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1402         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
1403 };
1404
1405 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
1406         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1407         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1408         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1409         QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1410 };
1411
1412 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
1413         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1414         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1415         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1416         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1417         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1418         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1419         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1420         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1421         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
1422         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1423         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1424         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
1425         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1426         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
1427         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
1428         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
1429         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1430         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1431         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1432         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1433         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1434         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1435         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1436         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1437
1438         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1439
1440         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1441
1442         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1443         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1444         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1445         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1446         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1447         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1448         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1449         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1450
1451         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1452         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1453         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1454         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1455         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1456         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1457         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1458         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1459         QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1460 };
1461
1462 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
1463         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1464         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1465         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1466         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
1467 };
1468
1469 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1470         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1471         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1472         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1473         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1474 };
1475
1476 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
1477         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1478         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1479         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
1480 };
1481
1482 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
1483         QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1484         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1485         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1486         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1487         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1488         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1489         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1490         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1491         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1492         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1493         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1494         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1495         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1496         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1497         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1498         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1499         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1500         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1501         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1502         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1503 };
1504
1505 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
1506         QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1507 };
1508
1509 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
1510         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1511         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1512         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1513         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1514         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1515         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
1516         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1517         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1518         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1519         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1520         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1521         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1522         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1523         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1524         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1525         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1526         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1527         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1528         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
1529         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1530         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1531         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1532         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1533         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1534         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
1535         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1536         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1537         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1538         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1539         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1540         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
1541         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1542         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1543         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1544         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1545         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1546         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
1547         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1548 };
1549
1550 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
1551         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
1552         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
1553         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
1554         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1555         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
1556 };
1557
1558 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
1559         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1560         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
1561         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
1562         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
1563         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
1564         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
1565         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
1566         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
1567         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
1568         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
1569         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
1570         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
1571         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
1572         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
1573         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
1574         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
1575         QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
1576         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
1577         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
1578         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
1579         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
1580         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
1581         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
1582         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1583         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
1584 };
1585
1586 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
1587         QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
1588         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
1589         QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
1590         QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
1591         QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
1592 };
1593
1594 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1595         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1596         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1597         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1598         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1599 };
1600
1601 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
1602         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1603         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1604         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1605         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1606         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1607         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1608         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1609         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1610         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1611         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1612         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1613         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1614         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1615         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1616         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1617         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1618         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1619         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1620         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1621         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1622         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1623         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1624         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1625         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1626         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1627         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1628         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1629         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1630         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1631         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1632         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1633         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1634         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1635         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1636         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1637         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1638         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1639         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1640         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1641         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1642         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1643         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1644         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1645         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1646         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1647 };
1648
1649 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1650         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1651         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
1652         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
1653         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1654         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1655         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1656         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1657         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1658         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1659         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1660         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1661         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1662         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1663         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1664         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1665         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1666         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1667         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1668         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1669         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1670         QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1671 };
1672
1673 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
1674         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1675         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1676         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1677         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
1678         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1679         QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1680 };
1681
1682 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
1683         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
1684         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1685         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1686         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1687         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1688         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1689         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
1690         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1691         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1692         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1693         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1694         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1695         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1696         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
1697         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1698         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1699         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1700         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1701         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1702         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1703         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1704         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
1705         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
1706         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
1707         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1708         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
1709         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1710         QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1711 };
1712
1713 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
1714         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1715         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
1716         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1717         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1718         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1719         QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1720 };
1721
1722 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1723         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1724         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1725         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1726         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1727         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1728         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1729         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1730         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1731         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1732         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1733         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1734         QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1735 };
1736
1737 struct qmp_pcie_offsets {
1738         u16 serdes;
1739         u16 pcs;
1740         u16 pcs_misc;
1741         u16 tx;
1742         u16 rx;
1743         u16 tx2;
1744         u16 rx2;
1745         u16 ln_shrd;
1746 };
1747
1748 struct qmp_phy_cfg_tbls {
1749         const struct qmp_phy_init_tbl *serdes;
1750         int serdes_num;
1751         const struct qmp_phy_init_tbl *tx;
1752         int tx_num;
1753         const struct qmp_phy_init_tbl *rx;
1754         int rx_num;
1755         const struct qmp_phy_init_tbl *pcs;
1756         int pcs_num;
1757         const struct qmp_phy_init_tbl *pcs_misc;
1758         int pcs_misc_num;
1759         const struct qmp_phy_init_tbl *ln_shrd;
1760         int ln_shrd_num;
1761 };
1762
1763 /* struct qmp_phy_cfg - per-PHY initialization config */
1764 struct qmp_phy_cfg {
1765         int lanes;
1766
1767         const struct qmp_pcie_offsets *offsets;
1768
1769         /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1770         const struct qmp_phy_cfg_tbls tbls;
1771         /*
1772          * Additional init sequences for PHY blocks, providing additional
1773          * register programming. They are used for providing separate sequences
1774          * for the Root Complex and End Point use cases.
1775          *
1776          * If EP mode is not supported, both tables can be left unset.
1777          */
1778         const struct qmp_phy_cfg_tbls *tbls_rc;
1779         const struct qmp_phy_cfg_tbls *tbls_ep;
1780
1781         const struct qmp_phy_init_tbl *serdes_4ln_tbl;
1782         int serdes_4ln_num;
1783
1784         /* clock ids to be requested */
1785         const char * const *clk_list;
1786         int num_clks;
1787         /* resets to be requested */
1788         const char * const *reset_list;
1789         int num_resets;
1790         /* regulators to be requested */
1791         const char * const *vreg_list;
1792         int num_vregs;
1793
1794         /* array of registers with different offsets */
1795         const unsigned int *regs;
1796
1797         unsigned int pwrdn_ctrl;
1798         /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
1799         unsigned int phy_status;
1800
1801         bool skip_start_delay;
1802
1803         bool has_nocsr_reset;
1804
1805         /* QMP PHY pipe clock interface rate */
1806         unsigned long pipe_clock_rate;
1807 };
1808
1809 struct qmp_pcie {
1810         struct device *dev;
1811
1812         const struct qmp_phy_cfg *cfg;
1813         bool tcsr_4ln_config;
1814
1815         void __iomem *serdes;
1816         void __iomem *pcs;
1817         void __iomem *pcs_misc;
1818         void __iomem *tx;
1819         void __iomem *rx;
1820         void __iomem *tx2;
1821         void __iomem *rx2;
1822         void __iomem *ln_shrd;
1823
1824         void __iomem *port_b;
1825
1826         struct clk_bulk_data *clks;
1827         struct clk_bulk_data pipe_clks[2];
1828         int num_pipe_clks;
1829
1830         struct reset_control_bulk_data *resets;
1831         struct reset_control *nocsr_reset;
1832         struct regulator_bulk_data *vregs;
1833
1834         struct phy *phy;
1835         int mode;
1836
1837         struct clk_fixed_rate pipe_clk_fixed;
1838 };
1839
1840 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1841 {
1842         u32 reg;
1843
1844         reg = readl(base + offset);
1845         reg |= val;
1846         writel(reg, base + offset);
1847
1848         /* ensure that above write is through */
1849         readl(base + offset);
1850 }
1851
1852 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1853 {
1854         u32 reg;
1855
1856         reg = readl(base + offset);
1857         reg &= ~val;
1858         writel(reg, base + offset);
1859
1860         /* ensure that above write is through */
1861         readl(base + offset);
1862 }
1863
1864 /* list of clocks required by phy */
1865 static const char * const ipq8074_pciephy_clk_l[] = {
1866         "aux", "cfg_ahb",
1867 };
1868
1869 static const char * const msm8996_phy_clk_l[] = {
1870         "aux", "cfg_ahb", "ref",
1871 };
1872
1873 static const char * const sc8280xp_pciephy_clk_l[] = {
1874         "aux", "cfg_ahb", "ref", "rchng",
1875 };
1876
1877 static const char * const sdm845_pciephy_clk_l[] = {
1878         "aux", "cfg_ahb", "ref", "refgen",
1879 };
1880
1881 /* list of regulators */
1882 static const char * const qmp_phy_vreg_l[] = {
1883         "vdda-phy", "vdda-pll",
1884 };
1885
1886 static const char * const sm8550_qmp_phy_vreg_l[] = {
1887         "vdda-phy", "vdda-pll", "vdda-qref",
1888 };
1889
1890 /* list of resets */
1891 static const char * const ipq8074_pciephy_reset_l[] = {
1892         "phy", "common",
1893 };
1894
1895 static const char * const sdm845_pciephy_reset_l[] = {
1896         "phy",
1897 };
1898
1899 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
1900         .serdes         = 0,
1901         .pcs            = 0x0200,
1902         .pcs_misc       = 0x0600,
1903         .tx             = 0x0e00,
1904         .rx             = 0x1000,
1905         .tx2            = 0x1600,
1906         .rx2            = 0x1800,
1907 };
1908
1909 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
1910         .serdes         = 0x1000,
1911         .pcs            = 0x1200,
1912         .pcs_misc       = 0x1400,
1913         .tx             = 0x0000,
1914         .rx             = 0x0200,
1915         .tx2            = 0x0800,
1916         .rx2            = 0x0a00,
1917         .ln_shrd        = 0x0e00,
1918 };
1919
1920 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
1921         .lanes                  = 1,
1922
1923         .tbls = {
1924                 .serdes         = ipq8074_pcie_serdes_tbl,
1925                 .serdes_num     = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
1926                 .tx             = ipq8074_pcie_tx_tbl,
1927                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
1928                 .rx             = ipq8074_pcie_rx_tbl,
1929                 .rx_num         = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
1930                 .pcs            = ipq8074_pcie_pcs_tbl,
1931                 .pcs_num        = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
1932         },
1933         .clk_list               = ipq8074_pciephy_clk_l,
1934         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1935         .reset_list             = ipq8074_pciephy_reset_l,
1936         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1937         .vreg_list              = NULL,
1938         .num_vregs              = 0,
1939         .regs                   = pciephy_v2_regs_layout,
1940
1941         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1942         .phy_status             = PHYSTATUS,
1943 };
1944
1945 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
1946         .lanes                  = 1,
1947
1948         .tbls = {
1949                 .serdes         = ipq8074_pcie_gen3_serdes_tbl,
1950                 .serdes_num     = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
1951                 .tx             = ipq8074_pcie_gen3_tx_tbl,
1952                 .tx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
1953                 .rx             = ipq8074_pcie_gen3_rx_tbl,
1954                 .rx_num         = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
1955                 .pcs            = ipq8074_pcie_gen3_pcs_tbl,
1956                 .pcs_num        = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
1957                 .pcs_misc       = ipq8074_pcie_gen3_pcs_misc_tbl,
1958                 .pcs_misc_num   = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
1959         },
1960         .clk_list               = ipq8074_pciephy_clk_l,
1961         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1962         .reset_list             = ipq8074_pciephy_reset_l,
1963         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1964         .vreg_list              = NULL,
1965         .num_vregs              = 0,
1966         .regs                   = pciephy_v4_regs_layout,
1967
1968         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1969         .phy_status             = PHYSTATUS,
1970
1971         .pipe_clock_rate        = 250000000,
1972 };
1973
1974 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
1975         .lanes                  = 1,
1976
1977         .tbls = {
1978                 .serdes         = ipq6018_pcie_serdes_tbl,
1979                 .serdes_num     = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
1980                 .tx             = ipq6018_pcie_tx_tbl,
1981                 .tx_num         = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
1982                 .rx             = ipq6018_pcie_rx_tbl,
1983                 .rx_num         = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
1984                 .pcs            = ipq6018_pcie_pcs_tbl,
1985                 .pcs_num        = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
1986                 .pcs_misc       = ipq6018_pcie_pcs_misc_tbl,
1987                 .pcs_misc_num   = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
1988         },
1989         .clk_list               = ipq8074_pciephy_clk_l,
1990         .num_clks               = ARRAY_SIZE(ipq8074_pciephy_clk_l),
1991         .reset_list             = ipq8074_pciephy_reset_l,
1992         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
1993         .vreg_list              = NULL,
1994         .num_vregs              = 0,
1995         .regs                   = pciephy_v4_regs_layout,
1996
1997         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
1998         .phy_status             = PHYSTATUS,
1999 };
2000
2001 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2002         .lanes                  = 1,
2003
2004         .tbls = {
2005                 .serdes         = sdm845_qmp_pcie_serdes_tbl,
2006                 .serdes_num     = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2007                 .tx             = sdm845_qmp_pcie_tx_tbl,
2008                 .tx_num         = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2009                 .rx             = sdm845_qmp_pcie_rx_tbl,
2010                 .rx_num         = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2011                 .pcs            = sdm845_qmp_pcie_pcs_tbl,
2012                 .pcs_num        = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2013                 .pcs_misc       = sdm845_qmp_pcie_pcs_misc_tbl,
2014                 .pcs_misc_num   = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2015         },
2016         .clk_list               = sdm845_pciephy_clk_l,
2017         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2018         .reset_list             = sdm845_pciephy_reset_l,
2019         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2020         .vreg_list              = qmp_phy_vreg_l,
2021         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2022         .regs                   = pciephy_v3_regs_layout,
2023
2024         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2025         .phy_status             = PHYSTATUS,
2026 };
2027
2028 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2029         .lanes                  = 1,
2030
2031         .tbls = {
2032                 .serdes         = sdm845_qhp_pcie_serdes_tbl,
2033                 .serdes_num     = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2034                 .tx             = sdm845_qhp_pcie_tx_tbl,
2035                 .tx_num         = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2036                 .rx             = sdm845_qhp_pcie_rx_tbl,
2037                 .rx_num         = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl),
2038                 .pcs            = sdm845_qhp_pcie_pcs_tbl,
2039                 .pcs_num        = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2040         },
2041         .clk_list               = sdm845_pciephy_clk_l,
2042         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2043         .reset_list             = sdm845_pciephy_reset_l,
2044         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2045         .vreg_list              = qmp_phy_vreg_l,
2046         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2047         .regs                   = sdm845_qhp_pciephy_regs_layout,
2048
2049         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2050         .phy_status             = PHYSTATUS,
2051 };
2052
2053 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
2054         .lanes                  = 1,
2055
2056         .tbls = {
2057                 .serdes         = sm8250_qmp_pcie_serdes_tbl,
2058                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2059                 .tx             = sm8250_qmp_pcie_tx_tbl,
2060                 .tx_num         = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2061                 .rx             = sm8250_qmp_pcie_rx_tbl,
2062                 .rx_num         = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2063                 .pcs            = sm8250_qmp_pcie_pcs_tbl,
2064                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2065                 .pcs_misc       = sm8250_qmp_pcie_pcs_misc_tbl,
2066                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2067         },
2068         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2069                 .serdes         = sm8250_qmp_gen3x1_pcie_serdes_tbl,
2070                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
2071                 .rx             = sm8250_qmp_gen3x1_pcie_rx_tbl,
2072                 .rx_num         = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
2073                 .pcs            = sm8250_qmp_gen3x1_pcie_pcs_tbl,
2074                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
2075                 .pcs_misc       = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
2076                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
2077         },
2078         .clk_list               = sdm845_pciephy_clk_l,
2079         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2080         .reset_list             = sdm845_pciephy_reset_l,
2081         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2082         .vreg_list              = qmp_phy_vreg_l,
2083         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2084         .regs                   = pciephy_v4_regs_layout,
2085
2086         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2087         .phy_status             = PHYSTATUS,
2088 };
2089
2090 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
2091         .lanes                  = 2,
2092
2093         .tbls = {
2094                 .serdes         = sm8250_qmp_pcie_serdes_tbl,
2095                 .serdes_num     = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2096                 .tx             = sm8250_qmp_pcie_tx_tbl,
2097                 .tx_num         = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2098                 .rx             = sm8250_qmp_pcie_rx_tbl,
2099                 .rx_num         = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2100                 .pcs            = sm8250_qmp_pcie_pcs_tbl,
2101                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2102                 .pcs_misc       = sm8250_qmp_pcie_pcs_misc_tbl,
2103                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2104         },
2105         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2106                 .tx             = sm8250_qmp_gen3x2_pcie_tx_tbl,
2107                 .tx_num         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
2108                 .rx             = sm8250_qmp_gen3x2_pcie_rx_tbl,
2109                 .rx_num         = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
2110                 .pcs            = sm8250_qmp_gen3x2_pcie_pcs_tbl,
2111                 .pcs_num        = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
2112                 .pcs_misc       = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
2113                 .pcs_misc_num   = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
2114         },
2115         .clk_list               = sdm845_pciephy_clk_l,
2116         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2117         .reset_list             = sdm845_pciephy_reset_l,
2118         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2119         .vreg_list              = qmp_phy_vreg_l,
2120         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2121         .regs                   = pciephy_v4_regs_layout,
2122
2123         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2124         .phy_status             = PHYSTATUS,
2125 };
2126
2127 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2128         .lanes                  = 1,
2129
2130         .tbls = {
2131                 .serdes         = msm8998_pcie_serdes_tbl,
2132                 .serdes_num     = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2133                 .tx             = msm8998_pcie_tx_tbl,
2134                 .tx_num         = ARRAY_SIZE(msm8998_pcie_tx_tbl),
2135                 .rx             = msm8998_pcie_rx_tbl,
2136                 .rx_num         = ARRAY_SIZE(msm8998_pcie_rx_tbl),
2137                 .pcs            = msm8998_pcie_pcs_tbl,
2138                 .pcs_num        = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2139         },
2140         .clk_list               = msm8996_phy_clk_l,
2141         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
2142         .reset_list             = ipq8074_pciephy_reset_l,
2143         .num_resets             = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2144         .vreg_list              = qmp_phy_vreg_l,
2145         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2146         .regs                   = pciephy_v3_regs_layout,
2147
2148         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2149         .phy_status             = PHYSTATUS,
2150
2151         .skip_start_delay       = true,
2152 };
2153
2154 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
2155         .lanes                  = 1,
2156
2157         .tbls = {
2158                 .serdes         = sc8180x_qmp_pcie_serdes_tbl,
2159                 .serdes_num     = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
2160                 .tx             = sc8180x_qmp_pcie_tx_tbl,
2161                 .tx_num         = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
2162                 .rx             = sc8180x_qmp_pcie_rx_tbl,
2163                 .rx_num         = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
2164                 .pcs            = sc8180x_qmp_pcie_pcs_tbl,
2165                 .pcs_num        = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
2166                 .pcs_misc       = sc8180x_qmp_pcie_pcs_misc_tbl,
2167                 .pcs_misc_num   = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
2168         },
2169         .clk_list               = sdm845_pciephy_clk_l,
2170         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2171         .reset_list             = sdm845_pciephy_reset_l,
2172         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2173         .vreg_list              = qmp_phy_vreg_l,
2174         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2175         .regs                   = pciephy_v4_regs_layout,
2176
2177         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2178         .phy_status             = PHYSTATUS,
2179 };
2180
2181 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
2182         .lanes                  = 1,
2183
2184         .offsets                = &qmp_pcie_offsets_v5,
2185
2186         .tbls = {
2187                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
2188                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2189                 .tx             = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
2190                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
2191                 .rx             = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
2192                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
2193                 .pcs            = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
2194                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
2195                 .pcs_misc       = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
2196                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
2197         },
2198
2199         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2200                 .serdes         = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
2201                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
2202         },
2203
2204         .clk_list               = sc8280xp_pciephy_clk_l,
2205         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2206         .reset_list             = sdm845_pciephy_reset_l,
2207         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2208         .vreg_list              = qmp_phy_vreg_l,
2209         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2210         .regs                   = pciephy_v5_regs_layout,
2211
2212         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2213         .phy_status             = PHYSTATUS,
2214 };
2215
2216 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
2217         .lanes                  = 2,
2218
2219         .offsets                = &qmp_pcie_offsets_v5,
2220
2221         .tbls = {
2222                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
2223                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2224                 .tx             = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2225                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
2226                 .rx             = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
2227                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
2228                 .pcs            = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2229                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
2230                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2231                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2232         },
2233
2234         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2235                 .serdes         = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
2236                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
2237         },
2238
2239         .clk_list               = sc8280xp_pciephy_clk_l,
2240         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2241         .reset_list             = sdm845_pciephy_reset_l,
2242         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2243         .vreg_list              = qmp_phy_vreg_l,
2244         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2245         .regs                   = pciephy_v5_regs_layout,
2246
2247         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2248         .phy_status             = PHYSTATUS,
2249 };
2250
2251 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
2252         .lanes                  = 4,
2253
2254         .offsets                = &qmp_pcie_offsets_v5,
2255
2256         .tbls = {
2257                 .serdes         = sc8280xp_qmp_pcie_serdes_tbl,
2258                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2259                 .tx             = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2260                 .tx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
2261                 .rx             = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
2262                 .rx_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
2263                 .pcs            = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2264                 .pcs_num        = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
2265                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2266                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2267         },
2268
2269         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2270                 .serdes         = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
2271                 .serdes_num     = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
2272         },
2273
2274         .serdes_4ln_tbl         = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
2275         .serdes_4ln_num         = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
2276
2277         .clk_list               = sc8280xp_pciephy_clk_l,
2278         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2279         .reset_list             = sdm845_pciephy_reset_l,
2280         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2281         .vreg_list              = qmp_phy_vreg_l,
2282         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2283         .regs                   = pciephy_v5_regs_layout,
2284
2285         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2286         .phy_status             = PHYSTATUS,
2287 };
2288
2289 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
2290         .lanes                  = 2,
2291
2292         .tbls = {
2293                 .serdes         = sdx55_qmp_pcie_serdes_tbl,
2294                 .serdes_num     = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
2295                 .tx             = sdx55_qmp_pcie_tx_tbl,
2296                 .tx_num         = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
2297                 .rx             = sdx55_qmp_pcie_rx_tbl,
2298                 .rx_num         = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
2299                 .pcs            = sdx55_qmp_pcie_pcs_tbl,
2300                 .pcs_num        = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
2301                 .pcs_misc       = sdx55_qmp_pcie_pcs_misc_tbl,
2302                 .pcs_misc_num   = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
2303         },
2304         .clk_list               = sdm845_pciephy_clk_l,
2305         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2306         .reset_list             = sdm845_pciephy_reset_l,
2307         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2308         .vreg_list              = qmp_phy_vreg_l,
2309         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2310         .regs                   = pciephy_v4_regs_layout,
2311
2312         .pwrdn_ctrl             = SW_PWRDN,
2313         .phy_status             = PHYSTATUS_4_20,
2314 };
2315
2316 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
2317         .lanes                  = 1,
2318
2319         .offsets                = &qmp_pcie_offsets_v5,
2320
2321         .tbls = {
2322                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
2323                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2324                 .tx             = sm8350_qmp_gen3x1_pcie_tx_tbl,
2325                 .tx_num         = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
2326                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
2327                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2328                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
2329                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2330                 .pcs_misc       = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2331                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2332         },
2333
2334         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2335                 .serdes         = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2336                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2337                 .rx             = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
2338                 .rx_num         = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
2339         },
2340
2341         .clk_list               = sc8280xp_pciephy_clk_l,
2342         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2343         .reset_list             = sdm845_pciephy_reset_l,
2344         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2345         .vreg_list              = qmp_phy_vreg_l,
2346         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2347         .regs                   = pciephy_v5_regs_layout,
2348
2349         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2350         .phy_status             = PHYSTATUS,
2351 };
2352
2353 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
2354         .lanes                  = 2,
2355
2356         .offsets                = &qmp_pcie_offsets_v5,
2357
2358         .tbls = {
2359                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
2360                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2361                 .tx             = sm8350_qmp_gen3x2_pcie_tx_tbl,
2362                 .tx_num         = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
2363                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
2364                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2365                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
2366                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2367                 .pcs_misc       = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2368                 .pcs_misc_num   = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2369         },
2370
2371         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2372                 .rx             = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
2373                 .rx_num         = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
2374                 .pcs            = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2375                 .pcs_num        = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
2376         },
2377
2378         .clk_list               = sc8280xp_pciephy_clk_l,
2379         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2380         .reset_list             = sdm845_pciephy_reset_l,
2381         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2382         .vreg_list              = qmp_phy_vreg_l,
2383         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2384         .regs                   = pciephy_v5_regs_layout,
2385
2386         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2387         .phy_status             = PHYSTATUS,
2388 };
2389
2390 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
2391         .lanes                  = 1,
2392
2393         .tbls = {
2394                 .serdes         = sm8450_qmp_gen3_pcie_serdes_tbl,
2395                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2396                 .tx             = sm8450_qmp_gen3x1_pcie_tx_tbl,
2397                 .tx_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2398                 .rx             = sm8450_qmp_gen3_pcie_rx_tbl,
2399                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2400                 .pcs            = sm8450_qmp_gen3_pcie_pcs_tbl,
2401                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2402                 .pcs_misc       = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2403                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2404         },
2405
2406         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2407                 .serdes         = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2408                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2409                 .rx             = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
2410                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
2411         },
2412
2413         .clk_list               = sdm845_pciephy_clk_l,
2414         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2415         .reset_list             = sdm845_pciephy_reset_l,
2416         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2417         .vreg_list              = qmp_phy_vreg_l,
2418         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2419         .regs                   = pciephy_v5_regs_layout,
2420
2421         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2422         .phy_status             = PHYSTATUS,
2423 };
2424
2425 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
2426         .lanes                  = 2,
2427
2428         .tbls = {
2429                 .serdes         = sm8450_qmp_gen4x2_pcie_serdes_tbl,
2430                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
2431                 .tx             = sm8450_qmp_gen4x2_pcie_tx_tbl,
2432                 .tx_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
2433                 .rx             = sm8450_qmp_gen4x2_pcie_rx_tbl,
2434                 .rx_num         = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
2435                 .pcs            = sm8450_qmp_gen4x2_pcie_pcs_tbl,
2436                 .pcs_num        = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
2437                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
2438                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
2439         },
2440
2441         .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2442                 .serdes         = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
2443                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
2444                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
2445                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
2446         },
2447
2448         .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
2449                 .serdes         = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
2450                 .serdes_num     = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
2451                 .pcs_misc       = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
2452                 .pcs_misc_num   = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
2453         },
2454
2455         .clk_list               = sdm845_pciephy_clk_l,
2456         .num_clks               = ARRAY_SIZE(sdm845_pciephy_clk_l),
2457         .reset_list             = sdm845_pciephy_reset_l,
2458         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2459         .vreg_list              = qmp_phy_vreg_l,
2460         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2461         .regs                   = pciephy_v5_regs_layout,
2462
2463         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2464         .phy_status             = PHYSTATUS_4_20,
2465 };
2466
2467 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
2468         .lanes = 2,
2469
2470         .offsets                = &qmp_pcie_offsets_v5,
2471
2472         .tbls = {
2473                 .serdes         = sm8550_qmp_gen3x2_pcie_serdes_tbl,
2474                 .serdes_num     = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
2475                 .tx             = sm8550_qmp_gen3x2_pcie_tx_tbl,
2476                 .tx_num         = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
2477                 .rx             = sm8550_qmp_gen3x2_pcie_rx_tbl,
2478                 .rx_num         = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
2479                 .pcs            = sm8550_qmp_gen3x2_pcie_pcs_tbl,
2480                 .pcs_num        = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
2481                 .pcs_misc       = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
2482                 .pcs_misc_num   = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
2483         },
2484         .clk_list               = sc8280xp_pciephy_clk_l,
2485         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2486         .reset_list             = sdm845_pciephy_reset_l,
2487         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2488         .vreg_list              = qmp_phy_vreg_l,
2489         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
2490         .regs                   = pciephy_v5_regs_layout,
2491
2492         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2493         .phy_status             = PHYSTATUS,
2494 };
2495
2496 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
2497         .lanes = 2,
2498
2499         .offsets                = &qmp_pcie_offsets_v6_20,
2500
2501         .tbls = {
2502                 .serdes                 = sm8550_qmp_gen4x2_pcie_serdes_tbl,
2503                 .serdes_num             = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
2504                 .tx                     = sm8550_qmp_gen4x2_pcie_tx_tbl,
2505                 .tx_num                 = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
2506                 .rx                     = sm8550_qmp_gen4x2_pcie_rx_tbl,
2507                 .rx_num                 = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
2508                 .pcs                    = sm8550_qmp_gen4x2_pcie_pcs_tbl,
2509                 .pcs_num                = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
2510                 .pcs_misc               = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
2511                 .pcs_misc_num           = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
2512                 .ln_shrd                = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
2513                 .ln_shrd_num            = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
2514         },
2515         .clk_list               = sc8280xp_pciephy_clk_l,
2516         .num_clks               = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
2517         .reset_list             = sdm845_pciephy_reset_l,
2518         .num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),
2519         .vreg_list              = sm8550_qmp_phy_vreg_l,
2520         .num_vregs              = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
2521         .regs                   = pciephy_v5_regs_layout,
2522
2523         .pwrdn_ctrl             = SW_PWRDN | REFCLK_DRV_DSBL,
2524         .phy_status             = PHYSTATUS_4_20,
2525         .has_nocsr_reset        = true,
2526 };
2527
2528 static void qmp_pcie_configure_lane(void __iomem *base,
2529                                         const struct qmp_phy_init_tbl tbl[],
2530                                         int num,
2531                                         u8 lane_mask)
2532 {
2533         int i;
2534         const struct qmp_phy_init_tbl *t = tbl;
2535
2536         if (!t)
2537                 return;
2538
2539         for (i = 0; i < num; i++, t++) {
2540                 if (!(t->lane_mask & lane_mask))
2541                         continue;
2542
2543                 writel(t->val, base + t->offset);
2544         }
2545 }
2546
2547 static void qmp_pcie_configure(void __iomem *base,
2548                                         const struct qmp_phy_init_tbl tbl[],
2549                                         int num)
2550 {
2551         qmp_pcie_configure_lane(base, tbl, num, 0xff);
2552 }
2553
2554 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
2555 {
2556         const struct qmp_phy_cfg *cfg = qmp->cfg;
2557         const struct qmp_pcie_offsets *offs = cfg->offsets;
2558         void __iomem *tx3, *rx3, *tx4, *rx4;
2559
2560         tx3 = qmp->port_b + offs->tx;
2561         rx3 = qmp->port_b + offs->rx;
2562         tx4 = qmp->port_b + offs->tx2;
2563         rx4 = qmp->port_b + offs->rx2;
2564
2565         qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
2566         qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
2567
2568         qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
2569         qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
2570 }
2571
2572 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
2573 {
2574         const struct qmp_phy_cfg *cfg = qmp->cfg;
2575         void __iomem *serdes = qmp->serdes;
2576         void __iomem *tx = qmp->tx;
2577         void __iomem *rx = qmp->rx;
2578         void __iomem *tx2 = qmp->tx2;
2579         void __iomem *rx2 = qmp->rx2;
2580         void __iomem *pcs = qmp->pcs;
2581         void __iomem *pcs_misc = qmp->pcs_misc;
2582         void __iomem *ln_shrd = qmp->ln_shrd;
2583
2584         if (!tbls)
2585                 return;
2586
2587         qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num);
2588
2589         qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
2590         qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
2591
2592         if (cfg->lanes >= 2) {
2593                 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
2594                 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
2595         }
2596
2597         qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
2598         qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
2599
2600         if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
2601                 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
2602                 qmp_pcie_init_port_b(qmp, tbls);
2603         }
2604
2605         qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
2606 }
2607
2608 static int qmp_pcie_init(struct phy *phy)
2609 {
2610         struct qmp_pcie *qmp = phy_get_drvdata(phy);
2611         const struct qmp_phy_cfg *cfg = qmp->cfg;
2612         int ret;
2613
2614         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2615         if (ret) {
2616                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2617                 return ret;
2618         }
2619
2620         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2621         if (ret) {
2622                 dev_err(qmp->dev, "reset assert failed\n");
2623                 goto err_disable_regulators;
2624         }
2625
2626         ret = reset_control_assert(qmp->nocsr_reset);
2627         if (ret) {
2628                 dev_err(qmp->dev, "no-csr reset assert failed\n");
2629                 goto err_assert_reset;
2630         }
2631
2632         usleep_range(200, 300);
2633
2634         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2635         if (ret) {
2636                 dev_err(qmp->dev, "reset deassert failed\n");
2637                 goto err_assert_reset;
2638         }
2639
2640         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2641         if (ret)
2642                 goto err_assert_reset;
2643
2644         return 0;
2645
2646 err_assert_reset:
2647         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2648 err_disable_regulators:
2649         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2650
2651         return ret;
2652 }
2653
2654 static int qmp_pcie_exit(struct phy *phy)
2655 {
2656         struct qmp_pcie *qmp = phy_get_drvdata(phy);
2657         const struct qmp_phy_cfg *cfg = qmp->cfg;
2658
2659         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2660
2661         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2662
2663         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2664
2665         return 0;
2666 }
2667
2668 static int qmp_pcie_power_on(struct phy *phy)
2669 {
2670         struct qmp_pcie *qmp = phy_get_drvdata(phy);
2671         const struct qmp_phy_cfg *cfg = qmp->cfg;
2672         const struct qmp_phy_cfg_tbls *mode_tbls;
2673         void __iomem *pcs = qmp->pcs;
2674         void __iomem *status;
2675         unsigned int mask, val;
2676         int ret;
2677
2678         qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2679                         cfg->pwrdn_ctrl);
2680
2681         if (qmp->mode == PHY_MODE_PCIE_RC)
2682                 mode_tbls = cfg->tbls_rc;
2683         else
2684                 mode_tbls = cfg->tbls_ep;
2685
2686         qmp_pcie_init_registers(qmp, &cfg->tbls);
2687         qmp_pcie_init_registers(qmp, mode_tbls);
2688
2689         ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
2690         if (ret)
2691                 return ret;
2692
2693         ret = reset_control_deassert(qmp->nocsr_reset);
2694         if (ret) {
2695                 dev_err(qmp->dev, "no-csr reset deassert failed\n");
2696                 goto err_disable_pipe_clk;
2697         }
2698
2699         /* Pull PHY out of reset state */
2700         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2701
2702         /* start SerDes and Phy-Coding-Sublayer */
2703         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2704
2705         if (!cfg->skip_start_delay)
2706                 usleep_range(1000, 1200);
2707
2708         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2709         mask = cfg->phy_status;
2710         ret = readl_poll_timeout(status, val, !(val & mask), 200,
2711                                  PHY_INIT_COMPLETE_TIMEOUT);
2712         if (ret) {
2713                 dev_err(qmp->dev, "phy initialization timed-out\n");
2714                 goto err_disable_pipe_clk;
2715         }
2716
2717         return 0;
2718
2719 err_disable_pipe_clk:
2720         clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
2721
2722         return ret;
2723 }
2724
2725 static int qmp_pcie_power_off(struct phy *phy)
2726 {
2727         struct qmp_pcie *qmp = phy_get_drvdata(phy);
2728         const struct qmp_phy_cfg *cfg = qmp->cfg;
2729
2730         clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
2731
2732         /* PHY reset */
2733         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2734
2735         /* stop SerDes and Phy-Coding-Sublayer */
2736         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2737                         SERDES_START | PCS_START);
2738
2739         /* Put PHY into POWER DOWN state: active low */
2740         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2741                         cfg->pwrdn_ctrl);
2742
2743         return 0;
2744 }
2745
2746 static int qmp_pcie_enable(struct phy *phy)
2747 {
2748         int ret;
2749
2750         ret = qmp_pcie_init(phy);
2751         if (ret)
2752                 return ret;
2753
2754         ret = qmp_pcie_power_on(phy);
2755         if (ret)
2756                 qmp_pcie_exit(phy);
2757
2758         return ret;
2759 }
2760
2761 static int qmp_pcie_disable(struct phy *phy)
2762 {
2763         int ret;
2764
2765         ret = qmp_pcie_power_off(phy);
2766         if (ret)
2767                 return ret;
2768
2769         return qmp_pcie_exit(phy);
2770 }
2771
2772 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2773 {
2774         struct qmp_pcie *qmp = phy_get_drvdata(phy);
2775
2776         switch (submode) {
2777         case PHY_MODE_PCIE_RC:
2778         case PHY_MODE_PCIE_EP:
2779                 qmp->mode = submode;
2780                 break;
2781         default:
2782                 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
2783                 return -EINVAL;
2784         }
2785
2786         return 0;
2787 }
2788
2789 static const struct phy_ops qmp_pcie_phy_ops = {
2790         .power_on       = qmp_pcie_enable,
2791         .power_off      = qmp_pcie_disable,
2792         .set_mode       = qmp_pcie_set_mode,
2793         .owner          = THIS_MODULE,
2794 };
2795
2796 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
2797 {
2798         const struct qmp_phy_cfg *cfg = qmp->cfg;
2799         struct device *dev = qmp->dev;
2800         int num = cfg->num_vregs;
2801         int i;
2802
2803         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2804         if (!qmp->vregs)
2805                 return -ENOMEM;
2806
2807         for (i = 0; i < num; i++)
2808                 qmp->vregs[i].supply = cfg->vreg_list[i];
2809
2810         return devm_regulator_bulk_get(dev, num, qmp->vregs);
2811 }
2812
2813 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
2814 {
2815         const struct qmp_phy_cfg *cfg = qmp->cfg;
2816         struct device *dev = qmp->dev;
2817         int i;
2818         int ret;
2819
2820         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2821                                    sizeof(*qmp->resets), GFP_KERNEL);
2822         if (!qmp->resets)
2823                 return -ENOMEM;
2824
2825         for (i = 0; i < cfg->num_resets; i++)
2826                 qmp->resets[i].id = cfg->reset_list[i];
2827
2828         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2829         if (ret)
2830                 return dev_err_probe(dev, ret, "failed to get resets\n");
2831
2832         if (cfg->has_nocsr_reset) {
2833                 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
2834                 if (IS_ERR(qmp->nocsr_reset))
2835                         return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
2836                                                 "failed to get no-csr reset\n");
2837         }
2838
2839         return 0;
2840 }
2841
2842 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
2843 {
2844         const struct qmp_phy_cfg *cfg = qmp->cfg;
2845         struct device *dev = qmp->dev;
2846         int num = cfg->num_clks;
2847         int i;
2848
2849         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2850         if (!qmp->clks)
2851                 return -ENOMEM;
2852
2853         for (i = 0; i < num; i++)
2854                 qmp->clks[i].id = cfg->clk_list[i];
2855
2856         return devm_clk_bulk_get(dev, num, qmp->clks);
2857 }
2858
2859 static void phy_clk_release_provider(void *res)
2860 {
2861         of_clk_del_provider(res);
2862 }
2863
2864 /*
2865  * Register a fixed rate pipe clock.
2866  *
2867  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2868  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2869  * by the PHY driver for its operations.
2870  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2871  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2872  * Below picture shows this relationship.
2873  *
2874  *         +---------------+
2875  *         |   PHY block   |<<---------------------------------------+
2876  *         |               |                                         |
2877  *         |   +-------+   |                   +-----+               |
2878  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2879  *    clk  |   +-------+   |                   +-----+
2880  *         +---------------+
2881  */
2882 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
2883 {
2884         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2885         struct clk_init_data init = { };
2886         int ret;
2887
2888         ret = of_property_read_string(np, "clock-output-names", &init.name);
2889         if (ret) {
2890                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2891                 return ret;
2892         }
2893
2894         init.ops = &clk_fixed_rate_ops;
2895
2896         /*
2897          * Controllers using QMP PHY-s use 125MHz pipe clock interface
2898          * unless other frequency is specified in the PHY config.
2899          */
2900         if (qmp->cfg->pipe_clock_rate)
2901                 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
2902         else
2903                 fixed->fixed_rate = 125000000;
2904
2905         fixed->hw.init = &init;
2906
2907         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2908         if (ret)
2909                 return ret;
2910
2911         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2912         if (ret)
2913                 return ret;
2914
2915         /*
2916          * Roll a devm action because the clock provider is the child node, but
2917          * the child node is not actually a device.
2918          */
2919         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2920 }
2921
2922 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
2923 {
2924         struct platform_device *pdev = to_platform_device(qmp->dev);
2925         const struct qmp_phy_cfg *cfg = qmp->cfg;
2926         struct device *dev = qmp->dev;
2927         struct clk *clk;
2928
2929         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2930         if (IS_ERR(qmp->serdes))
2931                 return PTR_ERR(qmp->serdes);
2932
2933         /*
2934          * Get memory resources for the PHY:
2935          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2936          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2937          * For single lane PHYs: pcs_misc (optional) -> 3.
2938          */
2939         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2940         if (IS_ERR(qmp->tx))
2941                 return PTR_ERR(qmp->tx);
2942
2943         if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
2944                 qmp->rx = qmp->tx;
2945         else
2946                 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2947         if (IS_ERR(qmp->rx))
2948                 return PTR_ERR(qmp->rx);
2949
2950         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
2951         if (IS_ERR(qmp->pcs))
2952                 return PTR_ERR(qmp->pcs);
2953
2954         if (cfg->lanes >= 2) {
2955                 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2956                 if (IS_ERR(qmp->tx2))
2957                         return PTR_ERR(qmp->tx2);
2958
2959                 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2960                 if (IS_ERR(qmp->rx2))
2961                         return PTR_ERR(qmp->rx2);
2962
2963                 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2964         } else {
2965                 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2966         }
2967
2968         if (IS_ERR(qmp->pcs_misc) &&
2969             of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
2970                 qmp->pcs_misc = qmp->pcs + 0x400;
2971
2972         if (IS_ERR(qmp->pcs_misc)) {
2973                 if (cfg->tbls.pcs_misc ||
2974                     (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
2975                     (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
2976                         return PTR_ERR(qmp->pcs_misc);
2977                 }
2978         }
2979
2980         clk = devm_get_clk_from_child(dev, np, NULL);
2981         if (IS_ERR(clk)) {
2982                 return dev_err_probe(dev, PTR_ERR(clk),
2983                                      "failed to get pipe clock\n");
2984         }
2985
2986         qmp->num_pipe_clks = 1;
2987         qmp->pipe_clks[0].id = "pipe";
2988         qmp->pipe_clks[0].clk = clk;
2989
2990         return 0;
2991 }
2992
2993 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
2994 {
2995         struct regmap *tcsr;
2996         unsigned int args[2];
2997         int ret;
2998
2999         tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
3000                                                     "qcom,4ln-config-sel",
3001                                                     ARRAY_SIZE(args), args);
3002         if (IS_ERR(tcsr)) {
3003                 ret = PTR_ERR(tcsr);
3004                 if (ret == -ENOENT)
3005                         return 0;
3006
3007                 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
3008                 return ret;
3009         }
3010
3011         ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
3012         if (ret < 0) {
3013                 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
3014                 return ret;
3015         }
3016
3017         qmp->tcsr_4ln_config = ret;
3018
3019         dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
3020
3021         return 0;
3022 }
3023
3024 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
3025 {
3026         struct platform_device *pdev = to_platform_device(qmp->dev);
3027         const struct qmp_phy_cfg *cfg = qmp->cfg;
3028         const struct qmp_pcie_offsets *offs = cfg->offsets;
3029         struct device *dev = qmp->dev;
3030         void __iomem *base;
3031         int ret;
3032
3033         if (!offs)
3034                 return -EINVAL;
3035
3036         ret = qmp_pcie_get_4ln_config(qmp);
3037         if (ret)
3038                 return ret;
3039
3040         base = devm_platform_ioremap_resource(pdev, 0);
3041         if (IS_ERR(base))
3042                 return PTR_ERR(base);
3043
3044         qmp->serdes = base + offs->serdes;
3045         qmp->pcs = base + offs->pcs;
3046         qmp->pcs_misc = base + offs->pcs_misc;
3047         qmp->tx = base + offs->tx;
3048         qmp->rx = base + offs->rx;
3049
3050         if (cfg->lanes >= 2) {
3051                 qmp->tx2 = base + offs->tx2;
3052                 qmp->rx2 = base + offs->rx2;
3053         }
3054
3055         if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3056                 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
3057                 if (IS_ERR(qmp->port_b))
3058                         return PTR_ERR(qmp->port_b);
3059         }
3060
3061         if (cfg->tbls.ln_shrd)
3062                 qmp->ln_shrd = base + offs->ln_shrd;
3063
3064         qmp->num_pipe_clks = 2;
3065         qmp->pipe_clks[0].id = "pipe";
3066         qmp->pipe_clks[1].id = "pipediv2";
3067
3068         ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
3069         if (ret)
3070                 return ret;
3071
3072         ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
3073         if (ret)
3074                 return ret;
3075
3076         return 0;
3077 }
3078
3079 static int qmp_pcie_probe(struct platform_device *pdev)
3080 {
3081         struct device *dev = &pdev->dev;
3082         struct phy_provider *phy_provider;
3083         struct device_node *np;
3084         struct qmp_pcie *qmp;
3085         int ret;
3086
3087         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3088         if (!qmp)
3089                 return -ENOMEM;
3090
3091         qmp->dev = dev;
3092
3093         qmp->cfg = of_device_get_match_data(dev);
3094         if (!qmp->cfg)
3095                 return -EINVAL;
3096
3097         WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
3098         WARN_ON_ONCE(!qmp->cfg->phy_status);
3099
3100         ret = qmp_pcie_clk_init(qmp);
3101         if (ret)
3102                 return ret;
3103
3104         ret = qmp_pcie_reset_init(qmp);
3105         if (ret)
3106                 return ret;
3107
3108         ret = qmp_pcie_vreg_init(qmp);
3109         if (ret)
3110                 return ret;
3111
3112         /* Check for legacy binding with child node. */
3113         np = of_get_next_available_child(dev->of_node, NULL);
3114         if (np) {
3115                 ret = qmp_pcie_parse_dt_legacy(qmp, np);
3116         } else {
3117                 np = of_node_get(dev->of_node);
3118                 ret = qmp_pcie_parse_dt(qmp);
3119         }
3120         if (ret)
3121                 goto err_node_put;
3122
3123         ret = phy_pipe_clk_register(qmp, np);
3124         if (ret)
3125                 goto err_node_put;
3126
3127         qmp->mode = PHY_MODE_PCIE_RC;
3128
3129         qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
3130         if (IS_ERR(qmp->phy)) {
3131                 ret = PTR_ERR(qmp->phy);
3132                 dev_err(dev, "failed to create PHY: %d\n", ret);
3133                 goto err_node_put;
3134         }
3135
3136         phy_set_drvdata(qmp->phy, qmp);
3137
3138         of_node_put(np);
3139
3140         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3141
3142         return PTR_ERR_OR_ZERO(phy_provider);
3143
3144 err_node_put:
3145         of_node_put(np);
3146         return ret;
3147 }
3148
3149 static const struct of_device_id qmp_pcie_of_match_table[] = {
3150         {
3151                 .compatible = "qcom,ipq6018-qmp-pcie-phy",
3152                 .data = &ipq6018_pciephy_cfg,
3153         }, {
3154                 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
3155                 .data = &ipq8074_pciephy_gen3_cfg,
3156         }, {
3157                 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3158                 .data = &ipq8074_pciephy_cfg,
3159         }, {
3160                 .compatible = "qcom,msm8998-qmp-pcie-phy",
3161                 .data = &msm8998_pciephy_cfg,
3162         }, {
3163                 .compatible = "qcom,sc8180x-qmp-pcie-phy",
3164                 .data = &sc8180x_pciephy_cfg,
3165         }, {
3166                 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
3167                 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
3168         }, {
3169                 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
3170                 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
3171         }, {
3172                 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
3173                 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
3174         }, {
3175                 .compatible = "qcom,sdm845-qhp-pcie-phy",
3176                 .data = &sdm845_qhp_pciephy_cfg,
3177         }, {
3178                 .compatible = "qcom,sdm845-qmp-pcie-phy",
3179                 .data = &sdm845_qmp_pciephy_cfg,
3180         }, {
3181                 .compatible = "qcom,sdx55-qmp-pcie-phy",
3182                 .data = &sdx55_qmp_pciephy_cfg,
3183         }, {
3184                 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3185                 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
3186         }, {
3187                 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
3188                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3189         }, {
3190                 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3191                 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3192         }, {
3193                 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3194                 .data = &sm8350_qmp_gen3x1_pciephy_cfg,
3195         }, {
3196                 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3197                 .data = &sm8350_qmp_gen3x2_pciephy_cfg,
3198         }, {
3199                 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3200                 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
3201         }, {
3202                 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3203                 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
3204         }, {
3205                 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3206                 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
3207         }, {
3208                 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3209                 .data = &sm8550_qmp_gen4x2_pciephy_cfg,
3210         },
3211         { },
3212 };
3213 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
3214
3215 static struct platform_driver qmp_pcie_driver = {
3216         .probe          = qmp_pcie_probe,
3217         .driver = {
3218                 .name   = "qcom-qmp-pcie-phy",
3219                 .of_match_table = qmp_pcie_of_match_table,
3220         },
3221 };
3222
3223 module_platform_driver(qmp_pcie_driver);
3224
3225 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3226 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
3227 MODULE_LICENSE("GPL v2");