drivers/phy/qualcomm/phy-qcom-qmp-combo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy-qcom-qmp.h>
  24
  25 #include "phy-qcom-qmp.h"
  26 #include "phy-qcom-qmp-pcs-misc-v3.h"
  27 #include "phy-qcom-qmp-pcs-usb-v4.h"
  28 #include "phy-qcom-qmp-pcs-usb-v5.h"
  29 #include "phy-qcom-qmp-pcs-usb-v6.h"
  30
  31 /* QPHY_SW_RESET bit */
  32 #define SW_RESET                                BIT(0)
  33 /* QPHY_POWER_DOWN_CONTROL */
  34 #define SW_PWRDN                                BIT(0)
  35 /* QPHY_START_CONTROL bits */
  36 #define SERDES_START                            BIT(0)
  37 #define PCS_START                               BIT(1)
  38 /* QPHY_PCS_STATUS bit */
  39 #define PHYSTATUS                               BIT(6)
  40
  41 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  42 /* DP PHY soft reset */
  43 #define SW_DPPHY_RESET                          BIT(0)
  44 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  45 #define SW_DPPHY_RESET_MUX                      BIT(1)
  46 /* USB3 PHY soft reset */
  47 #define SW_USB3PHY_RESET                        BIT(2)
  48 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  50
  51 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  52 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  53 #define DP_MODE                                 BIT(1) /* enables DP mode */
  54
  55 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  56 #define ARCVR_DTCT_EN                           BIT(0)
  57 #define ALFPS_DTCT_EN                           BIT(1)
  58 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  59
  60 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  61 #define IRQ_CLEAR                               BIT(0)
  62
  63 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  64 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  65
  66 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  67
  68 struct qmp_phy_init_tbl {
  69         unsigned int offset;
  70         unsigned int val;
  71         /*
  72          * mask of lanes for which this register is written
  73          * for cases when second lane needs different values
  74          */
  75         u8 lane_mask;
  76 };
  77
  78 #define QMP_PHY_INIT_CFG(o, v)          \
  79         {                               \
  80                 .offset = o,            \
  81                 .val = v,               \
  82                 .lane_mask = 0xff,      \
  83         }
  84
  85 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  86         {                               \
  87                 .offset = o,            \
  88                 .val = v,               \
  89                 .lane_mask = l,         \
  90         }
  91
  92 /* set of registers with offsets different per-PHY */
  93 enum qphy_reg_layout {
  94         /* PCS registers */
  95         QPHY_SW_RESET,
  96         QPHY_START_CTRL,
  97         QPHY_PCS_STATUS,
  98         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
  99         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 100         QPHY_PCS_POWER_DOWN_CONTROL,
 101         /* Keep last to ensure regs_layout arrays are properly initialized */
 102         QPHY_LAYOUT_SIZE
 103 };
 104
 105 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 106         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 107         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 108         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 109         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 110         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 111         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 112 };
 113
 114 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 115         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 116         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 117         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 118         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 119
 120         /* In PCS_USB */
 121         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 122         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 123 };
 124
 125 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 126         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 127         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 128         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 129         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 130         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 131         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 132         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 133         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 139         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 140         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 141         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 149         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 150         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 151         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 157         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 159         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 160         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 161         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 162 };
 163
 164 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 165         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 166         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 167         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 168         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 169         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 170 };
 171
 172 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
 173         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 174         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
 175         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 176         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
 177         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 178         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 179         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
 180         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
 181         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 182         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 183         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 184         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 185         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 186         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 187         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 188         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
 189         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
 190         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 191         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 192         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 193         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 194 };
 195
 196 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
 197         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
 198         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 199         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 200         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 201         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
 202         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
 203         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 204 };
 205
 206 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
 207         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
 208         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 209         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 210         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 211         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
 212         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
 213         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 214 };
 215
 216 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
 217         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 218         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
 219         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
 220         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
 221         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
 222         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
 223         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 224 };
 225
 226 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
 227         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
 228         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 229         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 230         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 231         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
 232         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
 233         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
 234 };
 235
 236 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
 237         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 238         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
 239         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 240         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
 241         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
 242         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
 243         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
 244         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 245         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
 246         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
 247         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 252 };
 253
 254 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 255         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 260         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 261         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 262         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 263         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 264 };
 265
 266 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 267         /* FLL settings */
 268         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 269         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 270         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 271         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 272         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 273
 274         /* Lock Det settings */
 275         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 276         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 277         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 278         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 279
 280         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 281         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 282         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 283         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 284         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 285         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 287         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 296         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 299
 300         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 306         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 307         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 309         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 310         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 311 };
 312
 313 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
 314         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 315         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 316         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 317         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 318         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 319         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 320         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 321         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 322         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 323         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 324 };
 325
 326 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
 327         /* FLL settings */
 328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 332         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 333
 334         /* Lock Det settings */
 335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 339
 340         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
 341         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 342         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 343         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 344         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 345         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 346         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 347         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 348         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 349         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 350         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 351         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 352         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 353         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 354         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 355         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 356         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 357         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 358         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 359
 360         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 361         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 362         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 363         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 364         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 365         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 366         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 367         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 368         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 369         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 370         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 371         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
 372
 373         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 374         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 375 };
 376
 377 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 378         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 379         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 380         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 381         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 382         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 383         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 384         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 385         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 386         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 387         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 388         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 389         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 390         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 391         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 392         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 393         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 394         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 395         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 396         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 397         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 398         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 399         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 400         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 401         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 402         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 403         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 404         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 405         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 406         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 407         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 408         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 409         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 410         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 411         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 412         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 413         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 414         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 415         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 416         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 417         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 418 };
 419
 420 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
 421         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
 422         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
 423         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 424         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 425         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 426 };
 427
 428 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
 429         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 430         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 431         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 432         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 433         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 434         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 435         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 436         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 437         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 438         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 439         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 440         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
 441         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 442         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 443         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 444         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 445         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 446         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 447         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 448         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 449         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
 450         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
 451         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
 452         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 453         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
 454         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 455         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 456         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 457         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 458         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 459         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 460         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 461         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 462         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 463         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 464         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 465 };
 466
 467 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
 468         /* Lock Det settings */
 469         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 470         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 471         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 472
 473         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 474         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 475         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 476         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 477         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 478         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 479         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 480         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 481 };
 482
 483 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
 484         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 485         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 486 };
 487
 488 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
 489         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
 490         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
 491         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 492         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 493         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 494         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 495         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
 496         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
 497 };
 498
 499 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
 500         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 503         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 504         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 505         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 506         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 507         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 508         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 511         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 516         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 517         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 518         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 520         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
 521         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
 522         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
 523         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 526         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
 527         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 528         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 529         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 530         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 531         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 538 };
 539
 540 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
 541         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 542         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 543         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 544         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 545         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 546         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 547         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 548         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 549         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 550         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 551         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 552         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 553 };
 554
 555 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
 556         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 557         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 558 };
 559
 560 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
 561         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
 562         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
 563         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
 564         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 565         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
 566         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 567         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
 568         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
 569         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
 570         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 571 };
 572
 573 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
 574         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 575         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 576         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 577         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 578         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 579         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 580         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 581         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 582         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 583         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 584         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 585         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 586         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 587         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 588         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 589         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 590         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 591         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 592         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 593         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 594         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 595         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
 596         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
 597         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
 598         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
 599         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
 600         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 601         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 602         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 603         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
 604         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
 605         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 606         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
 607         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 608         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 609         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 610         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 611         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
 612 };
 613
 614 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
 615         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 616         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 617         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 618         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 619         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 620         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 621         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 622         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 623         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 624         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 625         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 626         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 627         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 628         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 629 };
 630
 631 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
 632         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 633         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 634         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 635         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 636 };
 637
 638 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
 639         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
 640         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
 641         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
 642         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
 643         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
 644         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
 645         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
 646         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
 647         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
 648         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
 649         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
 650         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
 651         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
 652         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 653         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
 654         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
 655         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
 656         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
 657         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
 658         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
 659         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
 660         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
 661         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
 662         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 663         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 664         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
 665         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
 666         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 667         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
 668         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
 669         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
 670         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
 671         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
 672         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
 673         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 674         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
 675         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
 676         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
 677         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
 678         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
 679         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
 680         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 681         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
 682         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 683         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
 684         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
 685         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
 686         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
 687 };
 688
 689 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
 690         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
 691         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
 692         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 693         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 694         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
 695         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
 696         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
 697         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
 698         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
 699         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
 700         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
 701 };
 702
 703 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
 704         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
 705         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
 706         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 707         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 708         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 709         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 710         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
 711         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
 712         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
 713         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
 714         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
 715         QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 716         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
 717         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
 718         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
 719         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 720         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 721         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 722         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
 723         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 724         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 725         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
 726         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 727         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
 728         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
 729         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
 730         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
 731         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
 732         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
 733         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 734         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
 735         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
 736         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
 737         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
 738
 739         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
 740         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
 741         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
 742         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
 743         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
 744
 745         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
 746         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
 747         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
 748         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
 749         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
 750 };
 751
 752 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
 753         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
 754         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
 755         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
 756         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
 757         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
 758         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),
 759         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 760         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 761         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),
 762         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 763         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 764         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
 765         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
 766         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
 767         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
 768 };
 769
 770 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
 771         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 772         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 773         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 774         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 775 };
 776
 777 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
 778         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 779         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 780         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 781         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 782         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 783         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 784         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 785         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 786         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 787         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 789         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 790         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 791         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
 792         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 798 };
 799
 800 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
 801         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
 802         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 803         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 804         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
 806         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
 807         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 808 };
 809
 810 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
 811         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 815         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
 816         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
 817         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 818 };
 819
 820 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
 821         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 822         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
 823         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
 824         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
 825         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
 826         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
 827         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 828 };
 829
 830 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
 831         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
 832         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 833         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 834         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 835         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
 836         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
 837         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 838 };
 839
 840 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
 841         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
 842         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 843         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
 844         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
 845         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
 846         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
 847         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 848         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
 849         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 850         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 851         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
 852         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
 853         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
 854         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
 855 };
 856
 857 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
 858         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 859         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 860         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 861         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 862         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 863         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 864         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 865         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 866         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 867         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 868         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 869         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 870         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 871         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 872         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 873         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 874         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 875         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 876         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 877         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 878         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 879         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 880         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 881 };
 882
 883 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
 884         QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
 885         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 886         QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
 887         QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
 888         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
 889         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
 890         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 891         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
 892         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 893         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 894         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
 895 };
 896
 897 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
 898         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
 899         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 900         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
 901         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
 902         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
 903         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
 904         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
 905         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
 906         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 907         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 908         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 909         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
 910 };
 911
 912 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
 913         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
 914         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
 915         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
 916         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
 917         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
 918         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
 919         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 920         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 921         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 922         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
 923         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
 924         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
 925         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 926         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 927         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
 928         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 929         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
 930         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
 931         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
 932         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
 933 };
 934
 935 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
 936         QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
 937         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 938         QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
 939         QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
 940         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
 941         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
 942         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 943         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
 944         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
 945         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
 946         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
 947 };
 948
 949 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
 950         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
 951         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 952         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 953         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 954         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
 955         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
 956         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
 957         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
 958         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
 959 };
 960
 961 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
 962         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
 963         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 964         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 965         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 966         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
 967         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
 968         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
 969         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
 970         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
 971 };
 972
 973 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
 974         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 975         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
 976         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
 977         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
 978         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
 979         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
 980         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
 981         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
 982         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
 983 };
 984
 985 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
 986         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
 987         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 988         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 989         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 990         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
 991         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
 992         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
 993         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
 994         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
 995 };
 996
 997 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
 998         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
 999         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1000         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1001         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1002         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1003         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1004         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1005         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1006         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1007         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1008         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1009         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1010         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1011         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1012         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1013         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1014         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1015         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1016         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1017         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1018         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1019         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1020         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1021         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1022         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1023         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1024         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1025         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1026         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1027         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1028         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1029         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1030         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1031         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1032         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1033         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1034         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1035         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1036         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1037         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1038         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1039         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1040         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1041         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1042         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1044         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1045 };
1046
1047 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1048         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1049         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1050         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1051         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1052         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1053 };
1054
1055 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1056         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1057         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1058         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1059         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1060         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1061         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1062         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1063         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1064         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1068         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1069         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1070         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1071         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1072         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1073         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1074         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1075         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1076         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1083         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1084         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1085         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1086         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1090 };
1091
1092 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1093         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1094         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1095         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1096         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1097         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1098         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1099         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1100         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1101         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1102         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1103         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1104         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1105         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1106         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1107         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1108         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1109 };
1110
1111 /* list of regulators */
1112 struct qmp_regulator_data {
1113         const char *name;
1114         unsigned int enable_load;
1115 };
1116
1117 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1118         { .name = "vdda-phy", .enable_load = 21800 },
1119         { .name = "vdda-pll", .enable_load = 36000 },
1120 };
1121
1122 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1123         { 0x00, 0x0c, 0x15, 0x1a },
1124         { 0x02, 0x0e, 0x16, 0xff },
1125         { 0x02, 0x11, 0xff, 0xff },
1126         { 0x04, 0xff, 0xff, 0xff }
1127 };
1128
1129 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1130         { 0x02, 0x12, 0x16, 0x1a },
1131         { 0x09, 0x19, 0x1f, 0xff },
1132         { 0x10, 0x1f, 0xff, 0xff },
1133         { 0x1f, 0xff, 0xff, 0xff }
1134 };
1135
1136 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1137         { 0x00, 0x0c, 0x14, 0x19 },
1138         { 0x00, 0x0b, 0x12, 0xff },
1139         { 0x00, 0x0b, 0xff, 0xff },
1140         { 0x04, 0xff, 0xff, 0xff }
1141 };
1142
1143 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1144         { 0x08, 0x0f, 0x16, 0x1f },
1145         { 0x11, 0x1e, 0x1f, 0xff },
1146         { 0x19, 0x1f, 0xff, 0xff },
1147         { 0x1f, 0xff, 0xff, 0xff }
1148 };
1149
1150 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1151         { 0x00, 0x0c, 0x15, 0x1b },
1152         { 0x02, 0x0e, 0x16, 0xff },
1153         { 0x02, 0x11, 0xff, 0xff },
1154         { 0x04, 0xff, 0xff, 0xff }
1155 };
1156
1157 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1158         { 0x00, 0x0d, 0x14, 0x1a },
1159         { 0x00, 0x0e, 0x15, 0xff },
1160         { 0x00, 0x0d, 0xff, 0xff },
1161         { 0x03, 0xff, 0xff, 0xff }
1162 };
1163
1164 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1165         { 0x08, 0x0f, 0x16, 0x1f },
1166         { 0x11, 0x1e, 0x1f, 0xff },
1167         { 0x16, 0x1f, 0xff, 0xff },
1168         { 0x1f, 0xff, 0xff, 0xff }
1169 };
1170
1171 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1172         { 0x20, 0x2c, 0x35, 0x3b },
1173         { 0x22, 0x2e, 0x36, 0xff },
1174         { 0x22, 0x31, 0xff, 0xff },
1175         { 0x24, 0xff, 0xff, 0xff }
1176 };
1177
1178 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1179         { 0x22, 0x32, 0x36, 0x3a },
1180         { 0x29, 0x39, 0x3f, 0xff },
1181         { 0x30, 0x3f, 0xff, 0xff },
1182         { 0x3f, 0xff, 0xff, 0xff }
1183 };
1184
1185 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1186         { 0x20, 0x2d, 0x34, 0x3a },
1187         { 0x20, 0x2e, 0x35, 0xff },
1188         { 0x20, 0x2e, 0xff, 0xff },
1189         { 0x24, 0xff, 0xff, 0xff }
1190 };
1191
1192 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1193         { 0x28, 0x2f, 0x36, 0x3f },
1194         { 0x31, 0x3e, 0x3f, 0xff },
1195         { 0x36, 0x3f, 0xff, 0xff },
1196         { 0x3f, 0xff, 0xff, 0xff }
1197 };
1198
1199 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1200         { 0x20, 0x2d, 0x34, 0x3a },
1201         { 0x20, 0x2e, 0x35, 0xff },
1202         { 0x20, 0x2e, 0xff, 0xff },
1203         { 0x22, 0xff, 0xff, 0xff }
1204 };
1205
1206 struct qmp_combo;
1207
1208 struct qmp_combo_offsets {
1209         u16 com;
1210         u16 txa;
1211         u16 rxa;
1212         u16 txb;
1213         u16 rxb;
1214         u16 usb3_serdes;
1215         u16 usb3_pcs_misc;
1216         u16 usb3_pcs;
1217         u16 usb3_pcs_usb;
1218         u16 dp_serdes;
1219         u16 dp_txa;
1220         u16 dp_txb;
1221         u16 dp_dp_phy;
1222 };
1223
1224 struct qmp_phy_cfg {
1225         const struct qmp_combo_offsets *offsets;
1226
1227         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1228         const struct qmp_phy_init_tbl *serdes_tbl;
1229         int serdes_tbl_num;
1230         const struct qmp_phy_init_tbl *tx_tbl;
1231         int tx_tbl_num;
1232         const struct qmp_phy_init_tbl *rx_tbl;
1233         int rx_tbl_num;
1234         const struct qmp_phy_init_tbl *pcs_tbl;
1235         int pcs_tbl_num;
1236         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1237         int pcs_usb_tbl_num;
1238
1239         const struct qmp_phy_init_tbl *dp_serdes_tbl;
1240         int dp_serdes_tbl_num;
1241         const struct qmp_phy_init_tbl *dp_tx_tbl;
1242         int dp_tx_tbl_num;
1243
1244         /* Init sequence for DP PHY block link rates */
1245         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1246         int serdes_tbl_rbr_num;
1247         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1248         int serdes_tbl_hbr_num;
1249         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1250         int serdes_tbl_hbr2_num;
1251         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1252         int serdes_tbl_hbr3_num;
1253
1254         /* DP PHY swing and pre_emphasis tables */
1255         const u8 (*swing_hbr_rbr)[4][4];
1256         const u8 (*swing_hbr3_hbr2)[4][4];
1257         const u8 (*pre_emphasis_hbr_rbr)[4][4];
1258         const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1259
1260         /* DP PHY callbacks */
1261         int (*configure_dp_phy)(struct qmp_combo *qmp);
1262         void (*configure_dp_tx)(struct qmp_combo *qmp);
1263         int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1264         void (*dp_aux_init)(struct qmp_combo *qmp);
1265
1266         /* clock ids to be requested */
1267         const char * const *clk_list;
1268         int num_clks;
1269         /* resets to be requested */
1270         const char * const *reset_list;
1271         int num_resets;
1272         /* regulators to be requested */
1273         const struct qmp_regulator_data *vreg_list;
1274         int num_vregs;
1275
1276         /* array of registers with different offsets */
1277         const unsigned int *regs;
1278
1279         /* true, if PHY needs delay after POWER_DOWN */
1280         bool has_pwrdn_delay;
1281
1282         /* Offset from PCS to PCS_USB region */
1283         unsigned int pcs_usb_offset;
1284
1285 };
1286
1287 struct qmp_combo {
1288         struct device *dev;
1289
1290         const struct qmp_phy_cfg *cfg;
1291
1292         void __iomem *com;
1293
1294         void __iomem *serdes;
1295         void __iomem *tx;
1296         void __iomem *rx;
1297         void __iomem *pcs;
1298         void __iomem *tx2;
1299         void __iomem *rx2;
1300         void __iomem *pcs_misc;
1301         void __iomem *pcs_usb;
1302
1303         void __iomem *dp_serdes;
1304         void __iomem *dp_tx;
1305         void __iomem *dp_tx2;
1306         void __iomem *dp_dp_phy;
1307
1308         struct clk *pipe_clk;
1309         struct clk_bulk_data *clks;
1310         struct reset_control_bulk_data *resets;
1311         struct regulator_bulk_data *vregs;
1312
1313         struct mutex phy_mutex;
1314         int init_count;
1315
1316         struct phy *usb_phy;
1317         enum phy_mode mode;
1318
1319         struct phy *dp_phy;
1320         unsigned int dp_aux_cfg;
1321         struct phy_configure_opts_dp dp_opts;
1322
1323         struct clk_fixed_rate pipe_clk_fixed;
1324         struct clk_hw dp_link_hw;
1325         struct clk_hw dp_pixel_hw;
1326 };
1327
1328 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1329 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1330 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1331 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1332
1333 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1334 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1335 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1336 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1337
1338 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);
1339
1340 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp);
1341 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp);
1342
1343 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1344 {
1345         u32 reg;
1346
1347         reg = readl(base + offset);
1348         reg |= val;
1349         writel(reg, base + offset);
1350
1351         /* ensure that above write is through */
1352         readl(base + offset);
1353 }
1354
1355 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1356 {
1357         u32 reg;
1358
1359         reg = readl(base + offset);
1360         reg &= ~val;
1361         writel(reg, base + offset);
1362
1363         /* ensure that above write is through */
1364         readl(base + offset);
1365 }
1366
1367 /* list of clocks required by phy */
1368 static const char * const qmp_v3_phy_clk_l[] = {
1369         "aux", "cfg_ahb", "ref", "com_aux",
1370 };
1371
1372 static const char * const qmp_v4_phy_clk_l[] = {
1373         "aux", "ref", "com_aux",
1374 };
1375
1376 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
1377 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1378         "aux", "ref_clk_src", "com_aux"
1379 };
1380
1381 /* list of resets */
1382 static const char * const msm8996_usb3phy_reset_l[] = {
1383         "phy", "common",
1384 };
1385
1386 static const char * const sc7180_usb3phy_reset_l[] = {
1387         "phy",
1388 };
1389
1390 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1391         .com            = 0x0000,
1392         .txa            = 0x1200,
1393         .rxa            = 0x1400,
1394         .txb            = 0x1600,
1395         .rxb            = 0x1800,
1396         .usb3_serdes    = 0x1000,
1397         .usb3_pcs_misc  = 0x1a00,
1398         .usb3_pcs       = 0x1c00,
1399         .usb3_pcs_usb   = 0x1f00,
1400         .dp_serdes      = 0x2000,
1401         .dp_txa         = 0x2200,
1402         .dp_txb         = 0x2600,
1403         .dp_dp_phy      = 0x2a00,
1404 };
1405
1406 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1407         .com            = 0x0000,
1408         .txa            = 0x0400,
1409         .rxa            = 0x0600,
1410         .txb            = 0x0a00,
1411         .rxb            = 0x0c00,
1412         .usb3_serdes    = 0x1000,
1413         .usb3_pcs_misc  = 0x1200,
1414         .usb3_pcs       = 0x1400,
1415         .usb3_pcs_usb   = 0x1700,
1416         .dp_serdes      = 0x2000,
1417         .dp_dp_phy      = 0x2200,
1418 };
1419
1420 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
1421         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1422         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1423         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1424         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1425         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1426         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1427         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1428         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1429
1430         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1431         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1432         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1433         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1434
1435         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1436         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1437         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1438         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1439         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1440         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1441         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1442         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1443
1444         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1445         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1446         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1447         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1448
1449         .dp_aux_init            = qmp_v3_dp_aux_init,
1450         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1451         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1452         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1453
1454         .clk_list               = qmp_v3_phy_clk_l,
1455         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1456         .reset_list             = sc7180_usb3phy_reset_l,
1457         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1458         .vreg_list              = qmp_phy_vreg_l,
1459         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1460         .regs                   = qmp_v3_usb3phy_regs_layout,
1461
1462         .has_pwrdn_delay        = true,
1463 };
1464
1465 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
1466         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1467         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1468         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1469         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1470         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1471         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1472         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1473         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1474
1475         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1476         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1477         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1478         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1479
1480         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1481         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1482         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1483         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1484         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1485         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1486         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1487         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1488
1489         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1490         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1491         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1492         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1493
1494         .dp_aux_init            = qmp_v3_dp_aux_init,
1495         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1496         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1497         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1498
1499         .clk_list               = qmp_v3_phy_clk_l,
1500         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1501         .reset_list             = msm8996_usb3phy_reset_l,
1502         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1503         .vreg_list              = qmp_phy_vreg_l,
1504         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1505         .regs                   = qmp_v3_usb3phy_regs_layout,
1506
1507         .has_pwrdn_delay        = true,
1508 };
1509
1510 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
1511         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1512         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1513         .tx_tbl                 = sm8150_usb3_tx_tbl,
1514         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1515         .rx_tbl                 = sm8150_usb3_rx_tbl,
1516         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1517         .pcs_tbl                = sm8150_usb3_pcs_tbl,
1518         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1519         .pcs_usb_tbl            = sm8150_usb3_pcs_usb_tbl,
1520         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1521
1522         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1523         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1524         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1525         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1526
1527         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1528         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1529         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1530         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1531         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1532         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1533         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1534         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1535
1536         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1537         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1538         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1539         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1540
1541         .dp_aux_init            = qmp_v4_dp_aux_init,
1542         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1543         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1544         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1545
1546         .clk_list               = qmp_v4_phy_clk_l,
1547         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1548         .reset_list             = msm8996_usb3phy_reset_l,
1549         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1550         .vreg_list              = qmp_phy_vreg_l,
1551         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1552         .regs                   = qmp_v4_usb3phy_regs_layout,
1553         .pcs_usb_offset         = 0x300,
1554
1555         .has_pwrdn_delay        = true,
1556 };
1557
1558 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
1559         .offsets                = &qmp_combo_offsets_v5,
1560
1561         .serdes_tbl             = sc8280xp_usb43dp_serdes_tbl,
1562         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1563         .tx_tbl                 = sc8280xp_usb43dp_tx_tbl,
1564         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1565         .rx_tbl                 = sc8280xp_usb43dp_rx_tbl,
1566         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1567         .pcs_tbl                = sc8280xp_usb43dp_pcs_tbl,
1568         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
1569
1570         .dp_serdes_tbl          = qmp_v5_dp_serdes_tbl,
1571         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1572         .dp_tx_tbl              = qmp_v5_5nm_dp_tx_tbl,
1573         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
1574
1575         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1576         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1577         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1578         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1579         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1580         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1581         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1582         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1583
1584         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1585         .pre_emphasis_hbr_rbr   = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1586         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1587         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1588
1589         .dp_aux_init            = qmp_v4_dp_aux_init,
1590         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1591         .configure_dp_phy       = qmp_v5_configure_dp_phy,
1592         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1593
1594         .clk_list               = qmp_v4_phy_clk_l,
1595         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1596         .reset_list             = msm8996_usb3phy_reset_l,
1597         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1598         .vreg_list              = qmp_phy_vreg_l,
1599         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1600         .regs                   = qmp_v4_usb3phy_regs_layout,
1601 };
1602
1603 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1604         .offsets                = &qmp_combo_offsets_v3,
1605
1606         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1607         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1608         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1609         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1610         .rx_tbl                 = sm6350_usb3_rx_tbl,
1611         .rx_tbl_num             = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1612         .pcs_tbl                = sm6350_usb3_pcs_tbl,
1613         .pcs_tbl_num            = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1614
1615         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1616         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1617         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1618         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1619
1620         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1621         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1622         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1623         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1624         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1625         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1626         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1627         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1628
1629         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1630         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1631         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1632         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1633
1634         .dp_aux_init            = qmp_v3_dp_aux_init,
1635         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1636         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1637         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1638
1639         .clk_list               = qmp_v4_phy_clk_l,
1640         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1641         .reset_list             = msm8996_usb3phy_reset_l,
1642         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1643         .vreg_list              = qmp_phy_vreg_l,
1644         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1645         .regs                   = qmp_v3_usb3phy_regs_layout,
1646 };
1647
1648 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1649         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1650         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1651         .tx_tbl                 = sm8250_usb3_tx_tbl,
1652         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1653         .rx_tbl                 = sm8250_usb3_rx_tbl,
1654         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1655         .pcs_tbl                = sm8250_usb3_pcs_tbl,
1656         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1657         .pcs_usb_tbl            = sm8250_usb3_pcs_usb_tbl,
1658         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1659
1660         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1661         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1662         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1663         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1664
1665         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1666         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1667         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1668         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1669         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1670         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1671         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1672         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1673
1674         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1675         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1676         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1677         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1678
1679         .dp_aux_init            = qmp_v4_dp_aux_init,
1680         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1681         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1682         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1683
1684         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
1685         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1686         .reset_list             = msm8996_usb3phy_reset_l,
1687         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1688         .vreg_list              = qmp_phy_vreg_l,
1689         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1690         .regs                   = qmp_v4_usb3phy_regs_layout,
1691         .pcs_usb_offset         = 0x300,
1692
1693         .has_pwrdn_delay        = true,
1694 };
1695
1696 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1697         .offsets                = &qmp_combo_offsets_v3,
1698
1699         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1700         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1701         .tx_tbl                 = sm8350_usb3_tx_tbl,
1702         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1703         .rx_tbl                 = sm8350_usb3_rx_tbl,
1704         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1705         .pcs_tbl                = sm8350_usb3_pcs_tbl,
1706         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1707         .pcs_usb_tbl            = sm8350_usb3_pcs_usb_tbl,
1708         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1709
1710         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1711         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1712         .dp_tx_tbl              = qmp_v5_dp_tx_tbl,
1713         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1714
1715         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1716         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1717         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1718         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1719         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1720         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1721         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1722         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1723
1724         .swing_hbr_rbr          = &qmp_dp_v4_voltage_swing_hbr_rbr,
1725         .pre_emphasis_hbr_rbr   = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1726         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1727         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1728
1729         .dp_aux_init            = qmp_v4_dp_aux_init,
1730         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1731         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1732         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1733
1734         .clk_list               = qmp_v4_phy_clk_l,
1735         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1736         .reset_list             = msm8996_usb3phy_reset_l,
1737         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1738         .vreg_list              = qmp_phy_vreg_l,
1739         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1740         .regs                   = qmp_v4_usb3phy_regs_layout,
1741
1742         .has_pwrdn_delay        = true,
1743 };
1744
1745 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1746         .offsets                = &qmp_combo_offsets_v3,
1747
1748         .serdes_tbl             = sm8550_usb3_serdes_tbl,
1749         .serdes_tbl_num         = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1750         .tx_tbl                 = sm8550_usb3_tx_tbl,
1751         .tx_tbl_num             = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1752         .rx_tbl                 = sm8550_usb3_rx_tbl,
1753         .rx_tbl_num             = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1754         .pcs_tbl                = sm8550_usb3_pcs_tbl,
1755         .pcs_tbl_num            = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1756         .pcs_usb_tbl            = sm8550_usb3_pcs_usb_tbl,
1757         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1758
1759         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
1760         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1761         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
1762         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1763
1764         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
1765         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1766         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
1767         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1768         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
1769         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1770         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
1771         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1772
1773         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1774         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1775         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1776         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1777
1778         .dp_aux_init            = qmp_v6_dp_aux_init,
1779         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1780         .configure_dp_phy       = qmp_v6_configure_dp_phy,
1781         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1782
1783         .regs                   = qmp_v4_usb3phy_regs_layout,
1784         .clk_list               = qmp_v4_phy_clk_l,
1785         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1786         .reset_list             = msm8996_usb3phy_reset_l,
1787         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1788         .vreg_list              = qmp_phy_vreg_l,
1789         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1790 };
1791
1792 static void qmp_combo_configure_lane(void __iomem *base,
1793                                         const struct qmp_phy_init_tbl tbl[],
1794                                         int num,
1795                                         u8 lane_mask)
1796 {
1797         int i;
1798         const struct qmp_phy_init_tbl *t = tbl;
1799
1800         if (!t)
1801                 return;
1802
1803         for (i = 0; i < num; i++, t++) {
1804                 if (!(t->lane_mask & lane_mask))
1805                         continue;
1806
1807                 writel(t->val, base + t->offset);
1808         }
1809 }
1810
1811 static void qmp_combo_configure(void __iomem *base,
1812                                    const struct qmp_phy_init_tbl tbl[],
1813                                    int num)
1814 {
1815         qmp_combo_configure_lane(base, tbl, num, 0xff);
1816 }
1817
1818 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
1819 {
1820         const struct qmp_phy_cfg *cfg = qmp->cfg;
1821         void __iomem *serdes = qmp->dp_serdes;
1822         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1823
1824         qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
1825
1826         switch (dp_opts->link_rate) {
1827         case 1620:
1828                 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
1829                                 cfg->serdes_tbl_rbr_num);
1830                 break;
1831         case 2700:
1832                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
1833                                 cfg->serdes_tbl_hbr_num);
1834                 break;
1835         case 5400:
1836                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
1837                                 cfg->serdes_tbl_hbr2_num);
1838                 break;
1839         case 8100:
1840                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
1841                                 cfg->serdes_tbl_hbr3_num);
1842                 break;
1843         default:
1844                 /* Other link rates aren't supported */
1845                 return -EINVAL;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
1852 {
1853         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1854                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1855                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1856
1857         /* Turn on BIAS current for PHY/PLL */
1858         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
1859                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
1860                qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1861
1862         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1863
1864         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1865                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
1866                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
1867                DP_PHY_PD_CTL_DP_CLAMP_EN,
1868                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1869
1870         writel(QSERDES_V3_COM_BIAS_EN |
1871                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
1872                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
1873                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
1874                qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1875
1876         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1877         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1878         writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1879         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1880         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1881         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1882         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1883         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1884         writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1885         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
1886         qmp->dp_aux_cfg = 0;
1887
1888         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
1889                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
1890                PHY_AUX_REQ_ERR_MASK,
1891                qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
1892 }
1893
1894 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
1895                 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
1896 {
1897         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1898         const struct qmp_phy_cfg *cfg = qmp->cfg;
1899         unsigned int v_level = 0, p_level = 0;
1900         u8 voltage_swing_cfg, pre_emphasis_cfg;
1901         int i;
1902
1903         for (i = 0; i < dp_opts->lanes; i++) {
1904                 v_level = max(v_level, dp_opts->voltage[i]);
1905                 p_level = max(p_level, dp_opts->pre[i]);
1906         }
1907
1908         if (dp_opts->link_rate <= 2700) {
1909                 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
1910                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
1911         } else {
1912                 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
1913                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
1914         }
1915
1916         /* TODO: Move check to config check */
1917         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
1918                 return -EINVAL;
1919
1920         /* Enable MUX to use Cursor values from these registers */
1921         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
1922         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
1923
1924         writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg);
1925         writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg);
1926         writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg);
1927         writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg);
1928
1929         return 0;
1930 }
1931
1932 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
1933 {
1934         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1935         u32 bias_en, drvr_en;
1936
1937         if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL,
1938                                 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
1939                 return;
1940
1941         if (dp_opts->lanes == 1) {
1942                 bias_en = 0x3e;
1943                 drvr_en = 0x13;
1944         } else {
1945                 bias_en = 0x3f;
1946                 drvr_en = 0x10;
1947         }
1948
1949         writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
1950         writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
1951         writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
1952         writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
1953 }
1954
1955 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
1956 {
1957         u32 val;
1958         bool reverse = false;
1959
1960         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1961               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
1962
1963         /*
1964          * TODO: Assume orientation is CC1 for now and two lanes, need to
1965          * use type-c connector to understand orientation and lanes.
1966          *
1967          * Otherwise val changes to be like below if this code understood
1968          * the orientation of the type-c cable.
1969          *
1970          * if (lane_cnt == 4 || orientation == ORIENTATION_CC2)
1971          *      val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
1972          * if (lane_cnt == 4 || orientation == ORIENTATION_CC1)
1973          *      val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1974          * if (orientation == ORIENTATION_CC2)
1975          *      writel(0x4c, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_MODE);
1976          */
1977         val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1978         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1979
1980         writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
1981
1982         return reverse;
1983 }
1984
1985 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
1986 {
1987         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1988         u32 phy_vco_div, status;
1989         unsigned long pixel_freq;
1990
1991         qmp_combo_configure_dp_mode(qmp);
1992
1993         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
1994         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
1995
1996         switch (dp_opts->link_rate) {
1997         case 1620:
1998                 phy_vco_div = 0x1;
1999                 pixel_freq = 1620000000UL / 2;
2000                 break;
2001         case 2700:
2002                 phy_vco_div = 0x1;
2003                 pixel_freq = 2700000000UL / 2;
2004                 break;
2005         case 5400:
2006                 phy_vco_div = 0x2;
2007                 pixel_freq = 5400000000UL / 4;
2008                 break;
2009         case 8100:
2010                 phy_vco_div = 0x0;
2011                 pixel_freq = 8100000000UL / 6;
2012                 break;
2013         default:
2014                 /* Other link rates aren't supported */
2015                 return -EINVAL;
2016         }
2017         writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV);
2018
2019         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2020         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2021
2022         writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2023         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2024         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2025         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2026         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2027
2028         writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);
2029
2030         if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS,
2031                         status,
2032                         ((status & BIT(0)) > 0),
2033                         500,
2034                         10000))
2035                 return -ETIMEDOUT;
2036
2037         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2038
2039         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
2040                         status,
2041                         ((status & BIT(1)) > 0),
2042                         500,
2043                         10000))
2044                 return -ETIMEDOUT;
2045
2046         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2047         udelay(2000);
2048         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2049
2050         return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
2051                         status,
2052                         ((status & BIT(1)) > 0),
2053                         500,
2054                         10000);
2055 }
2056
2057 /*
2058  * We need to calibrate the aux setting here as many times
2059  * as the caller tries
2060  */
2061 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2062 {
2063         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2064         u8 val;
2065
2066         qmp->dp_aux_cfg++;
2067         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2068         val = cfg1_settings[qmp->dp_aux_cfg];
2069
2070         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2071
2072         return 0;
2073 }
2074
2075 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2076 {
2077         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2078                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2079                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2080
2081         /* Turn on BIAS current for PHY/PLL */
2082         writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
2083
2084         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2085         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2086         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2087         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2088         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2089         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2090         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2091         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2092         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2093         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2094         qmp->dp_aux_cfg = 0;
2095
2096         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2097                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2098                PHY_AUX_REQ_ERR_MASK,
2099                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2100 }
2101
2102 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
2103 {
2104         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2105                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2106                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2107
2108         /* Turn on BIAS current for PHY/PLL */
2109         writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
2110
2111         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2112         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2113         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2114         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2115         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2116         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2117         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2118         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2119         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2120         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2121         qmp->dp_aux_cfg = 0;
2122
2123         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2124                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2125                PHY_AUX_REQ_ERR_MASK,
2126                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2127 }
2128
2129 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2130 {
2131         /* Program default values before writing proper values */
2132         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2133         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2134
2135         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2136         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2137
2138         qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL,
2139                         QSERDES_V4_TX_TX_EMP_POST1_LVL);
2140 }
2141
2142 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp,
2143                                      unsigned int com_resetm_ctrl_reg,
2144                                      unsigned int com_c_ready_status_reg,
2145                                      unsigned int dp_phy_status_reg)
2146 {
2147         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2148         u32 phy_vco_div, status;
2149         unsigned long pixel_freq;
2150
2151         writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
2152
2153         qmp_combo_configure_dp_mode(qmp);
2154
2155         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2156         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2157
2158         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2159         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2160
2161         switch (dp_opts->link_rate) {
2162         case 1620:
2163                 phy_vco_div = 0x1;
2164                 pixel_freq = 1620000000UL / 2;
2165                 break;
2166         case 2700:
2167                 phy_vco_div = 0x1;
2168                 pixel_freq = 2700000000UL / 2;
2169                 break;
2170         case 5400:
2171                 phy_vco_div = 0x2;
2172                 pixel_freq = 5400000000UL / 4;
2173                 break;
2174         case 8100:
2175                 phy_vco_div = 0x0;
2176                 pixel_freq = 8100000000UL / 6;
2177                 break;
2178         default:
2179                 /* Other link rates aren't supported */
2180                 return -EINVAL;
2181         }
2182         writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
2183
2184         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2185         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2186
2187         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2188         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2189         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2190         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2191
2192         writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg);
2193
2194         if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg,
2195                         status,
2196                         ((status & BIT(0)) > 0),
2197                         500,
2198                         10000))
2199                 return -ETIMEDOUT;
2200
2201         if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS,
2202                         status,
2203                         ((status & BIT(0)) > 0),
2204                         500,
2205                         10000))
2206                 return -ETIMEDOUT;
2207
2208         if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V4_COM_CMN_STATUS,
2209                         status,
2210                         ((status & BIT(1)) > 0),
2211                         500,
2212                         10000))
2213                 return -ETIMEDOUT;
2214
2215         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2216
2217         if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2218                         status,
2219                         ((status & BIT(0)) > 0),
2220                         500,
2221                         10000))
2222                 return -ETIMEDOUT;
2223
2224         if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2225                         status,
2226                         ((status & BIT(1)) > 0),
2227                         500,
2228                         10000))
2229                 return -ETIMEDOUT;
2230
2231         return 0;
2232 }
2233
2234 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2235 {
2236         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2237         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2238         bool reverse = false;
2239         u32 status;
2240         int ret;
2241
2242         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2243                                         QSERDES_V4_COM_C_READY_STATUS,
2244                                         QSERDES_V4_DP_PHY_STATUS);
2245         if (ret < 0)
2246                 return ret;
2247
2248         /*
2249          * At least for 7nm DP PHY this has to be done after enabling link
2250          * clock.
2251          */
2252
2253         if (dp_opts->lanes == 1) {
2254                 bias0_en = reverse ? 0x3e : 0x15;
2255                 bias1_en = reverse ? 0x15 : 0x3e;
2256                 drvr0_en = reverse ? 0x13 : 0x10;
2257                 drvr1_en = reverse ? 0x10 : 0x13;
2258         } else if (dp_opts->lanes == 2) {
2259                 bias0_en = reverse ? 0x3f : 0x15;
2260                 bias1_en = reverse ? 0x15 : 0x3f;
2261                 drvr0_en = 0x10;
2262                 drvr1_en = 0x10;
2263         } else {
2264                 bias0_en = 0x3f;
2265                 bias1_en = 0x3f;
2266                 drvr0_en = 0x10;
2267                 drvr1_en = 0x10;
2268         }
2269
2270         writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2271         writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2272         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2273         writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2274
2275         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2276         udelay(2000);
2277         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2278
2279         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2280                         status,
2281                         ((status & BIT(1)) > 0),
2282                         500,
2283                         10000))
2284                 return -ETIMEDOUT;
2285
2286         writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2287         writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2288
2289         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2290         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2291
2292         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2293         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2294
2295         return 0;
2296 }
2297
2298 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp)
2299 {
2300         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2301         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2302         bool reverse = false;
2303         u32 status;
2304         int ret;
2305
2306         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2307                                         QSERDES_V4_COM_C_READY_STATUS,
2308                                         QSERDES_V4_DP_PHY_STATUS);
2309         if (ret < 0)
2310                 return ret;
2311
2312         if (dp_opts->lanes == 1) {
2313                 bias0_en = reverse ? 0x3e : 0x1a;
2314                 drvr0_en = reverse ? 0x13 : 0x10;
2315                 bias1_en = reverse ? 0x15 : 0x3e;
2316                 drvr1_en = reverse ? 0x10 : 0x13;
2317         } else if (dp_opts->lanes == 2) {
2318                 bias0_en = reverse ? 0x3f : 0x15;
2319                 drvr0_en = 0x10;
2320                 bias1_en = reverse ? 0x15 : 0x3f;
2321                 drvr1_en = 0x10;
2322         } else {
2323                 bias0_en = 0x3f;
2324                 bias1_en = 0x3f;
2325                 drvr0_en = 0x10;
2326                 drvr1_en = 0x10;
2327         }
2328
2329         writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
2330         writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
2331         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
2332         writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
2333
2334         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2335         udelay(2000);
2336         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2337
2338         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2339                         status,
2340                         ((status & BIT(1)) > 0),
2341                         500,
2342                         10000))
2343                 return -ETIMEDOUT;
2344
2345         writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV);
2346         writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);
2347
2348         writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2349         writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2350
2351         writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2352         writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2353
2354         return 0;
2355 }
2356
2357 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
2358 {
2359         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2360         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2361         bool reverse = false;
2362         u32 status;
2363         int ret;
2364
2365         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL,
2366                                         QSERDES_V6_COM_C_READY_STATUS,
2367                                         QSERDES_V6_DP_PHY_STATUS);
2368         if (ret < 0)
2369                 return ret;
2370
2371         if (dp_opts->lanes == 1) {
2372                 bias0_en = reverse ? 0x3e : 0x1a;
2373                 drvr0_en = reverse ? 0x13 : 0x10;
2374                 bias1_en = reverse ? 0x15 : 0x3e;
2375                 drvr1_en = reverse ? 0x10 : 0x13;
2376         } else if (dp_opts->lanes == 2) {
2377                 bias0_en = reverse ? 0x3f : 0x15;
2378                 drvr0_en = 0x10;
2379                 bias1_en = reverse ? 0x15 : 0x3f;
2380                 drvr1_en = 0x10;
2381         } else {
2382                 bias0_en = 0x3f;
2383                 bias1_en = 0x3f;
2384                 drvr0_en = 0x10;
2385                 drvr1_en = 0x10;
2386         }
2387
2388         writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2389         writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2390         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2391         writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2392
2393         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2394         udelay(2000);
2395         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2396
2397         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS,
2398                                status,
2399                                ((status & BIT(1)) > 0),
2400                                500,
2401                                10000))
2402                 return -ETIMEDOUT;
2403
2404         writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2405         writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2406
2407         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2408         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2409
2410         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2411         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2412
2413         return 0;
2414 }
2415
2416 /*
2417  * We need to calibrate the aux setting here as many times
2418  * as the caller tries
2419  */
2420 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2421 {
2422         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2423         u8 val;
2424
2425         qmp->dp_aux_cfg++;
2426         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2427         val = cfg1_settings[qmp->dp_aux_cfg];
2428
2429         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2430
2431         return 0;
2432 }
2433
2434 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2435 {
2436         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2437         struct qmp_combo *qmp = phy_get_drvdata(phy);
2438         const struct qmp_phy_cfg *cfg = qmp->cfg;
2439
2440         memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2441         if (qmp->dp_opts.set_voltages) {
2442                 cfg->configure_dp_tx(qmp);
2443                 qmp->dp_opts.set_voltages = 0;
2444         }
2445
2446         return 0;
2447 }
2448
2449 static int qmp_combo_dp_calibrate(struct phy *phy)
2450 {
2451         struct qmp_combo *qmp = phy_get_drvdata(phy);
2452         const struct qmp_phy_cfg *cfg = qmp->cfg;
2453
2454         if (cfg->calibrate_dp_phy)
2455                 return cfg->calibrate_dp_phy(qmp);
2456
2457         return 0;
2458 }
2459
2460 static int qmp_combo_com_init(struct qmp_combo *qmp)
2461 {
2462         const struct qmp_phy_cfg *cfg = qmp->cfg;
2463         void __iomem *com = qmp->com;
2464         int ret;
2465
2466         mutex_lock(&qmp->phy_mutex);
2467         if (qmp->init_count++) {
2468                 mutex_unlock(&qmp->phy_mutex);
2469                 return 0;
2470         }
2471
2472         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2473         if (ret) {
2474                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2475                 goto err_decrement_count;
2476         }
2477
2478         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2479         if (ret) {
2480                 dev_err(qmp->dev, "reset assert failed\n");
2481                 goto err_disable_regulators;
2482         }
2483
2484         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2485         if (ret) {
2486                 dev_err(qmp->dev, "reset deassert failed\n");
2487                 goto err_disable_regulators;
2488         }
2489
2490         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2491         if (ret)
2492                 goto err_assert_reset;
2493
2494         qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
2495
2496         /* override hardware control for reset of qmp phy */
2497         qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2498                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2499                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2500
2501         /* Default type-c orientation, i.e CC1 */
2502         qphy_setbits(com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2503
2504         qphy_setbits(com, QPHY_V3_DP_COM_PHY_MODE_CTRL, USB3_MODE | DP_MODE);
2505
2506         /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2507         qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2508                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2509                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2510
2511         qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2512         qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2513
2514         qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2515                         SW_PWRDN);
2516
2517         mutex_unlock(&qmp->phy_mutex);
2518
2519         return 0;
2520
2521 err_assert_reset:
2522         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2523 err_disable_regulators:
2524         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2525 err_decrement_count:
2526         qmp->init_count--;
2527         mutex_unlock(&qmp->phy_mutex);
2528
2529         return ret;
2530 }
2531
2532 static int qmp_combo_com_exit(struct qmp_combo *qmp)
2533 {
2534         const struct qmp_phy_cfg *cfg = qmp->cfg;
2535
2536         mutex_lock(&qmp->phy_mutex);
2537         if (--qmp->init_count) {
2538                 mutex_unlock(&qmp->phy_mutex);
2539                 return 0;
2540         }
2541
2542         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2543
2544         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2545
2546         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2547
2548         mutex_unlock(&qmp->phy_mutex);
2549
2550         return 0;
2551 }
2552
2553 static int qmp_combo_dp_init(struct phy *phy)
2554 {
2555         struct qmp_combo *qmp = phy_get_drvdata(phy);
2556         const struct qmp_phy_cfg *cfg = qmp->cfg;
2557         int ret;
2558
2559         ret = qmp_combo_com_init(qmp);
2560         if (ret)
2561                 return ret;
2562
2563         cfg->dp_aux_init(qmp);
2564
2565         return 0;
2566 }
2567
2568 static int qmp_combo_dp_exit(struct phy *phy)
2569 {
2570         struct qmp_combo *qmp = phy_get_drvdata(phy);
2571
2572         qmp_combo_com_exit(qmp);
2573
2574         return 0;
2575 }
2576
2577 static int qmp_combo_dp_power_on(struct phy *phy)
2578 {
2579         struct qmp_combo *qmp = phy_get_drvdata(phy);
2580         const struct qmp_phy_cfg *cfg = qmp->cfg;
2581         void __iomem *tx = qmp->dp_tx;
2582         void __iomem *tx2 = qmp->dp_tx2;
2583
2584         qmp_combo_dp_serdes_init(qmp);
2585
2586         qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2587         qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2588
2589         /* Configure special DP tx tunings */
2590         cfg->configure_dp_tx(qmp);
2591
2592         /* Configure link rate, swing, etc. */
2593         cfg->configure_dp_phy(qmp);
2594
2595         return 0;
2596 }
2597
2598 static int qmp_combo_dp_power_off(struct phy *phy)
2599 {
2600         struct qmp_combo *qmp = phy_get_drvdata(phy);
2601
2602         /* Assert DP PHY power down */
2603         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2604
2605         return 0;
2606 }
2607
2608 static int qmp_combo_usb_power_on(struct phy *phy)
2609 {
2610         struct qmp_combo *qmp = phy_get_drvdata(phy);
2611         const struct qmp_phy_cfg *cfg = qmp->cfg;
2612         void __iomem *serdes = qmp->serdes;
2613         void __iomem *tx = qmp->tx;
2614         void __iomem *rx = qmp->rx;
2615         void __iomem *tx2 = qmp->tx2;
2616         void __iomem *rx2 = qmp->rx2;
2617         void __iomem *pcs = qmp->pcs;
2618         void __iomem *status;
2619         unsigned int val;
2620         int ret;
2621
2622         qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2623
2624         ret = clk_prepare_enable(qmp->pipe_clk);
2625         if (ret) {
2626                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2627                 return ret;
2628         }
2629
2630         /* Tx, Rx, and PCS configurations */
2631         qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2632         qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2633
2634         qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2635         qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2636
2637         qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2638
2639         if (cfg->has_pwrdn_delay)
2640                 usleep_range(10, 20);
2641
2642         /* Pull PHY out of reset state */
2643         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2644
2645         /* start SerDes and Phy-Coding-Sublayer */
2646         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2647
2648         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2649         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2650                         PHY_INIT_COMPLETE_TIMEOUT);
2651         if (ret) {
2652                 dev_err(qmp->dev, "phy initialization timed-out\n");
2653                 goto err_disable_pipe_clk;
2654         }
2655
2656         return 0;
2657
2658 err_disable_pipe_clk:
2659         clk_disable_unprepare(qmp->pipe_clk);
2660
2661         return ret;
2662 }
2663
2664 static int qmp_combo_usb_power_off(struct phy *phy)
2665 {
2666         struct qmp_combo *qmp = phy_get_drvdata(phy);
2667         const struct qmp_phy_cfg *cfg = qmp->cfg;
2668
2669         clk_disable_unprepare(qmp->pipe_clk);
2670
2671         /* PHY reset */
2672         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2673
2674         /* stop SerDes and Phy-Coding-Sublayer */
2675         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2676                         SERDES_START | PCS_START);
2677
2678         /* Put PHY into POWER DOWN state: active low */
2679         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2680                         SW_PWRDN);
2681
2682         return 0;
2683 }
2684
2685 static int qmp_combo_usb_init(struct phy *phy)
2686 {
2687         struct qmp_combo *qmp = phy_get_drvdata(phy);
2688         int ret;
2689
2690         ret = qmp_combo_com_init(qmp);
2691         if (ret)
2692                 return ret;
2693
2694         ret = qmp_combo_usb_power_on(phy);
2695         if (ret)
2696                 qmp_combo_com_exit(qmp);
2697
2698         return ret;
2699 }
2700
2701 static int qmp_combo_usb_exit(struct phy *phy)
2702 {
2703         struct qmp_combo *qmp = phy_get_drvdata(phy);
2704         int ret;
2705
2706         ret = qmp_combo_usb_power_off(phy);
2707         if (ret)
2708                 return ret;
2709
2710         return qmp_combo_com_exit(qmp);
2711 }
2712
2713 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2714 {
2715         struct qmp_combo *qmp = phy_get_drvdata(phy);
2716
2717         qmp->mode = mode;
2718
2719         return 0;
2720 }
2721
2722 static const struct phy_ops qmp_combo_usb_phy_ops = {
2723         .init           = qmp_combo_usb_init,
2724         .exit           = qmp_combo_usb_exit,
2725         .set_mode       = qmp_combo_usb_set_mode,
2726         .owner          = THIS_MODULE,
2727 };
2728
2729 static const struct phy_ops qmp_combo_dp_phy_ops = {
2730         .init           = qmp_combo_dp_init,
2731         .configure      = qmp_combo_dp_configure,
2732         .power_on       = qmp_combo_dp_power_on,
2733         .calibrate      = qmp_combo_dp_calibrate,
2734         .power_off      = qmp_combo_dp_power_off,
2735         .exit           = qmp_combo_dp_exit,
2736         .owner          = THIS_MODULE,
2737 };
2738
2739 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
2740 {
2741         const struct qmp_phy_cfg *cfg = qmp->cfg;
2742         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2743         void __iomem *pcs_misc = qmp->pcs_misc;
2744         u32 intr_mask;
2745
2746         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2747             qmp->mode == PHY_MODE_USB_DEVICE_SS)
2748                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2749         else
2750                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2751
2752         /* Clear any pending interrupts status */
2753         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2754         /* Writing 1 followed by 0 clears the interrupt */
2755         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2756
2757         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2758                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2759
2760         /* Enable required PHY autonomous mode interrupts */
2761         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2762
2763         /* Enable i/o clamp_n for autonomous mode */
2764         if (pcs_misc)
2765                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2766 }
2767
2768 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
2769 {
2770         const struct qmp_phy_cfg *cfg = qmp->cfg;
2771         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2772         void __iomem *pcs_misc = qmp->pcs_misc;
2773
2774         /* Disable i/o clamp_n on resume for normal mode */
2775         if (pcs_misc)
2776                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2777
2778         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2779                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2780
2781         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2782         /* Writing 1 followed by 0 clears the interrupt */
2783         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2784 }
2785
2786 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
2787 {
2788         struct qmp_combo *qmp = dev_get_drvdata(dev);
2789         const struct qmp_phy_cfg *cfg = qmp->cfg;
2790
2791         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2792
2793         if (!qmp->init_count) {
2794                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2795                 return 0;
2796         }
2797
2798         qmp_combo_enable_autonomous_mode(qmp);
2799
2800         clk_disable_unprepare(qmp->pipe_clk);
2801         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2802
2803         return 0;
2804 }
2805
2806 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
2807 {
2808         struct qmp_combo *qmp = dev_get_drvdata(dev);
2809         const struct qmp_phy_cfg *cfg = qmp->cfg;
2810         int ret = 0;
2811
2812         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2813
2814         if (!qmp->init_count) {
2815                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2816                 return 0;
2817         }
2818
2819         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2820         if (ret)
2821                 return ret;
2822
2823         ret = clk_prepare_enable(qmp->pipe_clk);
2824         if (ret) {
2825                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2826                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2827                 return ret;
2828         }
2829
2830         qmp_combo_disable_autonomous_mode(qmp);
2831
2832         return 0;
2833 }
2834
2835 static const struct dev_pm_ops qmp_combo_pm_ops = {
2836         SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
2837                            qmp_combo_runtime_resume, NULL)
2838 };
2839
2840 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
2841 {
2842         const struct qmp_phy_cfg *cfg = qmp->cfg;
2843         struct device *dev = qmp->dev;
2844         int num = cfg->num_vregs;
2845         int ret, i;
2846
2847         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2848         if (!qmp->vregs)
2849                 return -ENOMEM;
2850
2851         for (i = 0; i < num; i++)
2852                 qmp->vregs[i].supply = cfg->vreg_list[i].name;
2853
2854         ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
2855         if (ret) {
2856                 dev_err(dev, "failed at devm_regulator_bulk_get\n");
2857                 return ret;
2858         }
2859
2860         for (i = 0; i < num; i++) {
2861                 ret = regulator_set_load(qmp->vregs[i].consumer,
2862                                         cfg->vreg_list[i].enable_load);
2863                 if (ret) {
2864                         dev_err(dev, "failed to set load at %s\n",
2865                                 qmp->vregs[i].supply);
2866                         return ret;
2867                 }
2868         }
2869
2870         return 0;
2871 }
2872
2873 static int qmp_combo_reset_init(struct qmp_combo *qmp)
2874 {
2875         const struct qmp_phy_cfg *cfg = qmp->cfg;
2876         struct device *dev = qmp->dev;
2877         int i;
2878         int ret;
2879
2880         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2881                                    sizeof(*qmp->resets), GFP_KERNEL);
2882         if (!qmp->resets)
2883                 return -ENOMEM;
2884
2885         for (i = 0; i < cfg->num_resets; i++)
2886                 qmp->resets[i].id = cfg->reset_list[i];
2887
2888         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2889         if (ret)
2890                 return dev_err_probe(dev, ret, "failed to get resets\n");
2891
2892         return 0;
2893 }
2894
2895 static int qmp_combo_clk_init(struct qmp_combo *qmp)
2896 {
2897         const struct qmp_phy_cfg *cfg = qmp->cfg;
2898         struct device *dev = qmp->dev;
2899         int num = cfg->num_clks;
2900         int i;
2901
2902         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2903         if (!qmp->clks)
2904                 return -ENOMEM;
2905
2906         for (i = 0; i < num; i++)
2907                 qmp->clks[i].id = cfg->clk_list[i];
2908
2909         return devm_clk_bulk_get(dev, num, qmp->clks);
2910 }
2911
2912 static void phy_clk_release_provider(void *res)
2913 {
2914         of_clk_del_provider(res);
2915 }
2916
2917 /*
2918  * Register a fixed rate pipe clock.
2919  *
2920  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2921  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2922  * by the PHY driver for its operations.
2923  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2924  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2925  * Below picture shows this relationship.
2926  *
2927  *         +---------------+
2928  *         |   PHY block   |<<---------------------------------------+
2929  *         |               |                                         |
2930  *         |   +-------+   |                   +-----+               |
2931  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2932  *    clk  |   +-------+   |                   +-----+
2933  *         +---------------+
2934  */
2935 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
2936 {
2937         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2938         struct clk_init_data init = { };
2939         char name[64];
2940
2941         snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
2942         init.name = name;
2943         init.ops = &clk_fixed_rate_ops;
2944
2945         /* controllers using QMP phys use 125MHz pipe clock interface */
2946         fixed->fixed_rate = 125000000;
2947         fixed->hw.init = &init;
2948
2949         return devm_clk_hw_register(qmp->dev, &fixed->hw);
2950 }
2951
2952 /*
2953  * Display Port PLL driver block diagram for branch clocks
2954  *
2955  *              +------------------------------+
2956  *              |         DP_VCO_CLK           |
2957  *              |                              |
2958  *              |    +-------------------+     |
2959  *              |    |   (DP PLL/VCO)    |     |
2960  *              |    +---------+---------+     |
2961  *              |              v               |
2962  *              |   +----------+-----------+   |
2963  *              |   | hsclk_divsel_clk_src |   |
2964  *              |   +----------+-----------+   |
2965  *              +------------------------------+
2966  *                              |
2967  *          +---------<---------v------------>----------+
2968  *          |                                           |
2969  * +--------v----------------+                          |
2970  * |    dp_phy_pll_link_clk  |                          |
2971  * |     link_clk            |                          |
2972  * +--------+----------------+                          |
2973  *          |                                           |
2974  *          |                                           |
2975  *          v                                           v
2976  * Input to DISPCC block                                |
2977  * for link clk, crypto clk                             |
2978  * and interface clock                                  |
2979  *                                                      |
2980  *                                                      |
2981  *      +--------<------------+-----------------+---<---+
2982  *      |                     |                 |
2983  * +----v---------+  +--------v-----+  +--------v------+
2984  * | vco_divided  |  | vco_divided  |  | vco_divided   |
2985  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
2986  * |              |  |              |  |               |
2987  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
2988  * +-------+------+  +-----+--------+  +--------+------+
2989  *         |                 |                  |
2990  *         v---->----------v-------------<------v
2991  *                         |
2992  *              +----------+-----------------+
2993  *              |   dp_phy_pll_vco_div_clk   |
2994  *              +---------+------------------+
2995  *                        |
2996  *                        v
2997  *              Input to DISPCC block
2998  *              for DP pixel clock
2999  *
3000  */
3001 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3002 {
3003         switch (req->rate) {
3004         case 1620000000UL / 2:
3005         case 2700000000UL / 2:
3006         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3007                 return 0;
3008         default:
3009                 return -EINVAL;
3010         }
3011 }
3012
3013 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3014 {
3015         const struct qmp_combo *qmp;
3016         const struct phy_configure_opts_dp *dp_opts;
3017
3018         qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3019         dp_opts = &qmp->dp_opts;
3020
3021         switch (dp_opts->link_rate) {
3022         case 1620:
3023                 return 1620000000UL / 2;
3024         case 2700:
3025                 return 2700000000UL / 2;
3026         case 5400:
3027                 return 5400000000UL / 4;
3028         case 8100:
3029                 return 8100000000UL / 6;
3030         default:
3031                 return 0;
3032         }
3033 }
3034
3035 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3036         .determine_rate = qmp_dp_pixel_clk_determine_rate,
3037         .recalc_rate    = qmp_dp_pixel_clk_recalc_rate,
3038 };
3039
3040 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3041 {
3042         switch (req->rate) {
3043         case 162000000:
3044         case 270000000:
3045         case 540000000:
3046         case 810000000:
3047                 return 0;
3048         default:
3049                 return -EINVAL;
3050         }
3051 }
3052
3053 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3054 {
3055         const struct qmp_combo *qmp;
3056         const struct phy_configure_opts_dp *dp_opts;
3057
3058         qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3059         dp_opts = &qmp->dp_opts;
3060
3061         switch (dp_opts->link_rate) {
3062         case 1620:
3063         case 2700:
3064         case 5400:
3065         case 8100:
3066                 return dp_opts->link_rate * 100000;
3067         default:
3068                 return 0;
3069         }
3070 }
3071
3072 static const struct clk_ops qmp_dp_link_clk_ops = {
3073         .determine_rate = qmp_dp_link_clk_determine_rate,
3074         .recalc_rate    = qmp_dp_link_clk_recalc_rate,
3075 };
3076
3077 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3078 {
3079         struct qmp_combo *qmp = data;
3080         unsigned int idx = clkspec->args[0];
3081
3082         if (idx >= 2) {
3083                 pr_err("%s: invalid index %u\n", __func__, idx);
3084                 return ERR_PTR(-EINVAL);
3085         }
3086
3087         if (idx == 0)
3088                 return &qmp->dp_link_hw;
3089
3090         return &qmp->dp_pixel_hw;
3091 }
3092
3093 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3094 {
3095         struct clk_init_data init = { };
3096         char name[64];
3097         int ret;
3098
3099         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3100         init.ops = &qmp_dp_link_clk_ops;
3101         init.name = name;
3102         qmp->dp_link_hw.init = &init;
3103         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3104         if (ret)
3105                 return ret;
3106
3107         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3108         init.ops = &qmp_dp_pixel_clk_ops;
3109         init.name = name;
3110         qmp->dp_pixel_hw.init = &init;
3111         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3112         if (ret)
3113                 return ret;
3114
3115         return 0;
3116 }
3117
3118 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3119 {
3120         struct qmp_combo *qmp = data;
3121
3122         switch (clkspec->args[0]) {
3123         case QMP_USB43DP_USB3_PIPE_CLK:
3124                 return &qmp->pipe_clk_fixed.hw;
3125         case QMP_USB43DP_DP_LINK_CLK:
3126                 return &qmp->dp_link_hw;
3127         case QMP_USB43DP_DP_VCO_DIV_CLK:
3128                 return &qmp->dp_pixel_hw;
3129         }
3130
3131         return ERR_PTR(-EINVAL);
3132 }
3133
3134 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3135                                         struct device_node *dp_np)
3136 {
3137         int ret;
3138
3139         ret = phy_pipe_clk_register(qmp, usb_np);
3140         if (ret)
3141                 return ret;
3142
3143         ret = phy_dp_clks_register(qmp, dp_np);
3144         if (ret)
3145                 return ret;
3146
3147         /*
3148          * Register a single provider for bindings without child nodes.
3149          */
3150         if (usb_np == qmp->dev->of_node)
3151                 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3152
3153         /*
3154          * Register multiple providers for legacy bindings with child nodes.
3155          */
3156         ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3157                                         &qmp->pipe_clk_fixed.hw);
3158         if (ret)
3159                 return ret;
3160
3161         /*
3162          * Roll a devm action because the clock provider is the child node, but
3163          * the child node is not actually a device.
3164          */
3165         ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3166         if (ret)
3167                 return ret;
3168
3169         ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3170         if (ret)
3171                 return ret;
3172
3173         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3174 }
3175
3176 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
3177 {
3178         struct device *dev = qmp->dev;
3179
3180         /*
3181          * Get memory resources from the DP child node:
3182          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3183          * tx2 -> 3; rx2 -> 4
3184          *
3185          * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3186          * implementation.
3187          */
3188         qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3189         if (IS_ERR(qmp->dp_tx))
3190                 return PTR_ERR(qmp->dp_tx);
3191
3192         qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3193         if (IS_ERR(qmp->dp_dp_phy))
3194                 return PTR_ERR(qmp->dp_dp_phy);
3195
3196         qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3197         if (IS_ERR(qmp->dp_tx2))
3198                 return PTR_ERR(qmp->dp_tx2);
3199
3200         return 0;
3201 }
3202
3203 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
3204 {
3205         const struct qmp_phy_cfg *cfg = qmp->cfg;
3206         struct device *dev = qmp->dev;
3207
3208         /*
3209          * Get memory resources from the USB child node:
3210          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3211          * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3212          */
3213         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3214         if (IS_ERR(qmp->tx))
3215                 return PTR_ERR(qmp->tx);
3216
3217         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3218         if (IS_ERR(qmp->rx))
3219                 return PTR_ERR(qmp->rx);
3220
3221         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3222         if (IS_ERR(qmp->pcs))
3223                 return PTR_ERR(qmp->pcs);
3224
3225         if (cfg->pcs_usb_offset)
3226                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3227
3228         qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3229         if (IS_ERR(qmp->tx2))
3230                 return PTR_ERR(qmp->tx2);
3231
3232         qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3233         if (IS_ERR(qmp->rx2))
3234                 return PTR_ERR(qmp->rx2);
3235
3236         qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3237         if (IS_ERR(qmp->pcs_misc)) {
3238                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3239                 qmp->pcs_misc = NULL;
3240         }
3241
3242         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3243         if (IS_ERR(qmp->pipe_clk)) {
3244                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3245                                      "failed to get pipe clock\n");
3246         }
3247
3248         return 0;
3249 }
3250
3251 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3252                                         struct device_node *dp_np)
3253 {
3254         struct platform_device *pdev = to_platform_device(qmp->dev);
3255         int ret;
3256
3257         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3258         if (IS_ERR(qmp->serdes))
3259                 return PTR_ERR(qmp->serdes);
3260
3261         qmp->com = devm_platform_ioremap_resource(pdev, 1);
3262         if (IS_ERR(qmp->com))
3263                 return PTR_ERR(qmp->com);
3264
3265         qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3266         if (IS_ERR(qmp->dp_serdes))
3267                 return PTR_ERR(qmp->dp_serdes);
3268
3269         ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np);
3270         if (ret)
3271                 return ret;
3272
3273         ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np);
3274         if (ret)
3275                 return ret;
3276
3277         return 0;
3278 }
3279
3280 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3281 {
3282         struct platform_device *pdev = to_platform_device(qmp->dev);
3283         const struct qmp_phy_cfg *cfg = qmp->cfg;
3284         const struct qmp_combo_offsets *offs = cfg->offsets;
3285         struct device *dev = qmp->dev;
3286         void __iomem *base;
3287
3288         if (!offs)
3289                 return -EINVAL;
3290
3291         base = devm_platform_ioremap_resource(pdev, 0);
3292         if (IS_ERR(base))
3293                 return PTR_ERR(base);
3294
3295         qmp->com = base + offs->com;
3296         qmp->tx = base + offs->txa;
3297         qmp->rx = base + offs->rxa;
3298         qmp->tx2 = base + offs->txb;
3299         qmp->rx2 = base + offs->rxb;
3300
3301         qmp->serdes = base + offs->usb3_serdes;
3302         qmp->pcs_misc = base + offs->usb3_pcs_misc;
3303         qmp->pcs = base + offs->usb3_pcs;
3304         qmp->pcs_usb = base + offs->usb3_pcs_usb;
3305
3306         qmp->dp_serdes = base + offs->dp_serdes;
3307         if (offs->dp_txa) {
3308                 qmp->dp_tx = base + offs->dp_txa;
3309                 qmp->dp_tx2 = base + offs->dp_txb;
3310         } else {
3311                 qmp->dp_tx = base + offs->txa;
3312                 qmp->dp_tx2 = base + offs->txb;
3313         }
3314         qmp->dp_dp_phy = base + offs->dp_dp_phy;
3315
3316         qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3317         if (IS_ERR(qmp->pipe_clk)) {
3318                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3319                                 "failed to get usb3_pipe clock\n");
3320         }
3321
3322         return 0;
3323 }
3324
3325 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args)
3326 {
3327         struct qmp_combo *qmp = dev_get_drvdata(dev);
3328
3329         if (args->args_count == 0)
3330                 return ERR_PTR(-EINVAL);
3331
3332         switch (args->args[0]) {
3333         case QMP_USB43DP_USB3_PHY:
3334                 return qmp->usb_phy;
3335         case QMP_USB43DP_DP_PHY:
3336                 return qmp->dp_phy;
3337         }
3338
3339         return ERR_PTR(-EINVAL);
3340 }
3341
3342 static int qmp_combo_probe(struct platform_device *pdev)
3343 {
3344         struct qmp_combo *qmp;
3345         struct device *dev = &pdev->dev;
3346         struct device_node *dp_np, *usb_np;
3347         struct phy_provider *phy_provider;
3348         int ret;
3349
3350         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3351         if (!qmp)
3352                 return -ENOMEM;
3353
3354         qmp->dev = dev;
3355
3356         qmp->cfg = of_device_get_match_data(dev);
3357         if (!qmp->cfg)
3358                 return -EINVAL;
3359
3360         mutex_init(&qmp->phy_mutex);
3361
3362         ret = qmp_combo_clk_init(qmp);
3363         if (ret)
3364                 return ret;
3365
3366         ret = qmp_combo_reset_init(qmp);
3367         if (ret)
3368                 return ret;
3369
3370         ret = qmp_combo_vreg_init(qmp);
3371         if (ret)
3372                 return ret;
3373
3374         /* Check for legacy binding with child nodes. */
3375         usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
3376         if (usb_np) {
3377                 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3378                 if (!dp_np) {
3379                         of_node_put(usb_np);
3380                         return -EINVAL;
3381                 }
3382
3383                 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3384         } else {
3385                 usb_np = of_node_get(dev->of_node);
3386                 dp_np = of_node_get(dev->of_node);
3387
3388                 ret = qmp_combo_parse_dt(qmp);
3389         }
3390         if (ret)
3391                 goto err_node_put;
3392
3393         pm_runtime_set_active(dev);
3394         ret = devm_pm_runtime_enable(dev);
3395         if (ret)
3396                 goto err_node_put;
3397         /*
3398          * Prevent runtime pm from being ON by default. Users can enable
3399          * it using power/control in sysfs.
3400          */
3401         pm_runtime_forbid(dev);
3402
3403         ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
3404         if (ret)
3405                 goto err_node_put;
3406
3407         qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3408         if (IS_ERR(qmp->usb_phy)) {
3409                 ret = PTR_ERR(qmp->usb_phy);
3410                 dev_err(dev, "failed to create USB PHY: %d\n", ret);
3411                 goto err_node_put;
3412         }
3413
3414         phy_set_drvdata(qmp->usb_phy, qmp);
3415
3416         qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3417         if (IS_ERR(qmp->dp_phy)) {
3418                 ret = PTR_ERR(qmp->dp_phy);
3419                 dev_err(dev, "failed to create DP PHY: %d\n", ret);
3420                 goto err_node_put;
3421         }
3422
3423         phy_set_drvdata(qmp->dp_phy, qmp);
3424
3425         dev_set_drvdata(dev, qmp);
3426
3427         if (usb_np == dev->of_node)
3428                 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3429         else
3430                 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3431
3432         of_node_put(usb_np);
3433         of_node_put(dp_np);
3434
3435         return PTR_ERR_OR_ZERO(phy_provider);
3436
3437 err_node_put:
3438         of_node_put(usb_np);
3439         of_node_put(dp_np);
3440         return ret;
3441 }
3442
3443 static const struct of_device_id qmp_combo_of_match_table[] = {
3444         {
3445                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3446                 .data = &sc7180_usb3dpphy_cfg,
3447         },
3448         {
3449                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3450                 .data = &sc8180x_usb3dpphy_cfg,
3451         },
3452         {
3453                 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3454                 .data = &sc8280xp_usb43dpphy_cfg,
3455         },
3456         {
3457                 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3458                 .data = &sdm845_usb3dpphy_cfg,
3459         },
3460         {
3461                 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3462                 .data = &sm6350_usb3dpphy_cfg,
3463         },
3464         {
3465                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3466                 .data = &sm8250_usb3dpphy_cfg,
3467         },
3468         {
3469                 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3470                 .data = &sm8350_usb3dpphy_cfg,
3471         },
3472         {
3473                 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3474                 .data = &sm8350_usb3dpphy_cfg,
3475         },
3476         {
3477                 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3478                 .data = &sm8550_usb3dpphy_cfg,
3479         },
3480         { }
3481 };
3482 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3483
3484 static struct platform_driver qmp_combo_driver = {
3485         .probe          = qmp_combo_probe,
3486         .driver = {
3487                 .name   = "qcom-qmp-combo-phy",
3488                 .pm     = &qmp_combo_pm_ops,
3489                 .of_match_table = qmp_combo_of_match_table,
3490         },
3491 };
3492
3493 module_platform_driver(qmp_combo_driver);
3494
3495 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3496 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
3497 MODULE_LICENSE("GPL v2");