drivers/phy/qualcomm/phy-qcom-qmp-combo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22 #include <linux/usb/typec.h>
  23 #include <linux/usb/typec_mux.h>
  24
  25 #include <drm/drm_bridge.h>
  26
  27 #include <dt-bindings/phy/phy-qcom-qmp.h>
  28
  29 #include "phy-qcom-qmp.h"
  30 #include "phy-qcom-qmp-pcs-misc-v3.h"
  31 #include "phy-qcom-qmp-pcs-usb-v4.h"
  32 #include "phy-qcom-qmp-pcs-usb-v5.h"
  33 #include "phy-qcom-qmp-pcs-usb-v6.h"
  34
  35 /* QPHY_SW_RESET bit */
  36 #define SW_RESET                                BIT(0)
  37 /* QPHY_POWER_DOWN_CONTROL */
  38 #define SW_PWRDN                                BIT(0)
  39 /* QPHY_START_CONTROL bits */
  40 #define SERDES_START                            BIT(0)
  41 #define PCS_START                               BIT(1)
  42 /* QPHY_PCS_STATUS bit */
  43 #define PHYSTATUS                               BIT(6)
  44
  45 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  46 /* DP PHY soft reset */
  47 #define SW_DPPHY_RESET                          BIT(0)
  48 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  49 #define SW_DPPHY_RESET_MUX                      BIT(1)
  50 /* USB3 PHY soft reset */
  51 #define SW_USB3PHY_RESET                        BIT(2)
  52 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  53 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  54
  55 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  56 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  57 #define DP_MODE                                 BIT(1) /* enables DP mode */
  58
  59 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  60 #define ARCVR_DTCT_EN                           BIT(0)
  61 #define ALFPS_DTCT_EN                           BIT(1)
  62 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  63
  64 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  65 #define IRQ_CLEAR                               BIT(0)
  66
  67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  68 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  69
  70 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
  71 #define SW_PORTSELECT_VAL                       BIT(0)
  72 #define SW_PORTSELECT_MUX                       BIT(1)
  73
  74 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  75
  76 struct qmp_phy_init_tbl {
  77         unsigned int offset;
  78         unsigned int val;
  79         /*
  80          * mask of lanes for which this register is written
  81          * for cases when second lane needs different values
  82          */
  83         u8 lane_mask;
  84 };
  85
  86 #define QMP_PHY_INIT_CFG(o, v)          \
  87         {                               \
  88                 .offset = o,            \
  89                 .val = v,               \
  90                 .lane_mask = 0xff,      \
  91         }
  92
  93 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
  94         {                               \
  95                 .offset = o,            \
  96                 .val = v,               \
  97                 .lane_mask = l,         \
  98         }
  99
 100 /* set of registers with offsets different per-PHY */
 101 enum qphy_reg_layout {
 102         /* PCS registers */
 103         QPHY_SW_RESET,
 104         QPHY_START_CTRL,
 105         QPHY_PCS_STATUS,
 106         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 107         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 108         QPHY_PCS_POWER_DOWN_CONTROL,
 109         /* Keep last to ensure regs_layout arrays are properly initialized */
 110         QPHY_LAYOUT_SIZE
 111 };
 112
 113 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 114         [QPHY_SW_RESET]                 = QPHY_V3_PCS_SW_RESET,
 115         [QPHY_START_CTRL]               = QPHY_V3_PCS_START_CONTROL,
 116         [QPHY_PCS_STATUS]               = QPHY_V3_PCS_PCS_STATUS,
 117         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V3_PCS_POWER_DOWN_CONTROL,
 118         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
 119         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
 120 };
 121
 122 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 123         [QPHY_SW_RESET]                 = QPHY_V4_PCS_SW_RESET,
 124         [QPHY_START_CTRL]               = QPHY_V4_PCS_START_CONTROL,
 125         [QPHY_PCS_STATUS]               = QPHY_V4_PCS_PCS_STATUS1,
 126         [QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V4_PCS_POWER_DOWN_CONTROL,
 127
 128         /* In PCS_USB */
 129         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
 130         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
 131 };
 132
 133 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 134         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 135         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 136         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 137         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 138         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 139         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 140         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 141         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 142         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 143         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 144         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 145         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 146         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 147         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 148         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 149         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 150         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 151         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 152         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 153         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 154         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 155         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 156         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 157         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 158         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 159         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 160         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 161         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 162         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 163         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 164         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 165         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 166         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 167         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 168         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 169         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 170 };
 171
 172 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 173         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 174         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 175         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 176         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 177         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 178 };
 179
 180 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
 181         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 182         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
 183         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 184         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
 185         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
 186         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 187         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
 188         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
 189         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 190         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 191         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 192         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 193         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 194         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 195         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
 196         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
 197         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
 198         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 199         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 200         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 201         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 202 };
 203
 204 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
 205         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
 206         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 207         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 208         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 209         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
 210         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
 211         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 212 };
 213
 214 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
 215         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
 216         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 217         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 218         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 219         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
 220         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
 221         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 222 };
 223
 224 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
 225         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
 226         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
 227         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
 228         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
 229         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
 230         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
 231         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
 232 };
 233
 234 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
 235         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
 236         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
 237         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
 238         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
 239         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
 240         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
 241         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
 242 };
 243
 244 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
 245         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 246         QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
 247         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 248         QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
 249         QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
 250         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
 251         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
 252         QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 253         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
 254         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
 255         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
 256         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
 257         QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
 258         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 259         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
 260 };
 261
 262 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 263         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 264         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 265         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 266         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 267         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 268         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 269         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 270         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 271         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 272 };
 273
 274 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 275         /* FLL settings */
 276         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 277         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 278         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 279         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 280         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 281
 282         /* Lock Det settings */
 283         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 284         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 285         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 286         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 287
 288         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 289         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 290         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 291         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 292         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 293         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 294         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 295         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 296         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 297         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 298         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 299         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 300         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 301         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 302         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 303         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 304         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 305         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 306         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 307
 308         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 309         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 310         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 311         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 312         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 313         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 314         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 315         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 316         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 317         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 319 };
 320
 321 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
 322         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 323         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 324         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 325         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 326         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 327         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 328         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 329         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 330         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 331         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 332 };
 333
 334 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
 335         /* FLL settings */
 336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 339         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 340         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 341
 342         /* Lock Det settings */
 343         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 344         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 345         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 346         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 347
 348         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
 349         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 350         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 351         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 352         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 353         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 354         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 355         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 356         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 357         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 358         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 359         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 360         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 361         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 362         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 363         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 364         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 365         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 366         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 367
 368         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 369         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 370         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 371         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 372         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 373         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 374         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 375         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 376         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 377         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 378         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 379         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
 380
 381         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 382         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 383 };
 384
 385 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 386         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 387         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 388         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 389         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 390         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 391         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 392         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 393         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 394         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 395         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 396         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 397         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 398         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 399         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 400         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 401         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 402         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 403         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 404         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 405         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 406         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 407         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 408         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 409         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 410         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 411         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 412         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 413         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 414         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 415         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 416         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 417         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 418         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 419         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 420         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 421         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 422         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 423         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 424         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 425         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 426 };
 427
 428 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
 429         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
 430         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
 431         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 432         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 433         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 434 };
 435
 436 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
 437         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 438         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 439         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 440         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 441         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 442         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 443         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 444         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 445         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 446         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 447         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 448         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
 449         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 450         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 451         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 452         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 453         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 454         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 455         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 456         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 457         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
 458         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
 459         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
 460         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 461         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
 462         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 463         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 464         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 465         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 466         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 467         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 468         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 469         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 470         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 471         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 472         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 473 };
 474
 475 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
 476         /* Lock Det settings */
 477         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 478         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 479         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 480
 481         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 482         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 483         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 484         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 485         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 486         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 487         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 488         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 489 };
 490
 491 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
 492         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 493         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 494 };
 495
 496 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
 497         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
 498         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
 499         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 500         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 501         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 502         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 503         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
 504         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
 505 };
 506
 507 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
 508         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 509         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 510         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 511         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 512         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 513         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 514         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 515         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 516         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 517         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 518         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 519         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 520         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 521         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 522         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 523         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 524         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 525         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 526         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 527         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 528         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
 529         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
 530         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
 531         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
 532         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
 533         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 534         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
 535         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 536         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 537         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 538         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 539         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 540         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 541         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 542         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 543         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 544         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 545         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 546 };
 547
 548 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
 549         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 550         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 551         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 552         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 553         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 554         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 555         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 556         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 557         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 558         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 559         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 560         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 561 };
 562
 563 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
 564         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 565         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 566 };
 567
 568 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
 569         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
 570         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
 571         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
 572         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
 573         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
 574         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
 575         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
 576         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
 577         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
 578         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
 579 };
 580
 581 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
 582         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
 583         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
 584         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 585         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 586         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 587         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 588         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
 589         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
 590         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
 591         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
 592         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
 593         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
 594         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
 595         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 596         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 597         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 598         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 599         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 600         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 601         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
 602         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 603         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
 604         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
 605         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
 606         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
 607         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
 608         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
 609         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
 610         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
 611         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
 612         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
 613         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
 614         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
 615         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 616         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 617         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
 618         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
 619         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
 620 };
 621
 622 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
 623         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 624         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 625         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 626         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 627         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 628         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 629         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 630         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 631         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 632         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 633         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 634         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 635         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 636         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 637 };
 638
 639 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
 640         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 641         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 642         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 643         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 644 };
 645
 646 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
 647         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
 648         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
 649         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
 650         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
 651         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
 652         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
 653         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
 654         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
 655         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
 656         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
 657         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
 658         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
 659         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
 660         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 661         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
 662         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
 663         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
 664         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
 665         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
 666         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
 667         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
 668         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
 669         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
 670         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 671         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 672         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
 673         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
 674         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
 675         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
 676         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
 677         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
 678         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
 679         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
 680         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
 681         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 682         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
 683         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
 684         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
 685         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
 686         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
 687         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
 688         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
 689         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
 690         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
 691         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
 692         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
 693         QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
 694         QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
 695 };
 696
 697 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
 698         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
 699         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
 700         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
 701         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 702         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
 703         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
 704         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
 705         QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
 706         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
 707         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
 708         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
 709 };
 710
 711 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
 712         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
 713         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
 714         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 715         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 716         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 717         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 718         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
 719         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
 720         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
 721         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
 722         QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
 723         QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 724         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
 725         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
 726         QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
 727         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 728         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 729         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 730         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
 731         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 732         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 733         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
 734         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 735         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
 736         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
 737         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
 738         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
 739         QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
 740         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
 741         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 742         QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
 743         QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
 744         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
 745         QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
 746
 747         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
 748         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
 749         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
 750         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
 751         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
 752
 753         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
 754         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
 755         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
 756         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
 757         QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
 758 };
 759
 760 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
 761         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
 762         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
 763         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
 764         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
 765         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
 766         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99),
 767         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 768         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 769         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a),
 770         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 771         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 772         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
 773         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b),
 774         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10),
 775         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
 776 };
 777
 778 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
 779         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 780         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 781         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
 782         QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
 783 };
 784
 785 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
 786         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 787         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 789         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 790         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 791         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 792         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 798         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 799         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
 800         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 801         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 802         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 803         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 804         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 806 };
 807
 808 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
 809         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
 810         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 811         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
 815         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 816 };
 817
 818 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
 819         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
 820         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 821         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 822         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 823         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
 824         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
 825         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 826 };
 827
 828 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
 829         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 830         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
 831         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
 832         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
 833         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
 834         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
 835         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 836 };
 837
 838 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
 839         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
 840         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
 841         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
 842         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
 843         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
 844         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
 845         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
 846 };
 847
 848 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
 849         QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
 850         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 851         QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
 852         QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
 853         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
 854         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
 855         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 856         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
 857         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 858         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 859         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
 860         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
 861         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
 862         QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
 863 };
 864
 865 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
 866         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
 867         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
 868         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
 869         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
 870         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
 871         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
 872         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
 873         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 874         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 875         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 876         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 877         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 878         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 879         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
 880         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 881         QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 882         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 883         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
 884         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
 885         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
 886         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
 887         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
 888         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
 889 };
 890
 891 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
 892         QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
 893         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 894         QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
 895         QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
 896         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
 897         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
 898         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 899         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
 900         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 901         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 902         QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
 903 };
 904
 905 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
 906         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
 907         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
 908         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
 909         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
 910         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
 911         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
 912         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
 913         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
 914         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 915         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 916         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
 917         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
 918 };
 919
 920 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
 921         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
 922         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
 923         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
 924         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
 925         QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
 926         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
 927         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
 928         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
 929         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
 930         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
 931         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
 932         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
 933         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 934         QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 935         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
 936         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
 937         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
 938         QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
 939         QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
 940         QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
 941 };
 942
 943 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
 944         QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
 945         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
 946         QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
 947         QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
 948         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
 949         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
 950         QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
 951         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
 952         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
 953         QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
 954         QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
 955 };
 956
 957 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
 958         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
 959         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 960         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 961         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 962         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
 963         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
 964         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
 965         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
 966         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
 967 };
 968
 969 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
 970         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
 971         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 972         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 973         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 974         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
 975         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
 976         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
 977         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
 978         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
 979 };
 980
 981 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
 982         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
 983         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
 984         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
 985         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
 986         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
 987         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
 988         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
 989         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
 990         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
 991 };
 992
 993 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
 994         QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
 995         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
 996         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
 997         QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
 998         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
 999         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1000         QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1001         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1002         QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1003 };
1004
1005 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1006         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1007         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1008         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1009         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1010         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1011         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1012         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1013         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1014         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1015         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1016         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1017         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1018         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1019         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1020         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1021         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1022         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1023         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1024         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1025         QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1026         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1027         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1028         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1029         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1030         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1031         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1032         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1033         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1034         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1035         QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1036         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1037         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1038         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1039         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1040         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1041         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1042         QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1043         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1044         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1045         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1046         QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1047         QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1048         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1049         QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1050         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1051         QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1052         QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1053 };
1054
1055 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1056         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1057         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1058         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1059         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1060         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1061 };
1062
1063 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1064         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1068         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1069         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1070         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1071         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1072         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1073         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1074         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1075         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1076         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1083         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1084         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1085         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1086         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1090         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1091         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1092         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1093         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1094         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1095         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1096         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1097         QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1098 };
1099
1100 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1101         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1102         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1103         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1104         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1105         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1106         QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1107         QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1108         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1109         QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1110         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1111         QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1112         QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1113         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1114         QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1115         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1116         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1117 };
1118
1119 /* list of regulators */
1120 struct qmp_regulator_data {
1121         const char *name;
1122         unsigned int enable_load;
1123 };
1124
1125 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1126         { .name = "vdda-phy", .enable_load = 21800 },
1127         { .name = "vdda-pll", .enable_load = 36000 },
1128 };
1129
1130 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1131         { 0x00, 0x0c, 0x15, 0x1a },
1132         { 0x02, 0x0e, 0x16, 0xff },
1133         { 0x02, 0x11, 0xff, 0xff },
1134         { 0x04, 0xff, 0xff, 0xff }
1135 };
1136
1137 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1138         { 0x02, 0x12, 0x16, 0x1a },
1139         { 0x09, 0x19, 0x1f, 0xff },
1140         { 0x10, 0x1f, 0xff, 0xff },
1141         { 0x1f, 0xff, 0xff, 0xff }
1142 };
1143
1144 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1145         { 0x00, 0x0c, 0x14, 0x19 },
1146         { 0x00, 0x0b, 0x12, 0xff },
1147         { 0x00, 0x0b, 0xff, 0xff },
1148         { 0x04, 0xff, 0xff, 0xff }
1149 };
1150
1151 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1152         { 0x08, 0x0f, 0x16, 0x1f },
1153         { 0x11, 0x1e, 0x1f, 0xff },
1154         { 0x19, 0x1f, 0xff, 0xff },
1155         { 0x1f, 0xff, 0xff, 0xff }
1156 };
1157
1158 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1159         { 0x00, 0x0c, 0x15, 0x1b },
1160         { 0x02, 0x0e, 0x16, 0xff },
1161         { 0x02, 0x11, 0xff, 0xff },
1162         { 0x04, 0xff, 0xff, 0xff }
1163 };
1164
1165 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1166         { 0x00, 0x0d, 0x14, 0x1a },
1167         { 0x00, 0x0e, 0x15, 0xff },
1168         { 0x00, 0x0d, 0xff, 0xff },
1169         { 0x03, 0xff, 0xff, 0xff }
1170 };
1171
1172 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1173         { 0x08, 0x0f, 0x16, 0x1f },
1174         { 0x11, 0x1e, 0x1f, 0xff },
1175         { 0x16, 0x1f, 0xff, 0xff },
1176         { 0x1f, 0xff, 0xff, 0xff }
1177 };
1178
1179 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1180         { 0x20, 0x2c, 0x35, 0x3b },
1181         { 0x22, 0x2e, 0x36, 0xff },
1182         { 0x22, 0x31, 0xff, 0xff },
1183         { 0x24, 0xff, 0xff, 0xff }
1184 };
1185
1186 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1187         { 0x22, 0x32, 0x36, 0x3a },
1188         { 0x29, 0x39, 0x3f, 0xff },
1189         { 0x30, 0x3f, 0xff, 0xff },
1190         { 0x3f, 0xff, 0xff, 0xff }
1191 };
1192
1193 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1194         { 0x20, 0x2d, 0x34, 0x3a },
1195         { 0x20, 0x2e, 0x35, 0xff },
1196         { 0x20, 0x2e, 0xff, 0xff },
1197         { 0x24, 0xff, 0xff, 0xff }
1198 };
1199
1200 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1201         { 0x28, 0x2f, 0x36, 0x3f },
1202         { 0x31, 0x3e, 0x3f, 0xff },
1203         { 0x36, 0x3f, 0xff, 0xff },
1204         { 0x3f, 0xff, 0xff, 0xff }
1205 };
1206
1207 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1208         { 0x20, 0x2d, 0x34, 0x3a },
1209         { 0x20, 0x2e, 0x35, 0xff },
1210         { 0x20, 0x2e, 0xff, 0xff },
1211         { 0x22, 0xff, 0xff, 0xff }
1212 };
1213
1214 struct qmp_combo;
1215
1216 struct qmp_combo_offsets {
1217         u16 com;
1218         u16 txa;
1219         u16 rxa;
1220         u16 txb;
1221         u16 rxb;
1222         u16 usb3_serdes;
1223         u16 usb3_pcs_misc;
1224         u16 usb3_pcs;
1225         u16 usb3_pcs_usb;
1226         u16 dp_serdes;
1227         u16 dp_txa;
1228         u16 dp_txb;
1229         u16 dp_dp_phy;
1230 };
1231
1232 struct qmp_phy_cfg {
1233         const struct qmp_combo_offsets *offsets;
1234
1235         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1236         const struct qmp_phy_init_tbl *serdes_tbl;
1237         int serdes_tbl_num;
1238         const struct qmp_phy_init_tbl *tx_tbl;
1239         int tx_tbl_num;
1240         const struct qmp_phy_init_tbl *rx_tbl;
1241         int rx_tbl_num;
1242         const struct qmp_phy_init_tbl *pcs_tbl;
1243         int pcs_tbl_num;
1244         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1245         int pcs_usb_tbl_num;
1246
1247         const struct qmp_phy_init_tbl *dp_serdes_tbl;
1248         int dp_serdes_tbl_num;
1249         const struct qmp_phy_init_tbl *dp_tx_tbl;
1250         int dp_tx_tbl_num;
1251
1252         /* Init sequence for DP PHY block link rates */
1253         const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1254         int serdes_tbl_rbr_num;
1255         const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1256         int serdes_tbl_hbr_num;
1257         const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1258         int serdes_tbl_hbr2_num;
1259         const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1260         int serdes_tbl_hbr3_num;
1261
1262         /* DP PHY swing and pre_emphasis tables */
1263         const u8 (*swing_hbr_rbr)[4][4];
1264         const u8 (*swing_hbr3_hbr2)[4][4];
1265         const u8 (*pre_emphasis_hbr_rbr)[4][4];
1266         const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1267
1268         /* DP PHY callbacks */
1269         int (*configure_dp_phy)(struct qmp_combo *qmp);
1270         void (*configure_dp_tx)(struct qmp_combo *qmp);
1271         int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1272         void (*dp_aux_init)(struct qmp_combo *qmp);
1273
1274         /* clock ids to be requested */
1275         const char * const *clk_list;
1276         int num_clks;
1277         /* resets to be requested */
1278         const char * const *reset_list;
1279         int num_resets;
1280         /* regulators to be requested */
1281         const struct qmp_regulator_data *vreg_list;
1282         int num_vregs;
1283
1284         /* array of registers with different offsets */
1285         const unsigned int *regs;
1286
1287         /* true, if PHY needs delay after POWER_DOWN */
1288         bool has_pwrdn_delay;
1289
1290         /* Offset from PCS to PCS_USB region */
1291         unsigned int pcs_usb_offset;
1292
1293 };
1294
1295 struct qmp_combo {
1296         struct device *dev;
1297
1298         const struct qmp_phy_cfg *cfg;
1299
1300         void __iomem *com;
1301
1302         void __iomem *serdes;
1303         void __iomem *tx;
1304         void __iomem *rx;
1305         void __iomem *pcs;
1306         void __iomem *tx2;
1307         void __iomem *rx2;
1308         void __iomem *pcs_misc;
1309         void __iomem *pcs_usb;
1310
1311         void __iomem *dp_serdes;
1312         void __iomem *dp_tx;
1313         void __iomem *dp_tx2;
1314         void __iomem *dp_dp_phy;
1315
1316         struct clk *pipe_clk;
1317         struct clk_bulk_data *clks;
1318         struct reset_control_bulk_data *resets;
1319         struct regulator_bulk_data *vregs;
1320
1321         struct mutex phy_mutex;
1322         int init_count;
1323
1324         struct phy *usb_phy;
1325         enum phy_mode mode;
1326         unsigned int usb_init_count;
1327
1328         struct phy *dp_phy;
1329         unsigned int dp_aux_cfg;
1330         struct phy_configure_opts_dp dp_opts;
1331         unsigned int dp_init_count;
1332
1333         struct clk_fixed_rate pipe_clk_fixed;
1334         struct clk_hw dp_link_hw;
1335         struct clk_hw dp_pixel_hw;
1336
1337         struct drm_bridge bridge;
1338
1339         struct typec_switch_dev *sw;
1340         enum typec_orientation orientation;
1341 };
1342
1343 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1344 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1345 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1346 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1347
1348 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1349 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1350 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1351 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1352
1353 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp);
1354
1355 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp);
1356 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp);
1357
1358 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1359 {
1360         u32 reg;
1361
1362         reg = readl(base + offset);
1363         reg |= val;
1364         writel(reg, base + offset);
1365
1366         /* ensure that above write is through */
1367         readl(base + offset);
1368 }
1369
1370 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1371 {
1372         u32 reg;
1373
1374         reg = readl(base + offset);
1375         reg &= ~val;
1376         writel(reg, base + offset);
1377
1378         /* ensure that above write is through */
1379         readl(base + offset);
1380 }
1381
1382 /* list of clocks required by phy */
1383 static const char * const qmp_v3_phy_clk_l[] = {
1384         "aux", "cfg_ahb", "ref", "com_aux",
1385 };
1386
1387 static const char * const qmp_v4_phy_clk_l[] = {
1388         "aux", "ref", "com_aux",
1389 };
1390
1391 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
1392 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1393         "aux", "ref_clk_src", "com_aux"
1394 };
1395
1396 /* list of resets */
1397 static const char * const msm8996_usb3phy_reset_l[] = {
1398         "phy", "common",
1399 };
1400
1401 static const char * const sc7180_usb3phy_reset_l[] = {
1402         "phy",
1403 };
1404
1405 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1406         .com            = 0x0000,
1407         .txa            = 0x1200,
1408         .rxa            = 0x1400,
1409         .txb            = 0x1600,
1410         .rxb            = 0x1800,
1411         .usb3_serdes    = 0x1000,
1412         .usb3_pcs_misc  = 0x1a00,
1413         .usb3_pcs       = 0x1c00,
1414         .usb3_pcs_usb   = 0x1f00,
1415         .dp_serdes      = 0x2000,
1416         .dp_txa         = 0x2200,
1417         .dp_txb         = 0x2600,
1418         .dp_dp_phy      = 0x2a00,
1419 };
1420
1421 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1422         .com            = 0x0000,
1423         .txa            = 0x0400,
1424         .rxa            = 0x0600,
1425         .txb            = 0x0a00,
1426         .rxb            = 0x0c00,
1427         .usb3_serdes    = 0x1000,
1428         .usb3_pcs_misc  = 0x1200,
1429         .usb3_pcs       = 0x1400,
1430         .usb3_pcs_usb   = 0x1700,
1431         .dp_serdes      = 0x2000,
1432         .dp_dp_phy      = 0x2200,
1433 };
1434
1435 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
1436         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1437         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1438         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1439         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1440         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1441         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1442         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1443         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1444
1445         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1446         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1447         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1448         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1449
1450         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1451         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1452         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1453         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1454         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1455         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1456         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1457         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1458
1459         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1460         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1461         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1462         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1463
1464         .dp_aux_init            = qmp_v3_dp_aux_init,
1465         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1466         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1467         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1468
1469         .clk_list               = qmp_v3_phy_clk_l,
1470         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1471         .reset_list             = sc7180_usb3phy_reset_l,
1472         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1473         .vreg_list              = qmp_phy_vreg_l,
1474         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1475         .regs                   = qmp_v3_usb3phy_regs_layout,
1476
1477         .has_pwrdn_delay        = true,
1478 };
1479
1480 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
1481         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1482         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1483         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1484         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1485         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1486         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1487         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1488         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1489
1490         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1491         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1492         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1493         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1494
1495         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1496         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1497         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1498         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1499         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1500         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1501         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1502         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1503
1504         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1505         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1506         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1507         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1508
1509         .dp_aux_init            = qmp_v3_dp_aux_init,
1510         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1511         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1512         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1513
1514         .clk_list               = qmp_v3_phy_clk_l,
1515         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1516         .reset_list             = msm8996_usb3phy_reset_l,
1517         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1518         .vreg_list              = qmp_phy_vreg_l,
1519         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1520         .regs                   = qmp_v3_usb3phy_regs_layout,
1521
1522         .has_pwrdn_delay        = true,
1523 };
1524
1525 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
1526         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1527         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1528         .tx_tbl                 = sm8150_usb3_tx_tbl,
1529         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1530         .rx_tbl                 = sm8150_usb3_rx_tbl,
1531         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1532         .pcs_tbl                = sm8150_usb3_pcs_tbl,
1533         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1534         .pcs_usb_tbl            = sm8150_usb3_pcs_usb_tbl,
1535         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1536
1537         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1538         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1539         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1540         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1541
1542         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1543         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1544         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1545         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1546         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1547         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1548         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1549         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1550
1551         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1552         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1553         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1554         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1555
1556         .dp_aux_init            = qmp_v4_dp_aux_init,
1557         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1558         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1559         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1560
1561         .clk_list               = qmp_v4_phy_clk_l,
1562         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1563         .reset_list             = msm8996_usb3phy_reset_l,
1564         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1565         .vreg_list              = qmp_phy_vreg_l,
1566         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1567         .regs                   = qmp_v4_usb3phy_regs_layout,
1568         .pcs_usb_offset         = 0x300,
1569
1570         .has_pwrdn_delay        = true,
1571 };
1572
1573 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
1574         .offsets                = &qmp_combo_offsets_v5,
1575
1576         .serdes_tbl             = sc8280xp_usb43dp_serdes_tbl,
1577         .serdes_tbl_num         = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1578         .tx_tbl                 = sc8280xp_usb43dp_tx_tbl,
1579         .tx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1580         .rx_tbl                 = sc8280xp_usb43dp_rx_tbl,
1581         .rx_tbl_num             = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1582         .pcs_tbl                = sc8280xp_usb43dp_pcs_tbl,
1583         .pcs_tbl_num            = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
1584
1585         .dp_serdes_tbl          = qmp_v5_dp_serdes_tbl,
1586         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1587         .dp_tx_tbl              = qmp_v5_5nm_dp_tx_tbl,
1588         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
1589
1590         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1591         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1592         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1593         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1594         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1595         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1596         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1597         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1598
1599         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1600         .pre_emphasis_hbr_rbr   = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1601         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1602         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1603
1604         .dp_aux_init            = qmp_v4_dp_aux_init,
1605         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1606         .configure_dp_phy       = qmp_v5_configure_dp_phy,
1607         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1608
1609         .clk_list               = qmp_v4_phy_clk_l,
1610         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1611         .reset_list             = msm8996_usb3phy_reset_l,
1612         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1613         .vreg_list              = qmp_phy_vreg_l,
1614         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1615         .regs                   = qmp_v4_usb3phy_regs_layout,
1616 };
1617
1618 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1619         .offsets                = &qmp_combo_offsets_v3,
1620
1621         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1622         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1623         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1624         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1625         .rx_tbl                 = sm6350_usb3_rx_tbl,
1626         .rx_tbl_num             = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1627         .pcs_tbl                = sm6350_usb3_pcs_tbl,
1628         .pcs_tbl_num            = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1629
1630         .dp_serdes_tbl          = qmp_v3_dp_serdes_tbl,
1631         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1632         .dp_tx_tbl              = qmp_v3_dp_tx_tbl,
1633         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1634
1635         .serdes_tbl_rbr         = qmp_v3_dp_serdes_tbl_rbr,
1636         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1637         .serdes_tbl_hbr         = qmp_v3_dp_serdes_tbl_hbr,
1638         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1639         .serdes_tbl_hbr2        = qmp_v3_dp_serdes_tbl_hbr2,
1640         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1641         .serdes_tbl_hbr3        = qmp_v3_dp_serdes_tbl_hbr3,
1642         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1643
1644         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1645         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1646         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1647         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1648
1649         .dp_aux_init            = qmp_v3_dp_aux_init,
1650         .configure_dp_tx        = qmp_v3_configure_dp_tx,
1651         .configure_dp_phy       = qmp_v3_configure_dp_phy,
1652         .calibrate_dp_phy       = qmp_v3_calibrate_dp_phy,
1653
1654         .clk_list               = qmp_v4_phy_clk_l,
1655         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1656         .reset_list             = msm8996_usb3phy_reset_l,
1657         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1658         .vreg_list              = qmp_phy_vreg_l,
1659         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1660         .regs                   = qmp_v3_usb3phy_regs_layout,
1661 };
1662
1663 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1664         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1665         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1666         .tx_tbl                 = sm8250_usb3_tx_tbl,
1667         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1668         .rx_tbl                 = sm8250_usb3_rx_tbl,
1669         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1670         .pcs_tbl                = sm8250_usb3_pcs_tbl,
1671         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1672         .pcs_usb_tbl            = sm8250_usb3_pcs_usb_tbl,
1673         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1674
1675         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1676         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1677         .dp_tx_tbl              = qmp_v4_dp_tx_tbl,
1678         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1679
1680         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1681         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1682         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1683         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1684         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1685         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1686         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1687         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1688
1689         .swing_hbr_rbr          = &qmp_dp_v3_voltage_swing_hbr_rbr,
1690         .pre_emphasis_hbr_rbr   = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1691         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1692         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1693
1694         .dp_aux_init            = qmp_v4_dp_aux_init,
1695         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1696         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1697         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1698
1699         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
1700         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1701         .reset_list             = msm8996_usb3phy_reset_l,
1702         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1703         .vreg_list              = qmp_phy_vreg_l,
1704         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1705         .regs                   = qmp_v4_usb3phy_regs_layout,
1706         .pcs_usb_offset         = 0x300,
1707
1708         .has_pwrdn_delay        = true,
1709 };
1710
1711 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1712         .offsets                = &qmp_combo_offsets_v3,
1713
1714         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1715         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1716         .tx_tbl                 = sm8350_usb3_tx_tbl,
1717         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1718         .rx_tbl                 = sm8350_usb3_rx_tbl,
1719         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1720         .pcs_tbl                = sm8350_usb3_pcs_tbl,
1721         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1722         .pcs_usb_tbl            = sm8350_usb3_pcs_usb_tbl,
1723         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1724
1725         .dp_serdes_tbl          = qmp_v4_dp_serdes_tbl,
1726         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1727         .dp_tx_tbl              = qmp_v5_dp_tx_tbl,
1728         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1729
1730         .serdes_tbl_rbr         = qmp_v4_dp_serdes_tbl_rbr,
1731         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1732         .serdes_tbl_hbr         = qmp_v4_dp_serdes_tbl_hbr,
1733         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1734         .serdes_tbl_hbr2        = qmp_v4_dp_serdes_tbl_hbr2,
1735         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1736         .serdes_tbl_hbr3        = qmp_v4_dp_serdes_tbl_hbr3,
1737         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1738
1739         .swing_hbr_rbr          = &qmp_dp_v4_voltage_swing_hbr_rbr,
1740         .pre_emphasis_hbr_rbr   = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1741         .swing_hbr3_hbr2        = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1742         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1743
1744         .dp_aux_init            = qmp_v4_dp_aux_init,
1745         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1746         .configure_dp_phy       = qmp_v4_configure_dp_phy,
1747         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1748
1749         .clk_list               = qmp_v4_phy_clk_l,
1750         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1751         .reset_list             = msm8996_usb3phy_reset_l,
1752         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1753         .vreg_list              = qmp_phy_vreg_l,
1754         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1755         .regs                   = qmp_v4_usb3phy_regs_layout,
1756
1757         .has_pwrdn_delay        = true,
1758 };
1759
1760 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1761         .offsets                = &qmp_combo_offsets_v3,
1762
1763         .serdes_tbl             = sm8550_usb3_serdes_tbl,
1764         .serdes_tbl_num         = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1765         .tx_tbl                 = sm8550_usb3_tx_tbl,
1766         .tx_tbl_num             = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1767         .rx_tbl                 = sm8550_usb3_rx_tbl,
1768         .rx_tbl_num             = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1769         .pcs_tbl                = sm8550_usb3_pcs_tbl,
1770         .pcs_tbl_num            = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1771         .pcs_usb_tbl            = sm8550_usb3_pcs_usb_tbl,
1772         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1773
1774         .dp_serdes_tbl          = qmp_v6_dp_serdes_tbl,
1775         .dp_serdes_tbl_num      = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1776         .dp_tx_tbl              = qmp_v6_dp_tx_tbl,
1777         .dp_tx_tbl_num          = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1778
1779         .serdes_tbl_rbr         = qmp_v6_dp_serdes_tbl_rbr,
1780         .serdes_tbl_rbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1781         .serdes_tbl_hbr         = qmp_v6_dp_serdes_tbl_hbr,
1782         .serdes_tbl_hbr_num     = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1783         .serdes_tbl_hbr2        = qmp_v6_dp_serdes_tbl_hbr2,
1784         .serdes_tbl_hbr2_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1785         .serdes_tbl_hbr3        = qmp_v6_dp_serdes_tbl_hbr3,
1786         .serdes_tbl_hbr3_num    = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1787
1788         .swing_hbr_rbr          = &qmp_dp_v5_voltage_swing_hbr_rbr,
1789         .pre_emphasis_hbr_rbr   = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1790         .swing_hbr3_hbr2        = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1791         .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1792
1793         .dp_aux_init            = qmp_v6_dp_aux_init,
1794         .configure_dp_tx        = qmp_v4_configure_dp_tx,
1795         .configure_dp_phy       = qmp_v6_configure_dp_phy,
1796         .calibrate_dp_phy       = qmp_v4_calibrate_dp_phy,
1797
1798         .regs                   = qmp_v4_usb3phy_regs_layout,
1799         .clk_list               = qmp_v4_phy_clk_l,
1800         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1801         .reset_list             = msm8996_usb3phy_reset_l,
1802         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1803         .vreg_list              = qmp_phy_vreg_l,
1804         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1805 };
1806
1807 static void qmp_combo_configure_lane(void __iomem *base,
1808                                         const struct qmp_phy_init_tbl tbl[],
1809                                         int num,
1810                                         u8 lane_mask)
1811 {
1812         int i;
1813         const struct qmp_phy_init_tbl *t = tbl;
1814
1815         if (!t)
1816                 return;
1817
1818         for (i = 0; i < num; i++, t++) {
1819                 if (!(t->lane_mask & lane_mask))
1820                         continue;
1821
1822                 writel(t->val, base + t->offset);
1823         }
1824 }
1825
1826 static void qmp_combo_configure(void __iomem *base,
1827                                    const struct qmp_phy_init_tbl tbl[],
1828                                    int num)
1829 {
1830         qmp_combo_configure_lane(base, tbl, num, 0xff);
1831 }
1832
1833 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
1834 {
1835         const struct qmp_phy_cfg *cfg = qmp->cfg;
1836         void __iomem *serdes = qmp->dp_serdes;
1837         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1838
1839         qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
1840
1841         switch (dp_opts->link_rate) {
1842         case 1620:
1843                 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr,
1844                                 cfg->serdes_tbl_rbr_num);
1845                 break;
1846         case 2700:
1847                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr,
1848                                 cfg->serdes_tbl_hbr_num);
1849                 break;
1850         case 5400:
1851                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2,
1852                                 cfg->serdes_tbl_hbr2_num);
1853                 break;
1854         case 8100:
1855                 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3,
1856                                 cfg->serdes_tbl_hbr3_num);
1857                 break;
1858         default:
1859                 /* Other link rates aren't supported */
1860                 return -EINVAL;
1861         }
1862
1863         return 0;
1864 }
1865
1866 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
1867 {
1868         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1869                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
1870                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1871
1872         /* Turn on BIAS current for PHY/PLL */
1873         writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
1874                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
1875                qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1876
1877         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1878
1879         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1880                DP_PHY_PD_CTL_LANE_0_1_PWRDN |
1881                DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
1882                DP_PHY_PD_CTL_DP_CLAMP_EN,
1883                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1884
1885         writel(QSERDES_V3_COM_BIAS_EN |
1886                QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
1887                QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
1888                QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
1889                qmp->dp_serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
1890
1891         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
1892         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
1893         writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
1894         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
1895         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
1896         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
1897         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
1898         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
1899         writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
1900         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
1901         qmp->dp_aux_cfg = 0;
1902
1903         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
1904                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
1905                PHY_AUX_REQ_ERR_MASK,
1906                qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
1907 }
1908
1909 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp,
1910                 unsigned int drv_lvl_reg, unsigned int emp_post_reg)
1911 {
1912         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1913         const struct qmp_phy_cfg *cfg = qmp->cfg;
1914         unsigned int v_level = 0, p_level = 0;
1915         u8 voltage_swing_cfg, pre_emphasis_cfg;
1916         int i;
1917
1918         for (i = 0; i < dp_opts->lanes; i++) {
1919                 v_level = max(v_level, dp_opts->voltage[i]);
1920                 p_level = max(p_level, dp_opts->pre[i]);
1921         }
1922
1923         if (dp_opts->link_rate <= 2700) {
1924                 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
1925                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
1926         } else {
1927                 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
1928                 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
1929         }
1930
1931         /* TODO: Move check to config check */
1932         if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
1933                 return -EINVAL;
1934
1935         /* Enable MUX to use Cursor values from these registers */
1936         voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
1937         pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
1938
1939         writel(voltage_swing_cfg, qmp->dp_tx + drv_lvl_reg);
1940         writel(pre_emphasis_cfg, qmp->dp_tx + emp_post_reg);
1941         writel(voltage_swing_cfg, qmp->dp_tx2 + drv_lvl_reg);
1942         writel(pre_emphasis_cfg, qmp->dp_tx2 + emp_post_reg);
1943
1944         return 0;
1945 }
1946
1947 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
1948 {
1949         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1950         u32 bias_en, drvr_en;
1951
1952         if (qmp_combo_configure_dp_swing(qmp, QSERDES_V3_TX_TX_DRV_LVL,
1953                                 QSERDES_V3_TX_TX_EMP_POST1_LVL) < 0)
1954                 return;
1955
1956         if (dp_opts->lanes == 1) {
1957                 bias_en = 0x3e;
1958                 drvr_en = 0x13;
1959         } else {
1960                 bias_en = 0x3f;
1961                 drvr_en = 0x10;
1962         }
1963
1964         writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
1965         writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
1966         writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
1967         writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
1968 }
1969
1970 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
1971 {
1972         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
1973         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1974         u32 val;
1975
1976         val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
1977               DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
1978
1979         if (dp_opts->lanes == 4 || reverse)
1980                 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
1981         if (dp_opts->lanes == 4 || !reverse)
1982                 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
1983
1984         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
1985
1986         if (reverse)
1987                 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);
1988         else
1989                 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);
1990
1991         return reverse;
1992 }
1993
1994 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
1995 {
1996         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
1997         u32 phy_vco_div, status;
1998         unsigned long pixel_freq;
1999
2000         qmp_combo_configure_dp_mode(qmp);
2001
2002         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2003         writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2004
2005         switch (dp_opts->link_rate) {
2006         case 1620:
2007                 phy_vco_div = 0x1;
2008                 pixel_freq = 1620000000UL / 2;
2009                 break;
2010         case 2700:
2011                 phy_vco_div = 0x1;
2012                 pixel_freq = 2700000000UL / 2;
2013                 break;
2014         case 5400:
2015                 phy_vco_div = 0x2;
2016                 pixel_freq = 5400000000UL / 4;
2017                 break;
2018         case 8100:
2019                 phy_vco_div = 0x0;
2020                 pixel_freq = 8100000000UL / 6;
2021                 break;
2022         default:
2023                 /* Other link rates aren't supported */
2024                 return -EINVAL;
2025         }
2026         writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_VCO_DIV);
2027
2028         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2029         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2030
2031         writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2032         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2033         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2034         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2035         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2036
2037         writel(0x20, qmp->dp_serdes + QSERDES_V3_COM_RESETSM_CNTRL);
2038
2039         if (readl_poll_timeout(qmp->dp_serdes + QSERDES_V3_COM_C_READY_STATUS,
2040                         status,
2041                         ((status & BIT(0)) > 0),
2042                         500,
2043                         10000))
2044                 return -ETIMEDOUT;
2045
2046         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2047
2048         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
2049                         status,
2050                         ((status & BIT(1)) > 0),
2051                         500,
2052                         10000))
2053                 return -ETIMEDOUT;
2054
2055         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2056         udelay(2000);
2057         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2058
2059         return readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS,
2060                         status,
2061                         ((status & BIT(1)) > 0),
2062                         500,
2063                         10000);
2064 }
2065
2066 /*
2067  * We need to calibrate the aux setting here as many times
2068  * as the caller tries
2069  */
2070 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2071 {
2072         static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2073         u8 val;
2074
2075         qmp->dp_aux_cfg++;
2076         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2077         val = cfg1_settings[qmp->dp_aux_cfg];
2078
2079         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2080
2081         return 0;
2082 }
2083
2084 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2085 {
2086         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2087                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2088                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2089
2090         /* Turn on BIAS current for PHY/PLL */
2091         writel(0x17, qmp->dp_serdes + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN);
2092
2093         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2094         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2095         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2096         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2097         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2098         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2099         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2100         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2101         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2102         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2103         qmp->dp_aux_cfg = 0;
2104
2105         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2106                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2107                PHY_AUX_REQ_ERR_MASK,
2108                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2109 }
2110
2111 static void qmp_v6_dp_aux_init(struct qmp_combo *qmp)
2112 {
2113         writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2114                DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2115                qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2116
2117         /* Turn on BIAS current for PHY/PLL */
2118         writel(0x17, qmp->dp_serdes + QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN);
2119
2120         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2121         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2122         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2123         writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2124         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2125         writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2126         writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2127         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2128         writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2129         writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2130         qmp->dp_aux_cfg = 0;
2131
2132         writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2133                PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2134                PHY_AUX_REQ_ERR_MASK,
2135                qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2136 }
2137
2138 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2139 {
2140         /* Program default values before writing proper values */
2141         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2142         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2143
2144         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2145         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2146
2147         qmp_combo_configure_dp_swing(qmp, QSERDES_V4_TX_TX_DRV_LVL,
2148                         QSERDES_V4_TX_TX_EMP_POST1_LVL);
2149 }
2150
2151 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp,
2152                                      unsigned int com_resetm_ctrl_reg,
2153                                      unsigned int com_c_ready_status_reg,
2154                                      unsigned int com_cmn_status_reg,
2155                                      unsigned int dp_phy_status_reg)
2156 {
2157         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2158         u32 phy_vco_div, status;
2159         unsigned long pixel_freq;
2160
2161         writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1);
2162
2163         qmp_combo_configure_dp_mode(qmp);
2164
2165         writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2166         writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2167
2168         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2169         writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2170
2171         switch (dp_opts->link_rate) {
2172         case 1620:
2173                 phy_vco_div = 0x1;
2174                 pixel_freq = 1620000000UL / 2;
2175                 break;
2176         case 2700:
2177                 phy_vco_div = 0x1;
2178                 pixel_freq = 2700000000UL / 2;
2179                 break;
2180         case 5400:
2181                 phy_vco_div = 0x2;
2182                 pixel_freq = 5400000000UL / 4;
2183                 break;
2184         case 8100:
2185                 phy_vco_div = 0x0;
2186                 pixel_freq = 8100000000UL / 6;
2187                 break;
2188         default:
2189                 /* Other link rates aren't supported */
2190                 return -EINVAL;
2191         }
2192         writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
2193
2194         clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2195         clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2196
2197         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2198         writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2199         writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2200         writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2201
2202         writel(0x20, qmp->dp_serdes + com_resetm_ctrl_reg);
2203
2204         if (readl_poll_timeout(qmp->dp_serdes + com_c_ready_status_reg,
2205                         status,
2206                         ((status & BIT(0)) > 0),
2207                         500,
2208                         10000))
2209                 return -ETIMEDOUT;
2210
2211         if (readl_poll_timeout(qmp->dp_serdes + com_cmn_status_reg,
2212                         status,
2213                         ((status & BIT(0)) > 0),
2214                         500,
2215                         10000))
2216                 return -ETIMEDOUT;
2217
2218         if (readl_poll_timeout(qmp->dp_serdes + com_cmn_status_reg,
2219                         status,
2220                         ((status & BIT(1)) > 0),
2221                         500,
2222                         10000))
2223                 return -ETIMEDOUT;
2224
2225         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2226
2227         if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2228                         status,
2229                         ((status & BIT(0)) > 0),
2230                         500,
2231                         10000))
2232                 return -ETIMEDOUT;
2233
2234         if (readl_poll_timeout(qmp->dp_dp_phy + dp_phy_status_reg,
2235                         status,
2236                         ((status & BIT(1)) > 0),
2237                         500,
2238                         10000))
2239                 return -ETIMEDOUT;
2240
2241         return 0;
2242 }
2243
2244 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2245 {
2246         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2247         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2248         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2249         u32 status;
2250         int ret;
2251
2252         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2253                                         QSERDES_V4_COM_C_READY_STATUS,
2254                                         QSERDES_V4_COM_CMN_STATUS,
2255                                         QSERDES_V4_DP_PHY_STATUS);
2256         if (ret < 0)
2257                 return ret;
2258
2259         /*
2260          * At least for 7nm DP PHY this has to be done after enabling link
2261          * clock.
2262          */
2263
2264         if (dp_opts->lanes == 1) {
2265                 bias0_en = reverse ? 0x3e : 0x15;
2266                 bias1_en = reverse ? 0x15 : 0x3e;
2267                 drvr0_en = reverse ? 0x13 : 0x10;
2268                 drvr1_en = reverse ? 0x10 : 0x13;
2269         } else if (dp_opts->lanes == 2) {
2270                 bias0_en = reverse ? 0x3f : 0x15;
2271                 bias1_en = reverse ? 0x15 : 0x3f;
2272                 drvr0_en = 0x10;
2273                 drvr1_en = 0x10;
2274         } else {
2275                 bias0_en = 0x3f;
2276                 bias1_en = 0x3f;
2277                 drvr0_en = 0x10;
2278                 drvr1_en = 0x10;
2279         }
2280
2281         writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2282         writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2283         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2284         writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2285
2286         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2287         udelay(2000);
2288         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2289
2290         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2291                         status,
2292                         ((status & BIT(1)) > 0),
2293                         500,
2294                         10000))
2295                 return -ETIMEDOUT;
2296
2297         writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2298         writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2299
2300         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2301         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2302
2303         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2304         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2305
2306         return 0;
2307 }
2308
2309 static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp)
2310 {
2311         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2312         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2313         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2314         u32 status;
2315         int ret;
2316
2317         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V4_COM_RESETSM_CNTRL,
2318                                         QSERDES_V4_COM_C_READY_STATUS,
2319                                         QSERDES_V4_COM_CMN_STATUS,
2320                                         QSERDES_V4_DP_PHY_STATUS);
2321         if (ret < 0)
2322                 return ret;
2323
2324         if (dp_opts->lanes == 1) {
2325                 bias0_en = reverse ? 0x3e : 0x1a;
2326                 drvr0_en = reverse ? 0x13 : 0x10;
2327                 bias1_en = reverse ? 0x15 : 0x3e;
2328                 drvr1_en = reverse ? 0x10 : 0x13;
2329         } else if (dp_opts->lanes == 2) {
2330                 bias0_en = reverse ? 0x3f : 0x15;
2331                 drvr0_en = 0x10;
2332                 bias1_en = reverse ? 0x15 : 0x3f;
2333                 drvr1_en = 0x10;
2334         } else {
2335                 bias0_en = 0x3f;
2336                 bias1_en = 0x3f;
2337                 drvr0_en = 0x10;
2338                 drvr1_en = 0x10;
2339         }
2340
2341         writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
2342         writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
2343         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
2344         writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
2345
2346         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2347         udelay(2000);
2348         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2349
2350         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V4_DP_PHY_STATUS,
2351                         status,
2352                         ((status & BIT(1)) > 0),
2353                         500,
2354                         10000))
2355                 return -ETIMEDOUT;
2356
2357         writel(0x0a, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_POL_INV);
2358         writel(0x0a, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_POL_INV);
2359
2360         writel(0x27, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2361         writel(0x27, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_DRV_LVL);
2362
2363         writel(0x20, qmp->dp_tx + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2364         writel(0x20, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL);
2365
2366         return 0;
2367 }
2368
2369 static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
2370 {
2371         bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2372         const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2373         u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2374         u32 status;
2375         int ret;
2376
2377         ret = qmp_v456_configure_dp_phy(qmp, QSERDES_V6_COM_RESETSM_CNTRL,
2378                                         QSERDES_V6_COM_C_READY_STATUS,
2379                                         QSERDES_V6_COM_CMN_STATUS,
2380                                         QSERDES_V6_DP_PHY_STATUS);
2381         if (ret < 0)
2382                 return ret;
2383
2384         if (dp_opts->lanes == 1) {
2385                 bias0_en = reverse ? 0x3e : 0x1a;
2386                 drvr0_en = reverse ? 0x13 : 0x10;
2387                 bias1_en = reverse ? 0x15 : 0x3e;
2388                 drvr1_en = reverse ? 0x10 : 0x13;
2389         } else if (dp_opts->lanes == 2) {
2390                 bias0_en = reverse ? 0x3f : 0x15;
2391                 drvr0_en = 0x10;
2392                 bias1_en = reverse ? 0x15 : 0x3f;
2393                 drvr1_en = 0x10;
2394         } else {
2395                 bias0_en = 0x3f;
2396                 bias1_en = 0x3f;
2397                 drvr0_en = 0x10;
2398                 drvr1_en = 0x10;
2399         }
2400
2401         writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2402         writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2403         writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
2404         writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
2405
2406         writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2407         udelay(2000);
2408         writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2409
2410         if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V6_DP_PHY_STATUS,
2411                                status,
2412                                ((status & BIT(1)) > 0),
2413                                500,
2414                                10000))
2415                 return -ETIMEDOUT;
2416
2417         writel(0x0a, qmp->dp_tx + QSERDES_V4_TX_TX_POL_INV);
2418         writel(0x0a, qmp->dp_tx2 + QSERDES_V4_TX_TX_POL_INV);
2419
2420         writel(0x27, qmp->dp_tx + QSERDES_V4_TX_TX_DRV_LVL);
2421         writel(0x27, qmp->dp_tx2 + QSERDES_V4_TX_TX_DRV_LVL);
2422
2423         writel(0x20, qmp->dp_tx + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2424         writel(0x20, qmp->dp_tx2 + QSERDES_V4_TX_TX_EMP_POST1_LVL);
2425
2426         return 0;
2427 }
2428
2429 /*
2430  * We need to calibrate the aux setting here as many times
2431  * as the caller tries
2432  */
2433 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2434 {
2435         static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2436         u8 val;
2437
2438         qmp->dp_aux_cfg++;
2439         qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2440         val = cfg1_settings[qmp->dp_aux_cfg];
2441
2442         writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2443
2444         return 0;
2445 }
2446
2447 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2448 {
2449         const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2450         struct qmp_combo *qmp = phy_get_drvdata(phy);
2451         const struct qmp_phy_cfg *cfg = qmp->cfg;
2452
2453         mutex_lock(&qmp->phy_mutex);
2454
2455         memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2456         if (qmp->dp_opts.set_voltages) {
2457                 cfg->configure_dp_tx(qmp);
2458                 qmp->dp_opts.set_voltages = 0;
2459         }
2460
2461         mutex_unlock(&qmp->phy_mutex);
2462
2463         return 0;
2464 }
2465
2466 static int qmp_combo_dp_calibrate(struct phy *phy)
2467 {
2468         struct qmp_combo *qmp = phy_get_drvdata(phy);
2469         const struct qmp_phy_cfg *cfg = qmp->cfg;
2470         int ret = 0;
2471
2472         mutex_lock(&qmp->phy_mutex);
2473
2474         if (cfg->calibrate_dp_phy)
2475                 ret = cfg->calibrate_dp_phy(qmp);
2476
2477         mutex_unlock(&qmp->phy_mutex);
2478
2479         return ret;
2480 }
2481
2482 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
2483 {
2484         const struct qmp_phy_cfg *cfg = qmp->cfg;
2485         void __iomem *com = qmp->com;
2486         int ret;
2487         u32 val;
2488
2489         if (!force && qmp->init_count++)
2490                 return 0;
2491
2492         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2493         if (ret) {
2494                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2495                 goto err_decrement_count;
2496         }
2497
2498         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2499         if (ret) {
2500                 dev_err(qmp->dev, "reset assert failed\n");
2501                 goto err_disable_regulators;
2502         }
2503
2504         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2505         if (ret) {
2506                 dev_err(qmp->dev, "reset deassert failed\n");
2507                 goto err_disable_regulators;
2508         }
2509
2510         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2511         if (ret)
2512                 goto err_assert_reset;
2513
2514         qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
2515
2516         /* override hardware control for reset of qmp phy */
2517         qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2518                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2519                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2520
2521         /* Use software based port select and switch on typec orientation */
2522         val = SW_PORTSELECT_MUX;
2523         if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
2524                 val |= SW_PORTSELECT_VAL;
2525         writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
2526         writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
2527
2528         /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2529         qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2530                         SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2531                         SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2532
2533         qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2534         qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2535
2536         qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2537                         SW_PWRDN);
2538
2539         return 0;
2540
2541 err_assert_reset:
2542         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2543 err_disable_regulators:
2544         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2545 err_decrement_count:
2546         qmp->init_count--;
2547
2548         return ret;
2549 }
2550
2551 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
2552 {
2553         const struct qmp_phy_cfg *cfg = qmp->cfg;
2554
2555         if (!force && --qmp->init_count)
2556                 return 0;
2557
2558         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2559
2560         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2561
2562         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2563
2564         return 0;
2565 }
2566
2567 static int qmp_combo_dp_init(struct phy *phy)
2568 {
2569         struct qmp_combo *qmp = phy_get_drvdata(phy);
2570         const struct qmp_phy_cfg *cfg = qmp->cfg;
2571         int ret;
2572
2573         mutex_lock(&qmp->phy_mutex);
2574
2575         ret = qmp_combo_com_init(qmp, false);
2576         if (ret)
2577                 goto out_unlock;
2578
2579         cfg->dp_aux_init(qmp);
2580
2581         qmp->dp_init_count++;
2582
2583 out_unlock:
2584         mutex_unlock(&qmp->phy_mutex);
2585         return ret;
2586 }
2587
2588 static int qmp_combo_dp_exit(struct phy *phy)
2589 {
2590         struct qmp_combo *qmp = phy_get_drvdata(phy);
2591
2592         mutex_lock(&qmp->phy_mutex);
2593
2594         qmp_combo_com_exit(qmp, false);
2595
2596         qmp->dp_init_count--;
2597
2598         mutex_unlock(&qmp->phy_mutex);
2599
2600         return 0;
2601 }
2602
2603 static int qmp_combo_dp_power_on(struct phy *phy)
2604 {
2605         struct qmp_combo *qmp = phy_get_drvdata(phy);
2606         const struct qmp_phy_cfg *cfg = qmp->cfg;
2607         void __iomem *tx = qmp->dp_tx;
2608         void __iomem *tx2 = qmp->dp_tx2;
2609
2610         mutex_lock(&qmp->phy_mutex);
2611
2612         qmp_combo_dp_serdes_init(qmp);
2613
2614         qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2615         qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2616
2617         /* Configure special DP tx tunings */
2618         cfg->configure_dp_tx(qmp);
2619
2620         /* Configure link rate, swing, etc. */
2621         cfg->configure_dp_phy(qmp);
2622
2623         mutex_unlock(&qmp->phy_mutex);
2624
2625         return 0;
2626 }
2627
2628 static int qmp_combo_dp_power_off(struct phy *phy)
2629 {
2630         struct qmp_combo *qmp = phy_get_drvdata(phy);
2631
2632         mutex_lock(&qmp->phy_mutex);
2633
2634         /* Assert DP PHY power down */
2635         writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2636
2637         mutex_unlock(&qmp->phy_mutex);
2638
2639         return 0;
2640 }
2641
2642 static int qmp_combo_usb_power_on(struct phy *phy)
2643 {
2644         struct qmp_combo *qmp = phy_get_drvdata(phy);
2645         const struct qmp_phy_cfg *cfg = qmp->cfg;
2646         void __iomem *serdes = qmp->serdes;
2647         void __iomem *tx = qmp->tx;
2648         void __iomem *rx = qmp->rx;
2649         void __iomem *tx2 = qmp->tx2;
2650         void __iomem *rx2 = qmp->rx2;
2651         void __iomem *pcs = qmp->pcs;
2652         void __iomem *status;
2653         unsigned int val;
2654         int ret;
2655
2656         qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2657
2658         ret = clk_prepare_enable(qmp->pipe_clk);
2659         if (ret) {
2660                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2661                 return ret;
2662         }
2663
2664         /* Tx, Rx, and PCS configurations */
2665         qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2666         qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2667
2668         qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2669         qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2670
2671         qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2672
2673         if (cfg->has_pwrdn_delay)
2674                 usleep_range(10, 20);
2675
2676         /* Pull PHY out of reset state */
2677         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2678
2679         /* start SerDes and Phy-Coding-Sublayer */
2680         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2681
2682         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2683         ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2684                         PHY_INIT_COMPLETE_TIMEOUT);
2685         if (ret) {
2686                 dev_err(qmp->dev, "phy initialization timed-out\n");
2687                 goto err_disable_pipe_clk;
2688         }
2689
2690         return 0;
2691
2692 err_disable_pipe_clk:
2693         clk_disable_unprepare(qmp->pipe_clk);
2694
2695         return ret;
2696 }
2697
2698 static int qmp_combo_usb_power_off(struct phy *phy)
2699 {
2700         struct qmp_combo *qmp = phy_get_drvdata(phy);
2701         const struct qmp_phy_cfg *cfg = qmp->cfg;
2702
2703         clk_disable_unprepare(qmp->pipe_clk);
2704
2705         /* PHY reset */
2706         qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2707
2708         /* stop SerDes and Phy-Coding-Sublayer */
2709         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2710                         SERDES_START | PCS_START);
2711
2712         /* Put PHY into POWER DOWN state: active low */
2713         qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2714                         SW_PWRDN);
2715
2716         return 0;
2717 }
2718
2719 static int qmp_combo_usb_init(struct phy *phy)
2720 {
2721         struct qmp_combo *qmp = phy_get_drvdata(phy);
2722         int ret;
2723
2724         mutex_lock(&qmp->phy_mutex);
2725         ret = qmp_combo_com_init(qmp, false);
2726         if (ret)
2727                 goto out_unlock;
2728
2729         ret = qmp_combo_usb_power_on(phy);
2730         if (ret) {
2731                 qmp_combo_com_exit(qmp, false);
2732                 goto out_unlock;
2733         }
2734
2735         qmp->usb_init_count++;
2736
2737 out_unlock:
2738         mutex_unlock(&qmp->phy_mutex);
2739         return ret;
2740 }
2741
2742 static int qmp_combo_usb_exit(struct phy *phy)
2743 {
2744         struct qmp_combo *qmp = phy_get_drvdata(phy);
2745         int ret;
2746
2747         mutex_lock(&qmp->phy_mutex);
2748         ret = qmp_combo_usb_power_off(phy);
2749         if (ret)
2750                 goto out_unlock;
2751
2752         ret = qmp_combo_com_exit(qmp, false);
2753         if (ret)
2754                 goto out_unlock;
2755
2756         qmp->usb_init_count--;
2757
2758 out_unlock:
2759         mutex_unlock(&qmp->phy_mutex);
2760         return ret;
2761 }
2762
2763 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2764 {
2765         struct qmp_combo *qmp = phy_get_drvdata(phy);
2766
2767         qmp->mode = mode;
2768
2769         return 0;
2770 }
2771
2772 static const struct phy_ops qmp_combo_usb_phy_ops = {
2773         .init           = qmp_combo_usb_init,
2774         .exit           = qmp_combo_usb_exit,
2775         .set_mode       = qmp_combo_usb_set_mode,
2776         .owner          = THIS_MODULE,
2777 };
2778
2779 static const struct phy_ops qmp_combo_dp_phy_ops = {
2780         .init           = qmp_combo_dp_init,
2781         .configure      = qmp_combo_dp_configure,
2782         .power_on       = qmp_combo_dp_power_on,
2783         .calibrate      = qmp_combo_dp_calibrate,
2784         .power_off      = qmp_combo_dp_power_off,
2785         .exit           = qmp_combo_dp_exit,
2786         .owner          = THIS_MODULE,
2787 };
2788
2789 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
2790 {
2791         const struct qmp_phy_cfg *cfg = qmp->cfg;
2792         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2793         void __iomem *pcs_misc = qmp->pcs_misc;
2794         u32 intr_mask;
2795
2796         if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2797             qmp->mode == PHY_MODE_USB_DEVICE_SS)
2798                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2799         else
2800                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2801
2802         /* Clear any pending interrupts status */
2803         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2804         /* Writing 1 followed by 0 clears the interrupt */
2805         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2806
2807         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2808                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2809
2810         /* Enable required PHY autonomous mode interrupts */
2811         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2812
2813         /* Enable i/o clamp_n for autonomous mode */
2814         if (pcs_misc)
2815                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2816 }
2817
2818 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
2819 {
2820         const struct qmp_phy_cfg *cfg = qmp->cfg;
2821         void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2822         void __iomem *pcs_misc = qmp->pcs_misc;
2823
2824         /* Disable i/o clamp_n on resume for normal mode */
2825         if (pcs_misc)
2826                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2827
2828         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2829                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2830
2831         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2832         /* Writing 1 followed by 0 clears the interrupt */
2833         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2834 }
2835
2836 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
2837 {
2838         struct qmp_combo *qmp = dev_get_drvdata(dev);
2839         const struct qmp_phy_cfg *cfg = qmp->cfg;
2840
2841         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2842
2843         if (!qmp->init_count) {
2844                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2845                 return 0;
2846         }
2847
2848         qmp_combo_enable_autonomous_mode(qmp);
2849
2850         clk_disable_unprepare(qmp->pipe_clk);
2851         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2852
2853         return 0;
2854 }
2855
2856 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
2857 {
2858         struct qmp_combo *qmp = dev_get_drvdata(dev);
2859         const struct qmp_phy_cfg *cfg = qmp->cfg;
2860         int ret = 0;
2861
2862         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2863
2864         if (!qmp->init_count) {
2865                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2866                 return 0;
2867         }
2868
2869         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2870         if (ret)
2871                 return ret;
2872
2873         ret = clk_prepare_enable(qmp->pipe_clk);
2874         if (ret) {
2875                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2876                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2877                 return ret;
2878         }
2879
2880         qmp_combo_disable_autonomous_mode(qmp);
2881
2882         return 0;
2883 }
2884
2885 static const struct dev_pm_ops qmp_combo_pm_ops = {
2886         SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
2887                            qmp_combo_runtime_resume, NULL)
2888 };
2889
2890 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
2891 {
2892         const struct qmp_phy_cfg *cfg = qmp->cfg;
2893         struct device *dev = qmp->dev;
2894         int num = cfg->num_vregs;
2895         int ret, i;
2896
2897         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2898         if (!qmp->vregs)
2899                 return -ENOMEM;
2900
2901         for (i = 0; i < num; i++)
2902                 qmp->vregs[i].supply = cfg->vreg_list[i].name;
2903
2904         ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
2905         if (ret) {
2906                 dev_err(dev, "failed at devm_regulator_bulk_get\n");
2907                 return ret;
2908         }
2909
2910         for (i = 0; i < num; i++) {
2911                 ret = regulator_set_load(qmp->vregs[i].consumer,
2912                                         cfg->vreg_list[i].enable_load);
2913                 if (ret) {
2914                         dev_err(dev, "failed to set load at %s\n",
2915                                 qmp->vregs[i].supply);
2916                         return ret;
2917                 }
2918         }
2919
2920         return 0;
2921 }
2922
2923 static int qmp_combo_reset_init(struct qmp_combo *qmp)
2924 {
2925         const struct qmp_phy_cfg *cfg = qmp->cfg;
2926         struct device *dev = qmp->dev;
2927         int i;
2928         int ret;
2929
2930         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2931                                    sizeof(*qmp->resets), GFP_KERNEL);
2932         if (!qmp->resets)
2933                 return -ENOMEM;
2934
2935         for (i = 0; i < cfg->num_resets; i++)
2936                 qmp->resets[i].id = cfg->reset_list[i];
2937
2938         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2939         if (ret)
2940                 return dev_err_probe(dev, ret, "failed to get resets\n");
2941
2942         return 0;
2943 }
2944
2945 static int qmp_combo_clk_init(struct qmp_combo *qmp)
2946 {
2947         const struct qmp_phy_cfg *cfg = qmp->cfg;
2948         struct device *dev = qmp->dev;
2949         int num = cfg->num_clks;
2950         int i;
2951
2952         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2953         if (!qmp->clks)
2954                 return -ENOMEM;
2955
2956         for (i = 0; i < num; i++)
2957                 qmp->clks[i].id = cfg->clk_list[i];
2958
2959         return devm_clk_bulk_get(dev, num, qmp->clks);
2960 }
2961
2962 static void phy_clk_release_provider(void *res)
2963 {
2964         of_clk_del_provider(res);
2965 }
2966
2967 /*
2968  * Register a fixed rate pipe clock.
2969  *
2970  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2971  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2972  * by the PHY driver for its operations.
2973  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2974  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2975  * Below picture shows this relationship.
2976  *
2977  *         +---------------+
2978  *         |   PHY block   |<<---------------------------------------+
2979  *         |               |                                         |
2980  *         |   +-------+   |                   +-----+               |
2981  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2982  *    clk  |   +-------+   |                   +-----+
2983  *         +---------------+
2984  */
2985 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
2986 {
2987         struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2988         struct clk_init_data init = { };
2989         char name[64];
2990
2991         snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
2992         init.name = name;
2993         init.ops = &clk_fixed_rate_ops;
2994
2995         /* controllers using QMP phys use 125MHz pipe clock interface */
2996         fixed->fixed_rate = 125000000;
2997         fixed->hw.init = &init;
2998
2999         return devm_clk_hw_register(qmp->dev, &fixed->hw);
3000 }
3001
3002 /*
3003  * Display Port PLL driver block diagram for branch clocks
3004  *
3005  *              +------------------------------+
3006  *              |         DP_VCO_CLK           |
3007  *              |                              |
3008  *              |    +-------------------+     |
3009  *              |    |   (DP PLL/VCO)    |     |
3010  *              |    +---------+---------+     |
3011  *              |              v               |
3012  *              |   +----------+-----------+   |
3013  *              |   | hsclk_divsel_clk_src |   |
3014  *              |   +----------+-----------+   |
3015  *              +------------------------------+
3016  *                              |
3017  *          +---------<---------v------------>----------+
3018  *          |                                           |
3019  * +--------v----------------+                          |
3020  * |    dp_phy_pll_link_clk  |                          |
3021  * |     link_clk            |                          |
3022  * +--------+----------------+                          |
3023  *          |                                           |
3024  *          |                                           |
3025  *          v                                           v
3026  * Input to DISPCC block                                |
3027  * for link clk, crypto clk                             |
3028  * and interface clock                                  |
3029  *                                                      |
3030  *                                                      |
3031  *      +--------<------------+-----------------+---<---+
3032  *      |                     |                 |
3033  * +----v---------+  +--------v-----+  +--------v------+
3034  * | vco_divided  |  | vco_divided  |  | vco_divided   |
3035  * |    _clk_src  |  |    _clk_src  |  |    _clk_src   |
3036  * |              |  |              |  |               |
3037  * |divsel_six    |  |  divsel_two  |  |  divsel_four  |
3038  * +-------+------+  +-----+--------+  +--------+------+
3039  *         |                 |                  |
3040  *         v---->----------v-------------<------v
3041  *                         |
3042  *              +----------+-----------------+
3043  *              |   dp_phy_pll_vco_div_clk   |
3044  *              +---------+------------------+
3045  *                        |
3046  *                        v
3047  *              Input to DISPCC block
3048  *              for DP pixel clock
3049  *
3050  */
3051 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3052 {
3053         switch (req->rate) {
3054         case 1620000000UL / 2:
3055         case 2700000000UL / 2:
3056         /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3057                 return 0;
3058         default:
3059                 return -EINVAL;
3060         }
3061 }
3062
3063 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3064 {
3065         const struct qmp_combo *qmp;
3066         const struct phy_configure_opts_dp *dp_opts;
3067
3068         qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3069         dp_opts = &qmp->dp_opts;
3070
3071         switch (dp_opts->link_rate) {
3072         case 1620:
3073                 return 1620000000UL / 2;
3074         case 2700:
3075                 return 2700000000UL / 2;
3076         case 5400:
3077                 return 5400000000UL / 4;
3078         case 8100:
3079                 return 8100000000UL / 6;
3080         default:
3081                 return 0;
3082         }
3083 }
3084
3085 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3086         .determine_rate = qmp_dp_pixel_clk_determine_rate,
3087         .recalc_rate    = qmp_dp_pixel_clk_recalc_rate,
3088 };
3089
3090 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3091 {
3092         switch (req->rate) {
3093         case 162000000:
3094         case 270000000:
3095         case 540000000:
3096         case 810000000:
3097                 return 0;
3098         default:
3099                 return -EINVAL;
3100         }
3101 }
3102
3103 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3104 {
3105         const struct qmp_combo *qmp;
3106         const struct phy_configure_opts_dp *dp_opts;
3107
3108         qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3109         dp_opts = &qmp->dp_opts;
3110
3111         switch (dp_opts->link_rate) {
3112         case 1620:
3113         case 2700:
3114         case 5400:
3115         case 8100:
3116                 return dp_opts->link_rate * 100000;
3117         default:
3118                 return 0;
3119         }
3120 }
3121
3122 static const struct clk_ops qmp_dp_link_clk_ops = {
3123         .determine_rate = qmp_dp_link_clk_determine_rate,
3124         .recalc_rate    = qmp_dp_link_clk_recalc_rate,
3125 };
3126
3127 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3128 {
3129         struct qmp_combo *qmp = data;
3130         unsigned int idx = clkspec->args[0];
3131
3132         if (idx >= 2) {
3133                 pr_err("%s: invalid index %u\n", __func__, idx);
3134                 return ERR_PTR(-EINVAL);
3135         }
3136
3137         if (idx == 0)
3138                 return &qmp->dp_link_hw;
3139
3140         return &qmp->dp_pixel_hw;
3141 }
3142
3143 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3144 {
3145         struct clk_init_data init = { };
3146         char name[64];
3147         int ret;
3148
3149         snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3150         init.ops = &qmp_dp_link_clk_ops;
3151         init.name = name;
3152         qmp->dp_link_hw.init = &init;
3153         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3154         if (ret)
3155                 return ret;
3156
3157         snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3158         init.ops = &qmp_dp_pixel_clk_ops;
3159         init.name = name;
3160         qmp->dp_pixel_hw.init = &init;
3161         ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3162         if (ret)
3163                 return ret;
3164
3165         return 0;
3166 }
3167
3168 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3169 {
3170         struct qmp_combo *qmp = data;
3171
3172         switch (clkspec->args[0]) {
3173         case QMP_USB43DP_USB3_PIPE_CLK:
3174                 return &qmp->pipe_clk_fixed.hw;
3175         case QMP_USB43DP_DP_LINK_CLK:
3176                 return &qmp->dp_link_hw;
3177         case QMP_USB43DP_DP_VCO_DIV_CLK:
3178                 return &qmp->dp_pixel_hw;
3179         }
3180
3181         return ERR_PTR(-EINVAL);
3182 }
3183
3184 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3185                                         struct device_node *dp_np)
3186 {
3187         int ret;
3188
3189         ret = phy_pipe_clk_register(qmp, usb_np);
3190         if (ret)
3191                 return ret;
3192
3193         ret = phy_dp_clks_register(qmp, dp_np);
3194         if (ret)
3195                 return ret;
3196
3197         /*
3198          * Register a single provider for bindings without child nodes.
3199          */
3200         if (usb_np == qmp->dev->of_node)
3201                 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3202
3203         /*
3204          * Register multiple providers for legacy bindings with child nodes.
3205          */
3206         ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3207                                         &qmp->pipe_clk_fixed.hw);
3208         if (ret)
3209                 return ret;
3210
3211         /*
3212          * Roll a devm action because the clock provider is the child node, but
3213          * the child node is not actually a device.
3214          */
3215         ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3216         if (ret)
3217                 return ret;
3218
3219         ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3220         if (ret)
3221                 return ret;
3222
3223         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3224 }
3225
3226 #if IS_ENABLED(CONFIG_TYPEC)
3227 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3228                                       enum typec_orientation orientation)
3229 {
3230         struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3231         const struct qmp_phy_cfg *cfg = qmp->cfg;
3232
3233         if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3234                 return 0;
3235
3236         mutex_lock(&qmp->phy_mutex);
3237         qmp->orientation = orientation;
3238
3239         if (qmp->init_count) {
3240                 if (qmp->usb_init_count)
3241                         qmp_combo_usb_power_off(qmp->usb_phy);
3242                 qmp_combo_com_exit(qmp, true);
3243
3244                 qmp_combo_com_init(qmp, true);
3245                 if (qmp->usb_init_count)
3246                         qmp_combo_usb_power_on(qmp->usb_phy);
3247                 if (qmp->dp_init_count)
3248                         cfg->dp_aux_init(qmp);
3249         }
3250         mutex_unlock(&qmp->phy_mutex);
3251
3252         return 0;
3253 }
3254
3255 static void qmp_combo_typec_unregister(void *data)
3256 {
3257         struct qmp_combo *qmp = data;
3258
3259         typec_switch_unregister(qmp->sw);
3260 }
3261
3262 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3263 {
3264         struct typec_switch_desc sw_desc = {};
3265         struct device *dev = qmp->dev;
3266
3267         sw_desc.drvdata = qmp;
3268         sw_desc.fwnode = dev->fwnode;
3269         sw_desc.set = qmp_combo_typec_switch_set;
3270         qmp->sw = typec_switch_register(dev, &sw_desc);
3271         if (IS_ERR(qmp->sw)) {
3272                 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3273                 return PTR_ERR(qmp->sw);
3274         }
3275
3276         return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp);
3277 }
3278 #else
3279 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3280 {
3281         return 0;
3282 }
3283 #endif
3284
3285 #if IS_ENABLED(CONFIG_DRM)
3286 static int qmp_combo_bridge_attach(struct drm_bridge *bridge,
3287                                    enum drm_bridge_attach_flags flags)
3288 {
3289         struct qmp_combo *qmp = container_of(bridge, struct qmp_combo, bridge);
3290         struct drm_bridge *next_bridge;
3291
3292         if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
3293                 return -EINVAL;
3294
3295         next_bridge = devm_drm_of_get_bridge(qmp->dev, qmp->dev->of_node, 0, 0);
3296         if (IS_ERR(next_bridge)) {
3297                 dev_err(qmp->dev, "failed to acquire drm_bridge: %pe\n", next_bridge);
3298                 return PTR_ERR(next_bridge);
3299         }
3300
3301         return drm_bridge_attach(bridge->encoder, next_bridge, bridge,
3302                                  DRM_BRIDGE_ATTACH_NO_CONNECTOR);
3303 }
3304
3305 static const struct drm_bridge_funcs qmp_combo_bridge_funcs = {
3306         .attach = qmp_combo_bridge_attach,
3307 };
3308
3309 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp)
3310 {
3311         qmp->bridge.funcs = &qmp_combo_bridge_funcs;
3312         qmp->bridge.of_node = qmp->dev->of_node;
3313
3314         return devm_drm_bridge_add(qmp->dev, &qmp->bridge);
3315 }
3316 #else
3317 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp)
3318 {
3319         return 0;
3320 }
3321 #endif
3322
3323 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
3324 {
3325         struct device *dev = qmp->dev;
3326
3327         /*
3328          * Get memory resources from the DP child node:
3329          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3330          * tx2 -> 3; rx2 -> 4
3331          *
3332          * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3333          * implementation.
3334          */
3335         qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3336         if (IS_ERR(qmp->dp_tx))
3337                 return PTR_ERR(qmp->dp_tx);
3338
3339         qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3340         if (IS_ERR(qmp->dp_dp_phy))
3341                 return PTR_ERR(qmp->dp_dp_phy);
3342
3343         qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3344         if (IS_ERR(qmp->dp_tx2))
3345                 return PTR_ERR(qmp->dp_tx2);
3346
3347         return 0;
3348 }
3349
3350 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
3351 {
3352         const struct qmp_phy_cfg *cfg = qmp->cfg;
3353         struct device *dev = qmp->dev;
3354
3355         /*
3356          * Get memory resources from the USB child node:
3357          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3358          * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3359          */
3360         qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3361         if (IS_ERR(qmp->tx))
3362                 return PTR_ERR(qmp->tx);
3363
3364         qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3365         if (IS_ERR(qmp->rx))
3366                 return PTR_ERR(qmp->rx);
3367
3368         qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3369         if (IS_ERR(qmp->pcs))
3370                 return PTR_ERR(qmp->pcs);
3371
3372         if (cfg->pcs_usb_offset)
3373                 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3374
3375         qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3376         if (IS_ERR(qmp->tx2))
3377                 return PTR_ERR(qmp->tx2);
3378
3379         qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3380         if (IS_ERR(qmp->rx2))
3381                 return PTR_ERR(qmp->rx2);
3382
3383         qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3384         if (IS_ERR(qmp->pcs_misc)) {
3385                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3386                 qmp->pcs_misc = NULL;
3387         }
3388
3389         qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3390         if (IS_ERR(qmp->pipe_clk)) {
3391                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3392                                      "failed to get pipe clock\n");
3393         }
3394
3395         return 0;
3396 }
3397
3398 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3399                                         struct device_node *dp_np)
3400 {
3401         struct platform_device *pdev = to_platform_device(qmp->dev);
3402         int ret;
3403
3404         qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3405         if (IS_ERR(qmp->serdes))
3406                 return PTR_ERR(qmp->serdes);
3407
3408         qmp->com = devm_platform_ioremap_resource(pdev, 1);
3409         if (IS_ERR(qmp->com))
3410                 return PTR_ERR(qmp->com);
3411
3412         qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3413         if (IS_ERR(qmp->dp_serdes))
3414                 return PTR_ERR(qmp->dp_serdes);
3415
3416         ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np);
3417         if (ret)
3418                 return ret;
3419
3420         ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np);
3421         if (ret)
3422                 return ret;
3423
3424         return 0;
3425 }
3426
3427 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3428 {
3429         struct platform_device *pdev = to_platform_device(qmp->dev);
3430         const struct qmp_phy_cfg *cfg = qmp->cfg;
3431         const struct qmp_combo_offsets *offs = cfg->offsets;
3432         struct device *dev = qmp->dev;
3433         void __iomem *base;
3434
3435         if (!offs)
3436                 return -EINVAL;
3437
3438         base = devm_platform_ioremap_resource(pdev, 0);
3439         if (IS_ERR(base))
3440                 return PTR_ERR(base);
3441
3442         qmp->com = base + offs->com;
3443         qmp->tx = base + offs->txa;
3444         qmp->rx = base + offs->rxa;
3445         qmp->tx2 = base + offs->txb;
3446         qmp->rx2 = base + offs->rxb;
3447
3448         qmp->serdes = base + offs->usb3_serdes;
3449         qmp->pcs_misc = base + offs->usb3_pcs_misc;
3450         qmp->pcs = base + offs->usb3_pcs;
3451         qmp->pcs_usb = base + offs->usb3_pcs_usb;
3452
3453         qmp->dp_serdes = base + offs->dp_serdes;
3454         if (offs->dp_txa) {
3455                 qmp->dp_tx = base + offs->dp_txa;
3456                 qmp->dp_tx2 = base + offs->dp_txb;
3457         } else {
3458                 qmp->dp_tx = base + offs->txa;
3459                 qmp->dp_tx2 = base + offs->txb;
3460         }
3461         qmp->dp_dp_phy = base + offs->dp_dp_phy;
3462
3463         qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3464         if (IS_ERR(qmp->pipe_clk)) {
3465                 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3466                                 "failed to get usb3_pipe clock\n");
3467         }
3468
3469         return 0;
3470 }
3471
3472 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args)
3473 {
3474         struct qmp_combo *qmp = dev_get_drvdata(dev);
3475
3476         if (args->args_count == 0)
3477                 return ERR_PTR(-EINVAL);
3478
3479         switch (args->args[0]) {
3480         case QMP_USB43DP_USB3_PHY:
3481                 return qmp->usb_phy;
3482         case QMP_USB43DP_DP_PHY:
3483                 return qmp->dp_phy;
3484         }
3485
3486         return ERR_PTR(-EINVAL);
3487 }
3488
3489 static int qmp_combo_probe(struct platform_device *pdev)
3490 {
3491         struct qmp_combo *qmp;
3492         struct device *dev = &pdev->dev;
3493         struct device_node *dp_np, *usb_np;
3494         struct phy_provider *phy_provider;
3495         int ret;
3496
3497         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3498         if (!qmp)
3499                 return -ENOMEM;
3500
3501         qmp->dev = dev;
3502
3503         qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3504
3505         qmp->cfg = of_device_get_match_data(dev);
3506         if (!qmp->cfg)
3507                 return -EINVAL;
3508
3509         mutex_init(&qmp->phy_mutex);
3510
3511         ret = qmp_combo_clk_init(qmp);
3512         if (ret)
3513                 return ret;
3514
3515         ret = qmp_combo_reset_init(qmp);
3516         if (ret)
3517                 return ret;
3518
3519         ret = qmp_combo_vreg_init(qmp);
3520         if (ret)
3521                 return ret;
3522
3523         ret = qmp_combo_typec_switch_register(qmp);
3524         if (ret)
3525                 return ret;
3526
3527         ret = qmp_combo_dp_register_bridge(qmp);
3528         if (ret)
3529                 return ret;
3530
3531         /* Check for legacy binding with child nodes. */
3532         usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
3533         if (usb_np) {
3534                 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3535                 if (!dp_np) {
3536                         of_node_put(usb_np);
3537                         return -EINVAL;
3538                 }
3539
3540                 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3541         } else {
3542                 usb_np = of_node_get(dev->of_node);
3543                 dp_np = of_node_get(dev->of_node);
3544
3545                 ret = qmp_combo_parse_dt(qmp);
3546         }
3547         if (ret)
3548                 goto err_node_put;
3549
3550         pm_runtime_set_active(dev);
3551         ret = devm_pm_runtime_enable(dev);
3552         if (ret)
3553                 goto err_node_put;
3554         /*
3555          * Prevent runtime pm from being ON by default. Users can enable
3556          * it using power/control in sysfs.
3557          */
3558         pm_runtime_forbid(dev);
3559
3560         ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
3561         if (ret)
3562                 goto err_node_put;
3563
3564         qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3565         if (IS_ERR(qmp->usb_phy)) {
3566                 ret = PTR_ERR(qmp->usb_phy);
3567                 dev_err(dev, "failed to create USB PHY: %d\n", ret);
3568                 goto err_node_put;
3569         }
3570
3571         phy_set_drvdata(qmp->usb_phy, qmp);
3572
3573         qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3574         if (IS_ERR(qmp->dp_phy)) {
3575                 ret = PTR_ERR(qmp->dp_phy);
3576                 dev_err(dev, "failed to create DP PHY: %d\n", ret);
3577                 goto err_node_put;
3578         }
3579
3580         phy_set_drvdata(qmp->dp_phy, qmp);
3581
3582         dev_set_drvdata(dev, qmp);
3583
3584         if (usb_np == dev->of_node)
3585                 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3586         else
3587                 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3588
3589         of_node_put(usb_np);
3590         of_node_put(dp_np);
3591
3592         return PTR_ERR_OR_ZERO(phy_provider);
3593
3594 err_node_put:
3595         of_node_put(usb_np);
3596         of_node_put(dp_np);
3597         return ret;
3598 }
3599
3600 static const struct of_device_id qmp_combo_of_match_table[] = {
3601         {
3602                 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3603                 .data = &sc7180_usb3dpphy_cfg,
3604         },
3605         {
3606                 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3607                 .data = &sc8180x_usb3dpphy_cfg,
3608         },
3609         {
3610                 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3611                 .data = &sc8280xp_usb43dpphy_cfg,
3612         },
3613         {
3614                 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3615                 .data = &sdm845_usb3dpphy_cfg,
3616         },
3617         {
3618                 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3619                 .data = &sm6350_usb3dpphy_cfg,
3620         },
3621         {
3622                 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3623                 .data = &sm8250_usb3dpphy_cfg,
3624         },
3625         {
3626                 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3627                 .data = &sm8350_usb3dpphy_cfg,
3628         },
3629         {
3630                 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3631                 .data = &sm8350_usb3dpphy_cfg,
3632         },
3633         {
3634                 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3635                 .data = &sm8550_usb3dpphy_cfg,
3636         },
3637         { }
3638 };
3639 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3640
3641 static struct platform_driver qmp_combo_driver = {
3642         .probe          = qmp_combo_probe,
3643         .driver = {
3644                 .name   = "qcom-qmp-combo-phy",
3645                 .pm     = &qmp_combo_pm_ops,
3646                 .of_match_table = qmp_combo_of_match_table,
3647         },
3648 };
3649
3650 module_platform_driver(qmp_combo_driver);
3651
3652 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3653 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
3654 MODULE_LICENSE("GPL v2");