1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 #include <generic-phy.h>
16 #include <linux/bitops.h>
17 #include <power/regulator.h>
19 /* USBPHYC registers */
20 #define STM32_USBPHYC_PLL 0x0
21 #define STM32_USBPHYC_MISC 0x8
23 /* STM32_USBPHYC_PLL bit fields */
24 #define PLLNDIV GENMASK(6, 0)
25 #define PLLNDIV_SHIFT 0
26 #define PLLFRACIN GENMASK(25, 10)
27 #define PLLFRACIN_SHIFT 10
29 #define PLLSTRB BIT(27)
30 #define PLLSTRBYP BIT(28)
31 #define PLLFRACCTL BIT(29)
32 #define PLLDITHEN0 BIT(30)
33 #define PLLDITHEN1 BIT(31)
35 /* STM32_USBPHYC_MISC bit fields */
36 #define SWITHOST BIT(0)
40 #define PLL_LOCK_TIME_US 100
41 #define PLL_PWR_DOWN_TIME_US 5
42 #define PLL_FVCO 2880 /* in MHz */
43 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
44 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
51 struct stm32_usbphyc {
54 struct udevice *vdda1v1;
55 struct udevice *vdda1v8;
56 struct stm32_usbphyc_phy {
63 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
64 struct pll_params *pll_params)
66 unsigned long long fvco, ndiv, frac;
69 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
71 * | NDIV = integer part of input bits to set the LDF
72 * | FRACT = fractional part of input bits to set the LDF
73 * => PLLNDIV = integer part of (FVCO / (INFF*2))
74 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
75 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
77 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
80 do_div(ndiv, (clk_rate * 2));
81 pll_params->ndiv = (u8)ndiv;
83 frac = fvco * (1 << 16);
84 do_div(frac, (clk_rate * 2));
85 frac = frac - (ndiv * (1 << 16));
86 pll_params->frac = (u16)frac;
89 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
91 struct pll_params pll_params;
92 u32 clk_rate = clk_get_rate(&usbphyc->clk);
95 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
96 pr_debug("%s: input clk freq (%dHz) out of range\n",
101 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
103 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
104 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
106 if (pll_params.frac) {
107 usbphyc_pll |= PLLFRACCTL;
108 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
112 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
114 pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
115 clk_rate, pll_params.ndiv, pll_params.frac);
120 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
124 for (i = 0; i < MAX_PHYS; i++) {
125 if (usbphyc->phys[i].init)
132 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
136 for (i = 0; i < MAX_PHYS; i++) {
137 if (usbphyc->phys[i].powered)
144 static int stm32_usbphyc_phy_init(struct phy *phy)
146 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
147 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
148 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
152 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
153 /* Check if one phy port has already configured the pll */
154 if (pllen && stm32_usbphyc_is_init(usbphyc))
157 if (usbphyc->vdda1v1) {
158 ret = regulator_set_enable(usbphyc->vdda1v1, true);
163 if (usbphyc->vdda1v8) {
164 ret = regulator_set_enable(usbphyc->vdda1v8, true);
170 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
171 udelay(PLL_PWR_DOWN_TIME_US);
174 ret = stm32_usbphyc_pll_init(usbphyc);
178 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
181 * We must wait PLL_LOCK_TIME_US before checking that PLLEN
184 udelay(PLL_LOCK_TIME_US);
186 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
190 usbphyc_phy->init = true;
195 static int stm32_usbphyc_phy_exit(struct phy *phy)
197 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
198 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
201 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
202 usbphyc_phy->init = false;
204 /* Check if other phy port requires pllen */
205 if (stm32_usbphyc_is_init(usbphyc))
208 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
211 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
214 udelay(PLL_PWR_DOWN_TIME_US);
216 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
219 if (usbphyc->vdda1v1) {
220 ret = regulator_set_enable(usbphyc->vdda1v1, false);
225 if (usbphyc->vdda1v8) {
226 ret = regulator_set_enable(usbphyc->vdda1v8, false);
234 static int stm32_usbphyc_phy_power_on(struct phy *phy)
236 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
237 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
240 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
241 if (usbphyc_phy->vdd) {
242 ret = regulator_set_enable(usbphyc_phy->vdd, true);
247 usbphyc_phy->powered = true;
252 static int stm32_usbphyc_phy_power_off(struct phy *phy)
254 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
255 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
258 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
259 usbphyc_phy->powered = false;
261 if (stm32_usbphyc_is_powered(usbphyc))
264 if (usbphyc_phy->vdd) {
265 ret = regulator_set_enable(usbphyc_phy->vdd, false);
273 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
275 struct udevice **regulator)
277 struct ofnode_phandle_args regulator_phandle;
280 ret = ofnode_parse_phandle_with_args(node, supply_name,
284 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
288 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
289 regulator_phandle.node,
293 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
300 static int stm32_usbphyc_of_xlate(struct phy *phy,
301 struct ofnode_phandle_args *args)
303 if (args->args_count < 1)
306 if (args->args[0] >= MAX_PHYS)
309 phy->id = args->args[0];
311 if ((phy->id == 0 && args->args_count != 1) ||
312 (phy->id == 1 && args->args_count != 2)) {
313 dev_err(dev, "invalid number of cells for phy port%ld\n",
321 static const struct phy_ops stm32_usbphyc_phy_ops = {
322 .init = stm32_usbphyc_phy_init,
323 .exit = stm32_usbphyc_phy_exit,
324 .power_on = stm32_usbphyc_phy_power_on,
325 .power_off = stm32_usbphyc_phy_power_off,
326 .of_xlate = stm32_usbphyc_of_xlate,
329 static int stm32_usbphyc_probe(struct udevice *dev)
331 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
332 struct reset_ctl reset;
336 usbphyc->base = dev_read_addr(dev);
337 if (usbphyc->base == FDT_ADDR_T_NONE)
341 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
345 ret = clk_enable(&usbphyc->clk);
350 ret = reset_get_by_index(dev, 0, &reset);
352 reset_assert(&reset);
354 reset_deassert(&reset);
357 /* get usbphyc regulator */
358 ret = device_get_supply_regulator(dev, "vdda1v1-supply",
361 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
365 ret = device_get_supply_regulator(dev, "vdda1v8-supply",
368 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
373 * parse all PHY subnodes in order to populate regulator associated
376 node = dev_read_first_subnode(dev);
377 for (i = 0; i < MAX_PHYS; i++) {
378 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
380 usbphyc_phy->init = false;
381 usbphyc_phy->powered = false;
382 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
387 node = dev_read_next_subnode(node);
390 /* Check if second port has to be used for host controller */
391 if (dev_read_bool(dev, "st,port2-switch-to-host"))
392 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
397 static const struct udevice_id stm32_usbphyc_of_match[] = {
398 { .compatible = "st,stm32mp1-usbphyc", },
402 U_BOOT_DRIVER(stm32_usb_phyc) = {
403 .name = "stm32-usbphyc",
405 .of_match = stm32_usbphyc_of_match,
406 .ops = &stm32_usbphyc_phy_ops,
407 .probe = stm32_usbphyc_probe,
408 .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),