1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
6 #define LOG_CATEGORY UCLASS_PHY
10 #include <clk-uclass.h>
14 #include <generic-phy.h>
20 #include <dm/device_compat.h>
22 #include <dm/of_access.h>
23 #include <linux/bitfield.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <power/regulator.h>
28 /* USBPHYC registers */
29 #define STM32_USBPHYC_PLL 0x0
30 #define STM32_USBPHYC_MISC 0x8
31 #define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
33 /* STM32_USBPHYC_PLL bit fields */
34 #define PLLNDIV GENMASK(6, 0)
35 #define PLLNDIV_SHIFT 0
36 #define PLLFRACIN GENMASK(25, 10)
37 #define PLLFRACIN_SHIFT 10
39 #define PLLSTRB BIT(27)
40 #define PLLSTRBYP BIT(28)
41 #define PLLFRACCTL BIT(29)
42 #define PLLDITHEN0 BIT(30)
43 #define PLLDITHEN1 BIT(31)
45 /* STM32_USBPHYC_MISC bit fields */
46 #define SWITHOST BIT(0)
48 /* STM32_USBPHYC_TUNE bit fields */
49 #define INCURREN BIT(0)
50 #define INCURRINT BIT(1)
51 #define LFSCAPEN BIT(2)
52 #define HSDRVSLEW BIT(3)
53 #define HSDRVDCCUR BIT(4)
54 #define HSDRVDCLEV BIT(5)
55 #define HSDRVCURINCR BIT(6)
56 #define FSDRVRFADJ BIT(7)
57 #define HSDRVRFRED BIT(8)
58 #define HSDRVCHKITRM GENMASK(12, 9)
59 #define HSDRVCHKZTRM GENMASK(14, 13)
60 #define OTPCOMP GENMASK(19, 15)
61 #define SQLCHCTL GENMASK(21, 20)
62 #define HDRXGNEQEN BIT(22)
63 #define HSRXOFF GENMASK(24, 23)
64 #define HSFALLPREEM BIT(25)
65 #define SHTCCTCTLPROT BIT(26)
66 #define STAGSEL BIT(27)
70 /* max 100 us for PLL lock and 100 us for PHY init */
71 #define PLL_INIT_TIME_US 200
72 #define PLL_PWR_DOWN_TIME_US 5
73 #define PLL_FVCO 2880 /* in MHz */
74 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
75 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
78 #define USBPHYC_CLK48_FREQ 48000000 /* in Hz */
112 enum impedance_trim {
131 RX_OFFSET_PLUS_10_MV,
132 RX_OFFSET_MINUS_5_MV,
141 struct stm32_usbphyc {
144 struct udevice *vdda1v1;
145 struct udevice *vdda1v8;
146 struct stm32_usbphyc_phy {
148 struct udevice *vbus;
155 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
156 struct pll_params *pll_params)
158 unsigned long long fvco, ndiv, frac;
161 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
163 * | NDIV = integer part of input bits to set the LDF
164 * | FRACT = fractional part of input bits to set the LDF
165 * => PLLNDIV = integer part of (FVCO / (INFF*2))
166 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
167 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
169 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
172 do_div(ndiv, (clk_rate * 2));
173 pll_params->ndiv = (u8)ndiv;
175 frac = fvco * (1 << 16);
176 do_div(frac, (clk_rate * 2));
177 frac = frac - (ndiv * (1 << 16));
178 pll_params->frac = (u16)frac;
181 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
183 struct pll_params pll_params;
184 u32 clk_rate = clk_get_rate(&usbphyc->clk);
187 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
188 log_debug("input clk freq (%dHz) out of range\n",
193 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
195 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
196 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
198 if (pll_params.frac) {
199 usbphyc_pll |= PLLFRACCTL;
200 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
204 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
206 log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
207 clk_rate, pll_params.ndiv, pll_params.frac);
212 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
216 for (i = 0; i < MAX_PHYS; i++) {
217 if (usbphyc->phys[i].powered)
224 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
226 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
230 /* Check if one consumer has already configured the pll */
231 if (pllen && usbphyc->n_pll_cons) {
232 usbphyc->n_pll_cons++;
236 if (usbphyc->vdda1v1) {
237 ret = regulator_set_enable(usbphyc->vdda1v1, true);
242 if (usbphyc->vdda1v8) {
243 ret = regulator_set_enable(usbphyc->vdda1v8, true);
249 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
250 udelay(PLL_PWR_DOWN_TIME_US);
253 ret = stm32_usbphyc_pll_init(usbphyc);
257 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
259 /* We must wait PLL_INIT_TIME_US before using PHY */
260 udelay(PLL_INIT_TIME_US);
262 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
265 usbphyc->n_pll_cons++;
270 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
274 usbphyc->n_pll_cons--;
276 /* Check if other consumer requires pllen */
277 if (usbphyc->n_pll_cons)
280 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
283 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
286 udelay(PLL_PWR_DOWN_TIME_US);
288 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
291 if (usbphyc->vdda1v1) {
292 ret = regulator_set_enable(usbphyc->vdda1v1, false);
297 if (usbphyc->vdda1v8) {
298 ret = regulator_set_enable(usbphyc->vdda1v8, false);
306 static int stm32_usbphyc_phy_init(struct phy *phy)
308 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
309 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
312 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
313 if (usbphyc_phy->init)
316 ret = stm32_usbphyc_pll_enable(usbphyc);
320 usbphyc_phy->init = true;
325 static int stm32_usbphyc_phy_exit(struct phy *phy)
327 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
328 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
331 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
332 if (!usbphyc_phy->init)
335 ret = stm32_usbphyc_pll_disable(usbphyc);
337 usbphyc_phy->init = false;
342 static int stm32_usbphyc_phy_power_on(struct phy *phy)
344 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
345 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
348 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
349 if (usbphyc_phy->vdd) {
350 ret = regulator_set_enable(usbphyc_phy->vdd, true);
354 if (usbphyc_phy->vbus) {
355 ret = regulator_set_enable(usbphyc_phy->vbus, true);
360 usbphyc_phy->powered = true;
365 static int stm32_usbphyc_phy_power_off(struct phy *phy)
367 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
368 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
371 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
372 usbphyc_phy->powered = false;
374 if (stm32_usbphyc_is_powered(usbphyc))
377 if (usbphyc_phy->vbus) {
378 ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
382 if (usbphyc_phy->vdd) {
383 ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
391 static int stm32_usbphyc_get_regulator(ofnode node,
393 struct udevice **regulator)
395 struct ofnode_phandle_args regulator_phandle;
398 ret = ofnode_parse_phandle_with_args(node, supply_name,
404 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
405 regulator_phandle.node,
413 static int stm32_usbphyc_of_xlate(struct phy *phy,
414 struct ofnode_phandle_args *args)
416 if (args->args_count < 1)
419 if (args->args[0] >= MAX_PHYS)
422 phy->id = args->args[0];
424 if ((phy->id == 0 && args->args_count != 1) ||
425 (phy->id == 1 && args->args_count != 2)) {
426 dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
434 static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
436 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
437 u32 reg = STM32_USBPHYC_TUNE(index);
438 u32 otpcomp, val, tune = 0;
441 /* Backup OTP compensation code */
442 otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
444 ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
445 if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
446 val = (val == BOOST_2000_UA) ? 1 : 0;
447 tune |= INCURREN | FIELD_PREP(INCURRINT, val);
448 } else if (ret != -EINVAL) {
449 dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
452 if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
455 if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
458 ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
459 if (!ret && val < DC_MAX) {
460 if (val == DC_MINUS_5_TO_7_MV) {
463 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
464 tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
466 } else if (ret != -EINVAL) {
467 dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
470 if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
473 if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
476 ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
477 if (!ret && val < CUR_MAX)
478 tune |= FIELD_PREP(HSDRVCHKITRM, val);
479 else if (ret != -EINVAL)
480 dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
482 ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
483 if (!ret && val < IMP_MAX)
484 tune |= FIELD_PREP(HSDRVCHKZTRM, val);
485 else if (ret != -EINVAL)
486 dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
488 ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
489 if (!ret && val < SQLCH_MAX)
490 tune |= FIELD_PREP(SQLCHCTL, val);
491 else if (ret != -EINVAL)
492 dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
494 if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
497 ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
498 if (!ret && val < RX_OFFSET_MAX)
499 tune |= FIELD_PREP(HSRXOFF, val);
500 else if (ret != -EINVAL)
501 dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
503 if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
506 if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
507 tune |= SHTCCTCTLPROT;
509 if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
512 /* Restore OTP compensation code */
513 tune |= FIELD_PREP(OTPCOMP, otpcomp);
515 writel(tune, usbphyc->base + reg);
518 static const struct phy_ops stm32_usbphyc_phy_ops = {
519 .init = stm32_usbphyc_phy_init,
520 .exit = stm32_usbphyc_phy_exit,
521 .power_on = stm32_usbphyc_phy_power_on,
522 .power_off = stm32_usbphyc_phy_power_off,
523 .of_xlate = stm32_usbphyc_of_xlate,
526 static int stm32_usbphyc_bind(struct udevice *dev)
530 ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
531 dev_ofnode(dev), NULL);
536 static int stm32_usbphyc_probe(struct udevice *dev)
538 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
539 struct reset_ctl reset;
540 ofnode node, connector;
543 usbphyc->base = dev_read_addr(dev);
544 if (usbphyc->base == FDT_ADDR_T_NONE)
548 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
552 ret = clk_enable(&usbphyc->clk);
557 ret = reset_get_by_index(dev, 0, &reset);
559 reset_assert(&reset);
561 reset_deassert(&reset);
564 /* get usbphyc regulator */
565 ret = device_get_supply_regulator(dev, "vdda1v1-supply",
568 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
572 ret = device_get_supply_regulator(dev, "vdda1v8-supply",
575 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
579 /* parse all PHY subnodes to populate regulator associated to each PHY port */
580 dev_for_each_subnode(node, dev) {
582 struct stm32_usbphyc_phy *usbphyc_phy;
584 phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
585 if (phy_id >= MAX_PHYS) {
586 dev_err(dev, "invalid reg value %llx for %s\n",
587 (fdt64_t)phy_id, ofnode_get_name(node));
591 /* Configure phy tuning */
592 stm32_usbphyc_tuning(dev, node, phy_id);
594 usbphyc_phy = usbphyc->phys + phy_id;
595 usbphyc_phy->init = false;
596 usbphyc_phy->powered = false;
597 ret = stm32_usbphyc_get_regulator(node, "phy-supply",
600 dev_err(dev, "Can't get phy-supply regulator\n");
604 usbphyc_phy->vbus = NULL;
605 connector = ofnode_find_subnode(node, "connector");
606 if (ofnode_valid(connector)) {
607 ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
612 /* Check if second port has to be used for host controller */
613 if (dev_read_bool(dev, "st,port2-switch-to-host"))
614 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
619 static const struct udevice_id stm32_usbphyc_of_match[] = {
620 { .compatible = "st,stm32mp1-usbphyc", },
624 U_BOOT_DRIVER(stm32_usb_phyc) = {
625 .name = "stm32-usbphyc",
627 .of_match = stm32_usbphyc_of_match,
628 .ops = &stm32_usbphyc_phy_ops,
629 .bind = stm32_usbphyc_bind,
630 .probe = stm32_usbphyc_probe,
631 .priv_auto = sizeof(struct stm32_usbphyc),
634 struct stm32_usbphyc_clk {
638 static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
640 return USBPHYC_CLK48_FREQ;
643 static int stm32_usbphyc_clk48_enable(struct clk *clk)
645 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
646 struct stm32_usbphyc *usbphyc;
649 if (usbphyc_clk->enable)
652 usbphyc = dev_get_priv(clk->dev->parent);
654 /* ck_usbo_48m is generated by usbphyc PLL */
655 ret = stm32_usbphyc_pll_enable(usbphyc);
659 usbphyc_clk->enable = true;
664 static int stm32_usbphyc_clk48_disable(struct clk *clk)
666 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
667 struct stm32_usbphyc *usbphyc;
670 if (!usbphyc_clk->enable)
673 usbphyc = dev_get_priv(clk->dev->parent);
675 ret = stm32_usbphyc_pll_disable(usbphyc);
679 usbphyc_clk->enable = false;
684 const struct clk_ops usbphyc_clk48_ops = {
685 .get_rate = stm32_usbphyc_clk48_get_rate,
686 .enable = stm32_usbphyc_clk48_enable,
687 .disable = stm32_usbphyc_clk48_disable,
690 U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
691 .name = "stm32-usbphyc-clk",
693 .ops = &usbphyc_clk48_ops,
694 .priv_auto = sizeof(struct stm32_usbphyc_clk),