1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 #include <generic-phy.h>
16 #include <linux/bitops.h>
17 #include <power/regulator.h>
19 /* USBPHYC registers */
20 #define STM32_USBPHYC_PLL 0x0
21 #define STM32_USBPHYC_MISC 0x8
23 /* STM32_USBPHYC_PLL bit fields */
24 #define PLLNDIV GENMASK(6, 0)
25 #define PLLNDIV_SHIFT 0
26 #define PLLFRACIN GENMASK(25, 10)
27 #define PLLFRACIN_SHIFT 10
29 #define PLLSTRB BIT(27)
30 #define PLLSTRBYP BIT(28)
31 #define PLLFRACCTL BIT(29)
32 #define PLLDITHEN0 BIT(30)
33 #define PLLDITHEN1 BIT(31)
35 /* STM32_USBPHYC_MISC bit fields */
36 #define SWITHOST BIT(0)
40 /* max 100 us for PLL lock and 100 us for PHY init */
41 #define PLL_INIT_TIME_US 200
42 #define PLL_PWR_DOWN_TIME_US 5
43 #define PLL_FVCO 2880 /* in MHz */
44 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
45 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
52 struct stm32_usbphyc {
55 struct udevice *vdda1v1;
56 struct udevice *vdda1v8;
57 struct stm32_usbphyc_phy {
64 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
65 struct pll_params *pll_params)
67 unsigned long long fvco, ndiv, frac;
70 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
72 * | NDIV = integer part of input bits to set the LDF
73 * | FRACT = fractional part of input bits to set the LDF
74 * => PLLNDIV = integer part of (FVCO / (INFF*2))
75 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
76 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
78 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
81 do_div(ndiv, (clk_rate * 2));
82 pll_params->ndiv = (u8)ndiv;
84 frac = fvco * (1 << 16);
85 do_div(frac, (clk_rate * 2));
86 frac = frac - (ndiv * (1 << 16));
87 pll_params->frac = (u16)frac;
90 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
92 struct pll_params pll_params;
93 u32 clk_rate = clk_get_rate(&usbphyc->clk);
96 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
97 pr_debug("%s: input clk freq (%dHz) out of range\n",
102 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
104 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
105 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
107 if (pll_params.frac) {
108 usbphyc_pll |= PLLFRACCTL;
109 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
113 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
115 pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
116 clk_rate, pll_params.ndiv, pll_params.frac);
121 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
125 for (i = 0; i < MAX_PHYS; i++) {
126 if (usbphyc->phys[i].init)
133 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
137 for (i = 0; i < MAX_PHYS; i++) {
138 if (usbphyc->phys[i].powered)
145 static int stm32_usbphyc_phy_init(struct phy *phy)
147 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
148 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
149 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
153 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
154 /* Check if one phy port has already configured the pll */
155 if (pllen && stm32_usbphyc_is_init(usbphyc))
158 if (usbphyc->vdda1v1) {
159 ret = regulator_set_enable(usbphyc->vdda1v1, true);
164 if (usbphyc->vdda1v8) {
165 ret = regulator_set_enable(usbphyc->vdda1v8, true);
171 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
172 udelay(PLL_PWR_DOWN_TIME_US);
175 ret = stm32_usbphyc_pll_init(usbphyc);
179 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
181 /* We must wait PLL_INIT_TIME_US before using PHY */
182 udelay(PLL_INIT_TIME_US);
184 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
188 usbphyc_phy->init = true;
193 static int stm32_usbphyc_phy_exit(struct phy *phy)
195 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
196 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
199 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
200 usbphyc_phy->init = false;
202 /* Check if other phy port requires pllen */
203 if (stm32_usbphyc_is_init(usbphyc))
206 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
209 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
212 udelay(PLL_PWR_DOWN_TIME_US);
214 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
217 if (usbphyc->vdda1v1) {
218 ret = regulator_set_enable(usbphyc->vdda1v1, false);
223 if (usbphyc->vdda1v8) {
224 ret = regulator_set_enable(usbphyc->vdda1v8, false);
232 static int stm32_usbphyc_phy_power_on(struct phy *phy)
234 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
235 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
238 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
239 if (usbphyc_phy->vdd) {
240 ret = regulator_set_enable(usbphyc_phy->vdd, true);
245 usbphyc_phy->powered = true;
250 static int stm32_usbphyc_phy_power_off(struct phy *phy)
252 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
253 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
256 pr_debug("%s phy ID = %lu\n", __func__, phy->id);
257 usbphyc_phy->powered = false;
259 if (stm32_usbphyc_is_powered(usbphyc))
262 if (usbphyc_phy->vdd) {
263 ret = regulator_set_enable(usbphyc_phy->vdd, false);
271 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
273 struct udevice **regulator)
275 struct ofnode_phandle_args regulator_phandle;
278 ret = ofnode_parse_phandle_with_args(node, supply_name,
282 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
286 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
287 regulator_phandle.node,
291 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
298 static int stm32_usbphyc_of_xlate(struct phy *phy,
299 struct ofnode_phandle_args *args)
301 if (args->args_count < 1)
304 if (args->args[0] >= MAX_PHYS)
307 phy->id = args->args[0];
309 if ((phy->id == 0 && args->args_count != 1) ||
310 (phy->id == 1 && args->args_count != 2)) {
311 dev_err(dev, "invalid number of cells for phy port%ld\n",
319 static const struct phy_ops stm32_usbphyc_phy_ops = {
320 .init = stm32_usbphyc_phy_init,
321 .exit = stm32_usbphyc_phy_exit,
322 .power_on = stm32_usbphyc_phy_power_on,
323 .power_off = stm32_usbphyc_phy_power_off,
324 .of_xlate = stm32_usbphyc_of_xlate,
327 static int stm32_usbphyc_probe(struct udevice *dev)
329 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
330 struct reset_ctl reset;
334 usbphyc->base = dev_read_addr(dev);
335 if (usbphyc->base == FDT_ADDR_T_NONE)
339 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
343 ret = clk_enable(&usbphyc->clk);
348 ret = reset_get_by_index(dev, 0, &reset);
350 reset_assert(&reset);
352 reset_deassert(&reset);
355 /* get usbphyc regulator */
356 ret = device_get_supply_regulator(dev, "vdda1v1-supply",
359 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
363 ret = device_get_supply_regulator(dev, "vdda1v8-supply",
366 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
371 * parse all PHY subnodes in order to populate regulator associated
374 node = dev_read_first_subnode(dev);
375 for (i = 0; i < MAX_PHYS; i++) {
376 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
378 usbphyc_phy->init = false;
379 usbphyc_phy->powered = false;
380 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
385 node = dev_read_next_subnode(node);
388 /* Check if second port has to be used for host controller */
389 if (dev_read_bool(dev, "st,port2-switch-to-host"))
390 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
395 static const struct udevice_id stm32_usbphyc_of_match[] = {
396 { .compatible = "st,stm32mp1-usbphyc", },
400 U_BOOT_DRIVER(stm32_usb_phyc) = {
401 .name = "stm32-usbphyc",
403 .of_match = stm32_usbphyc_of_match,
404 .ops = &stm32_usbphyc_phy_ops,
405 .probe = stm32_usbphyc_probe,
406 .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),