drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_PHY
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <div64.h>
  11 #include <dm.h>
  12 #include <fdtdec.h>
  13 #include <generic-phy.h>
  14 #include <log.h>
  15 #include <reset.h>
  16 #include <syscon.h>
  17 #include <usb.h>
  18 #include <asm/io.h>
  19 #include <dm/device_compat.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <power/regulator.h>
  23
  24 /* USBPHYC registers */
  25 #define STM32_USBPHYC_PLL       0x0
  26 #define STM32_USBPHYC_MISC      0x8
  27
  28 /* STM32_USBPHYC_PLL bit fields */
  29 #define PLLNDIV                 GENMASK(6, 0)
  30 #define PLLNDIV_SHIFT           0
  31 #define PLLFRACIN               GENMASK(25, 10)
  32 #define PLLFRACIN_SHIFT         10
  33 #define PLLEN                   BIT(26)
  34 #define PLLSTRB                 BIT(27)
  35 #define PLLSTRBYP               BIT(28)
  36 #define PLLFRACCTL              BIT(29)
  37 #define PLLDITHEN0              BIT(30)
  38 #define PLLDITHEN1              BIT(31)
  39
  40 /* STM32_USBPHYC_MISC bit fields */
  41 #define SWITHOST                BIT(0)
  42
  43 #define MAX_PHYS                2
  44
  45 /* max 100 us for PLL lock and 100 us for PHY init */
  46 #define PLL_INIT_TIME_US        200
  47 #define PLL_PWR_DOWN_TIME_US    5
  48 #define PLL_FVCO                2880     /* in MHz */
  49 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  50 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  51
  52 struct pll_params {
  53         u8 ndiv;
  54         u16 frac;
  55 };
  56
  57 struct stm32_usbphyc {
  58         fdt_addr_t base;
  59         struct clk clk;
  60         struct udevice *vdda1v1;
  61         struct udevice *vdda1v8;
  62         struct stm32_usbphyc_phy {
  63                 struct udevice *vdd;
  64                 struct udevice *vbus;
  65                 bool init;
  66                 bool powered;
  67         } phys[MAX_PHYS];
  68 };
  69
  70 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  71                                          struct pll_params *pll_params)
  72 {
  73         unsigned long long fvco, ndiv, frac;
  74
  75         /*
  76          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  77          *    | FVCO = 2880MHz
  78          *    | NDIV = integer part of input bits to set the LDF
  79          *    | FRACT = fractional part of input bits to set the LDF
  80          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  81          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  82          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  83          */
  84         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  85
  86         ndiv = fvco;
  87         do_div(ndiv, (clk_rate * 2));
  88         pll_params->ndiv = (u8)ndiv;
  89
  90         frac = fvco * (1 << 16);
  91         do_div(frac, (clk_rate * 2));
  92         frac = frac - (ndiv * (1 << 16));
  93         pll_params->frac = (u16)frac;
  94 }
  95
  96 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  97 {
  98         struct pll_params pll_params;
  99         u32 clk_rate = clk_get_rate(&usbphyc->clk);
 100         u32 usbphyc_pll;
 101
 102         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
 103                 log_debug("input clk freq (%dHz) out of range\n",
 104                           clk_rate);
 105                 return -EINVAL;
 106         }
 107
 108         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 109
 110         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 111         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 112
 113         if (pll_params.frac) {
 114                 usbphyc_pll |= PLLFRACCTL;
 115                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 116                                  & PLLFRACIN);
 117         }
 118
 119         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 120
 121         log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
 122                   clk_rate, pll_params.ndiv, pll_params.frac);
 123
 124         return 0;
 125 }
 126
 127 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
 128 {
 129         int i;
 130
 131         for (i = 0; i < MAX_PHYS; i++) {
 132                 if (usbphyc->phys[i].init)
 133                         return true;
 134         }
 135
 136         return false;
 137 }
 138
 139 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 140 {
 141         int i;
 142
 143         for (i = 0; i < MAX_PHYS; i++) {
 144                 if (usbphyc->phys[i].powered)
 145                         return true;
 146         }
 147
 148         return false;
 149 }
 150
 151 static int stm32_usbphyc_phy_init(struct phy *phy)
 152 {
 153         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 154         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 155         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 156                      true : false;
 157         int ret;
 158
 159         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 160         /* Check if one phy port has already configured the pll */
 161         if (pllen && stm32_usbphyc_is_init(usbphyc))
 162                 goto initialized;
 163
 164         if (usbphyc->vdda1v1) {
 165                 ret = regulator_set_enable(usbphyc->vdda1v1, true);
 166                 if (ret)
 167                         return ret;
 168         }
 169
 170         if (usbphyc->vdda1v8) {
 171                 ret = regulator_set_enable(usbphyc->vdda1v8, true);
 172                 if (ret)
 173                         return ret;
 174         }
 175
 176         if (pllen) {
 177                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 178                 udelay(PLL_PWR_DOWN_TIME_US);
 179         }
 180
 181         ret = stm32_usbphyc_pll_init(usbphyc);
 182         if (ret)
 183                 return ret;
 184
 185         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 186
 187         /* We must wait PLL_INIT_TIME_US before using PHY */
 188         udelay(PLL_INIT_TIME_US);
 189
 190         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 191                 return -EIO;
 192
 193 initialized:
 194         usbphyc_phy->init = true;
 195
 196         return 0;
 197 }
 198
 199 static int stm32_usbphyc_phy_exit(struct phy *phy)
 200 {
 201         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 202         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 203         int ret;
 204
 205         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 206         usbphyc_phy->init = false;
 207
 208         /* Check if other phy port requires pllen */
 209         if (stm32_usbphyc_is_init(usbphyc))
 210                 return 0;
 211
 212         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 213
 214         /*
 215          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 216          * bit is still clear
 217          */
 218         udelay(PLL_PWR_DOWN_TIME_US);
 219
 220         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 221                 return -EIO;
 222
 223         if (usbphyc->vdda1v1) {
 224                 ret = regulator_set_enable(usbphyc->vdda1v1, false);
 225                 if (ret)
 226                         return ret;
 227         }
 228
 229         if (usbphyc->vdda1v8) {
 230                 ret = regulator_set_enable(usbphyc->vdda1v8, false);
 231                 if (ret)
 232                         return ret;
 233         }
 234
 235         return 0;
 236 }
 237
 238 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 239 {
 240         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 241         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 242         int ret;
 243
 244         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 245         if (usbphyc_phy->vdd) {
 246                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 247                 if (ret)
 248                         return ret;
 249         }
 250         if (usbphyc_phy->vbus) {
 251                 ret = regulator_set_enable(usbphyc_phy->vbus, true);
 252                 if (ret)
 253                         return ret;
 254         }
 255
 256         usbphyc_phy->powered = true;
 257
 258         return 0;
 259 }
 260
 261 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 262 {
 263         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 264         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 265         int ret;
 266
 267         dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
 268         usbphyc_phy->powered = false;
 269
 270         if (stm32_usbphyc_is_powered(usbphyc))
 271                 return 0;
 272
 273         if (usbphyc_phy->vbus) {
 274                 ret = regulator_set_enable(usbphyc_phy->vbus, false);
 275                 if (ret)
 276                         return ret;
 277         }
 278         if (usbphyc_phy->vdd) {
 279                 ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
 280                 if (ret)
 281                         return ret;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int stm32_usbphyc_get_regulator(ofnode node,
 288                                        char *supply_name,
 289                                        struct udevice **regulator)
 290 {
 291         struct ofnode_phandle_args regulator_phandle;
 292         int ret;
 293
 294         ret = ofnode_parse_phandle_with_args(node, supply_name,
 295                                              NULL, 0, 0,
 296                                              &regulator_phandle);
 297         if (ret)
 298                 return ret;
 299
 300         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 301                                           regulator_phandle.node,
 302                                           regulator);
 303         if (ret)
 304                 return ret;
 305
 306         return 0;
 307 }
 308
 309 static int stm32_usbphyc_of_xlate(struct phy *phy,
 310                                   struct ofnode_phandle_args *args)
 311 {
 312         if (args->args_count < 1)
 313                 return -ENODEV;
 314
 315         if (args->args[0] >= MAX_PHYS)
 316                 return -ENODEV;
 317
 318         phy->id = args->args[0];
 319
 320         if ((phy->id == 0 && args->args_count != 1) ||
 321             (phy->id == 1 && args->args_count != 2)) {
 322                 dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
 323                         phy->id);
 324                 return -EINVAL;
 325         }
 326
 327         return 0;
 328 }
 329
 330 static const struct phy_ops stm32_usbphyc_phy_ops = {
 331         .init = stm32_usbphyc_phy_init,
 332         .exit = stm32_usbphyc_phy_exit,
 333         .power_on = stm32_usbphyc_phy_power_on,
 334         .power_off = stm32_usbphyc_phy_power_off,
 335         .of_xlate = stm32_usbphyc_of_xlate,
 336 };
 337
 338 static int stm32_usbphyc_probe(struct udevice *dev)
 339 {
 340         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 341         struct reset_ctl reset;
 342         ofnode node, connector;
 343         int ret;
 344
 345         usbphyc->base = dev_read_addr(dev);
 346         if (usbphyc->base == FDT_ADDR_T_NONE)
 347                 return -EINVAL;
 348
 349         /* Enable clock */
 350         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 351         if (ret)
 352                 return ret;
 353
 354         ret = clk_enable(&usbphyc->clk);
 355         if (ret)
 356                 return ret;
 357
 358         /* Reset */
 359         ret = reset_get_by_index(dev, 0, &reset);
 360         if (!ret) {
 361                 reset_assert(&reset);
 362                 udelay(2);
 363                 reset_deassert(&reset);
 364         }
 365
 366         /* get usbphyc regulator */
 367         ret = device_get_supply_regulator(dev, "vdda1v1-supply",
 368                                           &usbphyc->vdda1v1);
 369         if (ret) {
 370                 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
 371                 return ret;
 372         }
 373
 374         ret = device_get_supply_regulator(dev, "vdda1v8-supply",
 375                                           &usbphyc->vdda1v8);
 376         if (ret) {
 377                 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
 378                 return ret;
 379         }
 380
 381         /* parse all PHY subnodes to populate regulator associated to each PHY port */
 382         dev_for_each_subnode(node, dev) {
 383                 fdt_addr_t phy_id;
 384                 struct stm32_usbphyc_phy *usbphyc_phy;
 385
 386                 phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
 387                 if (phy_id >= MAX_PHYS) {
 388                         dev_err(dev, "invalid reg value %lx for %s\n",
 389                                 phy_id, ofnode_get_name(node));
 390                         return -ENOENT;
 391                 }
 392                 usbphyc_phy = usbphyc->phys + phy_id;
 393                 usbphyc_phy->init = false;
 394                 usbphyc_phy->powered = false;
 395                 ret = stm32_usbphyc_get_regulator(node, "phy-supply",
 396                                                   &usbphyc_phy->vdd);
 397                 if (ret) {
 398                         dev_err(dev, "Can't get phy-supply regulator\n");
 399                         return ret;
 400                 }
 401
 402                 usbphyc_phy->vbus = NULL;
 403                 connector = ofnode_find_subnode(node, "connector");
 404                 if (ofnode_valid(connector)) {
 405                         ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
 406                                                           &usbphyc_phy->vbus);
 407                 }
 408         }
 409
 410         /* Check if second port has to be used for host controller */
 411         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 412                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 413
 414         return 0;
 415 }
 416
 417 static const struct udevice_id stm32_usbphyc_of_match[] = {
 418         { .compatible = "st,stm32mp1-usbphyc", },
 419         { },
 420 };
 421
 422 U_BOOT_DRIVER(stm32_usb_phyc) = {
 423         .name = "stm32-usbphyc",
 424         .id = UCLASS_PHY,
 425         .of_match = stm32_usbphyc_of_match,
 426         .ops = &stm32_usbphyc_phy_ops,
 427         .probe = stm32_usbphyc_probe,
 428         .priv_auto      = sizeof(struct stm32_usbphyc),
 429 };