drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <generic-phy.h>
  12 #include <reset.h>
  13 #include <syscon.h>
  14 #include <usb.h>
  15 #include <asm/io.h>
  16 #include <linux/bitops.h>
  17 #include <power/regulator.h>
  18
  19 /* USBPHYC registers */
  20 #define STM32_USBPHYC_PLL       0x0
  21 #define STM32_USBPHYC_MISC      0x8
  22
  23 /* STM32_USBPHYC_PLL bit fields */
  24 #define PLLNDIV                 GENMASK(6, 0)
  25 #define PLLNDIV_SHIFT           0
  26 #define PLLFRACIN               GENMASK(25, 10)
  27 #define PLLFRACIN_SHIFT         10
  28 #define PLLEN                   BIT(26)
  29 #define PLLSTRB                 BIT(27)
  30 #define PLLSTRBYP               BIT(28)
  31 #define PLLFRACCTL              BIT(29)
  32 #define PLLDITHEN0              BIT(30)
  33 #define PLLDITHEN1              BIT(31)
  34
  35 /* STM32_USBPHYC_MISC bit fields */
  36 #define SWITHOST                BIT(0)
  37
  38 #define MAX_PHYS                2
  39
  40 #define PLL_LOCK_TIME_US        100
  41 #define PLL_PWR_DOWN_TIME_US    5
  42 #define PLL_FVCO                2880     /* in MHz */
  43 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  44 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  45
  46 struct pll_params {
  47         u8 ndiv;
  48         u16 frac;
  49 };
  50
  51 struct stm32_usbphyc {
  52         fdt_addr_t base;
  53         struct clk clk;
  54         struct stm32_usbphyc_phy {
  55                 struct udevice *vdd;
  56                 struct udevice *vdda1v1;
  57                 struct udevice *vdda1v8;
  58                 bool init;
  59                 bool powered;
  60         } phys[MAX_PHYS];
  61 };
  62
  63 void stm32_usbphyc_get_pll_params(u32 clk_rate, struct pll_params *pll_params)
  64 {
  65         unsigned long long fvco, ndiv, frac;
  66
  67         /*
  68          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  69          *    | FVCO = 2880MHz
  70          *    | NDIV = integer part of input bits to set the LDF
  71          *    | FRACT = fractional part of input bits to set the LDF
  72          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  73          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  74          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  75          */
  76         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  77
  78         ndiv = fvco;
  79         do_div(ndiv, (clk_rate * 2));
  80         pll_params->ndiv = (u8)ndiv;
  81
  82         frac = fvco * (1 << 16);
  83         do_div(frac, (clk_rate * 2));
  84         frac = frac - (ndiv * (1 << 16));
  85         pll_params->frac = (u16)frac;
  86 }
  87
  88 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  89 {
  90         struct pll_params pll_params;
  91         u32 clk_rate = clk_get_rate(&usbphyc->clk);
  92         u32 usbphyc_pll;
  93
  94         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  95                 pr_debug("%s: input clk freq (%dHz) out of range\n",
  96                          __func__, clk_rate);
  97                 return -EINVAL;
  98         }
  99
 100         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 101
 102         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 103         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 104
 105         if (pll_params.frac) {
 106                 usbphyc_pll |= PLLFRACCTL;
 107                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 108                                  & PLLFRACIN);
 109         }
 110
 111         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 112
 113         pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
 114                  clk_rate, pll_params.ndiv, pll_params.frac);
 115
 116         return 0;
 117 }
 118
 119 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
 120 {
 121         int i;
 122
 123         for (i = 0; i < MAX_PHYS; i++) {
 124                 if (usbphyc->phys[i].init)
 125                         return true;
 126         }
 127
 128         return false;
 129 }
 130
 131 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 132 {
 133         int i;
 134
 135         for (i = 0; i < MAX_PHYS; i++) {
 136                 if (usbphyc->phys[i].powered)
 137                         return true;
 138         }
 139
 140         return false;
 141 }
 142
 143 static int stm32_usbphyc_phy_init(struct phy *phy)
 144 {
 145         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 146         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 147         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 148                      true : false;
 149         int ret;
 150
 151         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 152         /* Check if one phy port has already configured the pll */
 153         if (pllen && stm32_usbphyc_is_init(usbphyc))
 154                 goto initialized;
 155
 156         if (pllen) {
 157                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 158                 udelay(PLL_PWR_DOWN_TIME_US);
 159         }
 160
 161         ret = stm32_usbphyc_pll_init(usbphyc);
 162         if (ret)
 163                 return ret;
 164
 165         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 166
 167         /*
 168          * We must wait PLL_LOCK_TIME_US before checking that PLLEN
 169          * bit is still set
 170          */
 171         udelay(PLL_LOCK_TIME_US);
 172
 173         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 174                 return -EIO;
 175
 176 initialized:
 177         usbphyc_phy->init = true;
 178
 179         return 0;
 180 }
 181
 182 static int stm32_usbphyc_phy_exit(struct phy *phy)
 183 {
 184         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 185         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 186
 187         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 188         usbphyc_phy->init = false;
 189
 190         /* Check if other phy port requires pllen */
 191         if (stm32_usbphyc_is_init(usbphyc))
 192                 return 0;
 193
 194         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 195
 196         /*
 197          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 198          * bit is still clear
 199          */
 200         udelay(PLL_PWR_DOWN_TIME_US);
 201
 202         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 203                 return -EIO;
 204
 205         return 0;
 206 }
 207
 208 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 209 {
 210         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 211         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 212         int ret;
 213
 214         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 215         if (usbphyc_phy->vdda1v1) {
 216                 ret = regulator_set_enable(usbphyc_phy->vdda1v1, true);
 217                 if (ret)
 218                         return ret;
 219         }
 220
 221         if (usbphyc_phy->vdda1v8) {
 222                 ret = regulator_set_enable(usbphyc_phy->vdda1v8, true);
 223                 if (ret)
 224                         return ret;
 225         }
 226         if (usbphyc_phy->vdd) {
 227                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 228                 if (ret)
 229                         return ret;
 230         }
 231
 232         usbphyc_phy->powered = true;
 233
 234         return 0;
 235 }
 236
 237 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 238 {
 239         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 240         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 241         int ret;
 242
 243         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 244         usbphyc_phy->powered = false;
 245
 246         if (stm32_usbphyc_is_powered(usbphyc))
 247                 return 0;
 248
 249         if (usbphyc_phy->vdda1v1) {
 250                 ret = regulator_set_enable(usbphyc_phy->vdda1v1, false);
 251                 if (ret)
 252                         return ret;
 253         }
 254
 255         if (usbphyc_phy->vdda1v8) {
 256                 ret = regulator_set_enable(usbphyc_phy->vdda1v8, false);
 257                 if (ret)
 258                         return ret;
 259         }
 260
 261         if (usbphyc_phy->vdd) {
 262                 ret = regulator_set_enable(usbphyc_phy->vdd, false);
 263                 if (ret)
 264                         return ret;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
 271                                        char *supply_name,
 272                                        struct udevice **regulator)
 273 {
 274         struct ofnode_phandle_args regulator_phandle;
 275         int ret;
 276
 277         ret = ofnode_parse_phandle_with_args(node, supply_name,
 278                                              NULL, 0, 0,
 279                                              &regulator_phandle);
 280         if (ret) {
 281                 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
 282                 return ret;
 283         }
 284
 285         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 286                                           regulator_phandle.node,
 287                                           regulator);
 288
 289         if (ret) {
 290                 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
 291                 return ret;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int stm32_usbphyc_of_xlate(struct phy *phy,
 298                                   struct ofnode_phandle_args *args)
 299 {
 300         if (args->args_count < 1)
 301                 return -ENODEV;
 302
 303         if (args->args[0] >= MAX_PHYS)
 304                 return -ENODEV;
 305
 306         phy->id = args->args[0];
 307
 308         if ((phy->id == 0 && args->args_count != 1) ||
 309             (phy->id == 1 && args->args_count != 2)) {
 310                 dev_err(dev, "invalid number of cells for phy port%ld\n",
 311                         phy->id);
 312                 return -EINVAL;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static const struct phy_ops stm32_usbphyc_phy_ops = {
 319         .init = stm32_usbphyc_phy_init,
 320         .exit = stm32_usbphyc_phy_exit,
 321         .power_on = stm32_usbphyc_phy_power_on,
 322         .power_off = stm32_usbphyc_phy_power_off,
 323         .of_xlate = stm32_usbphyc_of_xlate,
 324 };
 325
 326 static int stm32_usbphyc_probe(struct udevice *dev)
 327 {
 328         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 329         struct reset_ctl reset;
 330         ofnode node;
 331         int i, ret;
 332
 333         usbphyc->base = dev_read_addr(dev);
 334         if (usbphyc->base == FDT_ADDR_T_NONE)
 335                 return -EINVAL;
 336
 337         /* Enable clock */
 338         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 339         if (ret)
 340                 return ret;
 341
 342         ret = clk_enable(&usbphyc->clk);
 343         if (ret)
 344                 return ret;
 345
 346         /* Reset */
 347         ret = reset_get_by_index(dev, 0, &reset);
 348         if (!ret) {
 349                 reset_assert(&reset);
 350                 udelay(2);
 351                 reset_deassert(&reset);
 352         }
 353
 354         /*
 355          * parse all PHY subnodes in order to populate regulator associated
 356          * to each PHY port
 357          */
 358         node = dev_read_first_subnode(dev);
 359         for (i = 0; i < MAX_PHYS; i++) {
 360                 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
 361
 362                 usbphyc_phy->init = false;
 363                 usbphyc_phy->powered = false;
 364                 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
 365                                                   &usbphyc_phy->vdd);
 366                 if (ret)
 367                         return ret;
 368
 369                 ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v1-supply",
 370                                                   &usbphyc_phy->vdda1v1);
 371                 if (ret)
 372                         return ret;
 373
 374                 ret = stm32_usbphyc_get_regulator(dev, node, "vdda1v8-supply",
 375                                                   &usbphyc_phy->vdda1v8);
 376                 if (ret)
 377                         return ret;
 378
 379                 node = dev_read_next_subnode(node);
 380         }
 381
 382         /* Check if second port has to be used for host controller */
 383         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 384                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 385
 386         return 0;
 387 }
 388
 389 static const struct udevice_id stm32_usbphyc_of_match[] = {
 390         { .compatible = "st,stm32mp1-usbphyc", },
 391         { },
 392 };
 393
 394 U_BOOT_DRIVER(stm32_usb_phyc) = {
 395         .name = "stm32-usbphyc",
 396         .id = UCLASS_PHY,
 397         .of_match = stm32_usbphyc_of_match,
 398         .ops = &stm32_usbphyc_phy_ops,
 399         .probe = stm32_usbphyc_probe,
 400         .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
 401 };