drivers/phy/phy-stm32-usbphyc.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <div64.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <generic-phy.h>
  12 #include <reset.h>
  13 #include <syscon.h>
  14 #include <usb.h>
  15 #include <asm/io.h>
  16 #include <dm/device_compat.h>
  17 #include <linux/bitops.h>
  18 #include <power/regulator.h>
  19
  20 /* USBPHYC registers */
  21 #define STM32_USBPHYC_PLL       0x0
  22 #define STM32_USBPHYC_MISC      0x8
  23
  24 /* STM32_USBPHYC_PLL bit fields */
  25 #define PLLNDIV                 GENMASK(6, 0)
  26 #define PLLNDIV_SHIFT           0
  27 #define PLLFRACIN               GENMASK(25, 10)
  28 #define PLLFRACIN_SHIFT         10
  29 #define PLLEN                   BIT(26)
  30 #define PLLSTRB                 BIT(27)
  31 #define PLLSTRBYP               BIT(28)
  32 #define PLLFRACCTL              BIT(29)
  33 #define PLLDITHEN0              BIT(30)
  34 #define PLLDITHEN1              BIT(31)
  35
  36 /* STM32_USBPHYC_MISC bit fields */
  37 #define SWITHOST                BIT(0)
  38
  39 #define MAX_PHYS                2
  40
  41 /* max 100 us for PLL lock and 100 us for PHY init */
  42 #define PLL_INIT_TIME_US        200
  43 #define PLL_PWR_DOWN_TIME_US    5
  44 #define PLL_FVCO                2880     /* in MHz */
  45 #define PLL_INFF_MIN_RATE       19200000 /* in Hz */
  46 #define PLL_INFF_MAX_RATE       38400000 /* in Hz */
  47
  48 struct pll_params {
  49         u8 ndiv;
  50         u16 frac;
  51 };
  52
  53 struct stm32_usbphyc {
  54         fdt_addr_t base;
  55         struct clk clk;
  56         struct udevice *vdda1v1;
  57         struct udevice *vdda1v8;
  58         struct stm32_usbphyc_phy {
  59                 struct udevice *vdd;
  60                 bool init;
  61                 bool powered;
  62         } phys[MAX_PHYS];
  63 };
  64
  65 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  66                                          struct pll_params *pll_params)
  67 {
  68         unsigned long long fvco, ndiv, frac;
  69
  70         /*
  71          *    | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  72          *    | FVCO = 2880MHz
  73          *    | NDIV = integer part of input bits to set the LDF
  74          *    | FRACT = fractional part of input bits to set the LDF
  75          *  =>  PLLNDIV = integer part of (FVCO / (INFF*2))
  76          *  =>  PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  77          * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  78          */
  79         fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  80
  81         ndiv = fvco;
  82         do_div(ndiv, (clk_rate * 2));
  83         pll_params->ndiv = (u8)ndiv;
  84
  85         frac = fvco * (1 << 16);
  86         do_div(frac, (clk_rate * 2));
  87         frac = frac - (ndiv * (1 << 16));
  88         pll_params->frac = (u16)frac;
  89 }
  90
  91 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  92 {
  93         struct pll_params pll_params;
  94         u32 clk_rate = clk_get_rate(&usbphyc->clk);
  95         u32 usbphyc_pll;
  96
  97         if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  98                 pr_debug("%s: input clk freq (%dHz) out of range\n",
  99                          __func__, clk_rate);
 100                 return -EINVAL;
 101         }
 102
 103         stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
 104
 105         usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
 106         usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
 107
 108         if (pll_params.frac) {
 109                 usbphyc_pll |= PLLFRACCTL;
 110                 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
 111                                  & PLLFRACIN);
 112         }
 113
 114         writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
 115
 116         pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
 117                  clk_rate, pll_params.ndiv, pll_params.frac);
 118
 119         return 0;
 120 }
 121
 122 static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
 123 {
 124         int i;
 125
 126         for (i = 0; i < MAX_PHYS; i++) {
 127                 if (usbphyc->phys[i].init)
 128                         return true;
 129         }
 130
 131         return false;
 132 }
 133
 134 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
 135 {
 136         int i;
 137
 138         for (i = 0; i < MAX_PHYS; i++) {
 139                 if (usbphyc->phys[i].powered)
 140                         return true;
 141         }
 142
 143         return false;
 144 }
 145
 146 static int stm32_usbphyc_phy_init(struct phy *phy)
 147 {
 148         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 149         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 150         bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
 151                      true : false;
 152         int ret;
 153
 154         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 155         /* Check if one phy port has already configured the pll */
 156         if (pllen && stm32_usbphyc_is_init(usbphyc))
 157                 goto initialized;
 158
 159         if (usbphyc->vdda1v1) {
 160                 ret = regulator_set_enable(usbphyc->vdda1v1, true);
 161                 if (ret)
 162                         return ret;
 163         }
 164
 165         if (usbphyc->vdda1v8) {
 166                 ret = regulator_set_enable(usbphyc->vdda1v8, true);
 167                 if (ret)
 168                         return ret;
 169         }
 170
 171         if (pllen) {
 172                 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 173                 udelay(PLL_PWR_DOWN_TIME_US);
 174         }
 175
 176         ret = stm32_usbphyc_pll_init(usbphyc);
 177         if (ret)
 178                 return ret;
 179
 180         setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 181
 182         /* We must wait PLL_INIT_TIME_US before using PHY */
 183         udelay(PLL_INIT_TIME_US);
 184
 185         if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
 186                 return -EIO;
 187
 188 initialized:
 189         usbphyc_phy->init = true;
 190
 191         return 0;
 192 }
 193
 194 static int stm32_usbphyc_phy_exit(struct phy *phy)
 195 {
 196         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 197         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 198         int ret;
 199
 200         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 201         usbphyc_phy->init = false;
 202
 203         /* Check if other phy port requires pllen */
 204         if (stm32_usbphyc_is_init(usbphyc))
 205                 return 0;
 206
 207         clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
 208
 209         /*
 210          * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
 211          * bit is still clear
 212          */
 213         udelay(PLL_PWR_DOWN_TIME_US);
 214
 215         if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
 216                 return -EIO;
 217
 218         if (usbphyc->vdda1v1) {
 219                 ret = regulator_set_enable(usbphyc->vdda1v1, false);
 220                 if (ret)
 221                         return ret;
 222         }
 223
 224         if (usbphyc->vdda1v8) {
 225                 ret = regulator_set_enable(usbphyc->vdda1v8, false);
 226                 if (ret)
 227                         return ret;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int stm32_usbphyc_phy_power_on(struct phy *phy)
 234 {
 235         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 236         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 237         int ret;
 238
 239         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 240         if (usbphyc_phy->vdd) {
 241                 ret = regulator_set_enable(usbphyc_phy->vdd, true);
 242                 if (ret)
 243                         return ret;
 244         }
 245
 246         usbphyc_phy->powered = true;
 247
 248         return 0;
 249 }
 250
 251 static int stm32_usbphyc_phy_power_off(struct phy *phy)
 252 {
 253         struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
 254         struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
 255         int ret;
 256
 257         pr_debug("%s phy ID = %lu\n", __func__, phy->id);
 258         usbphyc_phy->powered = false;
 259
 260         if (stm32_usbphyc_is_powered(usbphyc))
 261                 return 0;
 262
 263         if (usbphyc_phy->vdd) {
 264                 ret = regulator_set_enable(usbphyc_phy->vdd, false);
 265                 if (ret)
 266                         return ret;
 267         }
 268
 269         return 0;
 270 }
 271
 272 static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
 273                                        char *supply_name,
 274                                        struct udevice **regulator)
 275 {
 276         struct ofnode_phandle_args regulator_phandle;
 277         int ret;
 278
 279         ret = ofnode_parse_phandle_with_args(node, supply_name,
 280                                              NULL, 0, 0,
 281                                              &regulator_phandle);
 282         if (ret) {
 283                 dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
 284                 return ret;
 285         }
 286
 287         ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
 288                                           regulator_phandle.node,
 289                                           regulator);
 290
 291         if (ret) {
 292                 dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
 293                 return ret;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static int stm32_usbphyc_of_xlate(struct phy *phy,
 300                                   struct ofnode_phandle_args *args)
 301 {
 302         if (args->args_count < 1)
 303                 return -ENODEV;
 304
 305         if (args->args[0] >= MAX_PHYS)
 306                 return -ENODEV;
 307
 308         phy->id = args->args[0];
 309
 310         if ((phy->id == 0 && args->args_count != 1) ||
 311             (phy->id == 1 && args->args_count != 2)) {
 312                 dev_err(dev, "invalid number of cells for phy port%ld\n",
 313                         phy->id);
 314                 return -EINVAL;
 315         }
 316
 317         return 0;
 318 }
 319
 320 static const struct phy_ops stm32_usbphyc_phy_ops = {
 321         .init = stm32_usbphyc_phy_init,
 322         .exit = stm32_usbphyc_phy_exit,
 323         .power_on = stm32_usbphyc_phy_power_on,
 324         .power_off = stm32_usbphyc_phy_power_off,
 325         .of_xlate = stm32_usbphyc_of_xlate,
 326 };
 327
 328 static int stm32_usbphyc_probe(struct udevice *dev)
 329 {
 330         struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
 331         struct reset_ctl reset;
 332         ofnode node;
 333         int i, ret;
 334
 335         usbphyc->base = dev_read_addr(dev);
 336         if (usbphyc->base == FDT_ADDR_T_NONE)
 337                 return -EINVAL;
 338
 339         /* Enable clock */
 340         ret = clk_get_by_index(dev, 0, &usbphyc->clk);
 341         if (ret)
 342                 return ret;
 343
 344         ret = clk_enable(&usbphyc->clk);
 345         if (ret)
 346                 return ret;
 347
 348         /* Reset */
 349         ret = reset_get_by_index(dev, 0, &reset);
 350         if (!ret) {
 351                 reset_assert(&reset);
 352                 udelay(2);
 353                 reset_deassert(&reset);
 354         }
 355
 356         /* get usbphyc regulator */
 357         ret = device_get_supply_regulator(dev, "vdda1v1-supply",
 358                                           &usbphyc->vdda1v1);
 359         if (ret) {
 360                 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
 361                 return ret;
 362         }
 363
 364         ret = device_get_supply_regulator(dev, "vdda1v8-supply",
 365                                           &usbphyc->vdda1v8);
 366         if (ret) {
 367                 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
 368                 return ret;
 369         }
 370
 371         /*
 372          * parse all PHY subnodes in order to populate regulator associated
 373          * to each PHY port
 374          */
 375         node = dev_read_first_subnode(dev);
 376         for (i = 0; i < MAX_PHYS; i++) {
 377                 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
 378
 379                 usbphyc_phy->init = false;
 380                 usbphyc_phy->powered = false;
 381                 ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
 382                                                   &usbphyc_phy->vdd);
 383                 if (ret)
 384                         return ret;
 385
 386                 node = dev_read_next_subnode(node);
 387         }
 388
 389         /* Check if second port has to be used for host controller */
 390         if (dev_read_bool(dev, "st,port2-switch-to-host"))
 391                 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
 392
 393         return 0;
 394 }
 395
 396 static const struct udevice_id stm32_usbphyc_of_match[] = {
 397         { .compatible = "st,stm32mp1-usbphyc", },
 398         { },
 399 };
 400
 401 U_BOOT_DRIVER(stm32_usb_phyc) = {
 402         .name = "stm32-usbphyc",
 403         .id = UCLASS_PHY,
 404         .of_match = stm32_usbphyc_of_match,
 405         .ops = &stm32_usbphyc_phy_ops,
 406         .probe = stm32_usbphyc_probe,
 407         .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
 408 };