1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RCar Gen2 USB PHY driver
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
13 #include <generic-phy.h>
19 #include <dm/device_compat.h>
20 #include <linux/bitops.h>
21 #include <power/regulator.h>
23 #define USBHS_LPSTS 0x02
24 #define USBHS_UGCTRL 0x80
25 #define USBHS_UGCTRL2 0x84
26 #define USBHS_UGSTS 0x88 /* From technical update */
28 /* Low Power Status register (LPSTS) */
29 #define USBHS_LPSTS_SUSPM 0x4000
31 /* USB General control register (UGCTRL) */
32 #define USBHS_UGCTRL_CONNECT BIT(2)
33 #define USBHS_UGCTRL_PLLRESET BIT(0)
35 /* USB General control register 2 (UGCTRL2) */
36 #define USBHS_UGCTRL2_USB2SEL 0x80000000
37 #define USBHS_UGCTRL2_USB2SEL_PCI 0x00000000
38 #define USBHS_UGCTRL2_USB2SEL_USB30 0x80000000
39 #define USBHS_UGCTRL2_USB0SEL 0x00000030
40 #define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010
41 #define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
43 /* USB General status register (UGSTS) */
44 #define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
46 #define PHYS_PER_CHANNEL 2
48 struct rcar_gen2_phy {
53 static int rcar_gen2_phy_phy_init(struct phy *phy)
55 struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
56 u16 chan = phy->id & 0xffff;
57 u16 mode = (phy->id >> 16) & 0xffff;
61 clrmask = USBHS_UGCTRL2_USB0SEL;
62 setmask = mode ? USBHS_UGCTRL2_USB0SEL_HS_USB :
63 USBHS_UGCTRL2_USB0SEL_PCI;
65 clrmask = USBHS_UGCTRL2_USB2SEL;
66 setmask = mode ? USBHS_UGCTRL2_USB2SEL_USB30 :
67 USBHS_UGCTRL2_USB2SEL_PCI;
69 clrsetbits_le32(priv->regs + USBHS_UGCTRL2, clrmask, setmask);
74 static int rcar_gen2_phy_phy_power_on(struct phy *phy)
76 struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
80 /* Power on USBHS PHY */
81 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET);
83 setbits_le16(priv->regs + USBHS_LPSTS, USBHS_LPSTS_SUSPM);
85 for (i = 0; i < 20; i++) {
86 value = readl(priv->regs + USBHS_UGSTS);
87 if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
88 setbits_le32(priv->regs + USBHS_UGCTRL,
89 USBHS_UGCTRL_CONNECT);
98 static int rcar_gen2_phy_phy_power_off(struct phy *phy)
100 struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
102 /* Power off USBHS PHY */
103 clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_CONNECT);
105 clrbits_le16(priv->regs + USBHS_LPSTS, USBHS_LPSTS_SUSPM);
107 setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET);
112 static int rcar_gen2_phy_of_xlate(struct phy *phy,
113 struct ofnode_phandle_args *args)
115 if (args->args_count != 2) {
116 dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
121 if (args->args[0] != 0 && args->args[0] != 2) {
122 dev_err(phy->dev, "Invalid DT PHY channel: %d\n",
127 if (args->args[1] != 0 && args->args[1] != 1) {
128 dev_err(phy->dev, "Invalid DT PHY mode: %d\n",
133 if (args->args_count)
134 phy->id = args->args[0] | (args->args[1] << 16);
141 static const struct phy_ops rcar_gen2_phy_phy_ops = {
142 .init = rcar_gen2_phy_phy_init,
143 .power_on = rcar_gen2_phy_phy_power_on,
144 .power_off = rcar_gen2_phy_phy_power_off,
145 .of_xlate = rcar_gen2_phy_of_xlate,
148 static int rcar_gen2_phy_probe(struct udevice *dev)
150 struct rcar_gen2_phy *priv = dev_get_priv(dev);
153 priv->regs = dev_read_addr(dev);
154 if (priv->regs == FDT_ADDR_T_NONE)
158 ret = clk_get_by_index(dev, 0, &priv->clk);
162 ret = clk_enable(&priv->clk);
169 static int rcar_gen2_phy_remove(struct udevice *dev)
171 struct rcar_gen2_phy *priv = dev_get_priv(dev);
173 clk_disable(&priv->clk);
174 clk_free(&priv->clk);
179 static const struct udevice_id rcar_gen2_phy_of_match[] = {
180 { .compatible = "renesas,rcar-gen2-usb-phy", },
184 U_BOOT_DRIVER(rcar_gen2_phy) = {
185 .name = "rcar-gen2-phy",
187 .of_match = rcar_gen2_phy_of_match,
188 .ops = &rcar_gen2_phy_phy_ops,
189 .probe = rcar_gen2_phy_probe,
190 .remove = rcar_gen2_phy_remove,
191 .priv_auto_alloc_size = sizeof(struct rcar_gen2_phy),