drivers/phy/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 - 2019 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <generic-phy.h>
  12 #include <mapmem.h>
  13 #include <asm/io.h>
  14 #include <dm/devres.h>
  15
  16 #include <dt-bindings/phy/phy.h>
  17
  18 /* version V1 sub-banks offset base address */
  19 /* banks shared by multiple phys */
  20 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  21 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  22 /* u3/pcie/sata phy banks */
  23 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  24 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  25
  26 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
  27 #define P3C_REG_IP_SW_RST               BIT(31)
  28 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
  29 #define P3C_FORCE_IP_SW_RST             BIT(29)
  30
  31 #define U3P_U3_CHIP_GPIO_CTLE           0x10
  32 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
  33 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
  34
  35 #define U3P_U3_PHYA_REG0                0x000
  36 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
  37 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
  38
  39 #define U3P_U3_PHYA_REG1                0x004
  40 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
  41 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
  42
  43 #define U3P_U3_PHYA_DA_REG0             0x100
  44 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
  45 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
  46 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
  47 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
  48 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
  49 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
  50
  51 #define U3P_U3_PHYA_DA_REG4             0x108
  52 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
  53 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
  54 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
  55
  56 #define U3P_U3_PHYA_DA_REG5             0x10c
  57 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
  58 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
  59 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
  60 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
  61
  62 #define U3P_U3_PHYA_DA_REG6             0x110
  63 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
  64 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
  65
  66 #define U3P_U3_PHYA_DA_REG7             0x114
  67 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
  68 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
  69
  70 #define U3P_U3_PHYA_DA_REG20            0x13c
  71 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
  72 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
  73
  74 #define U3P_U3_PHYA_DA_REG25            0x148
  75 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
  76 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
  77
  78 #define U3P_U3_PHYD_RXDET1              0x128
  79 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
  80 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
  81
  82 #define U3P_U3_PHYD_RXDET2              0x12c
  83 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
  84 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  85
  86 struct u3phy_banks {
  87         void __iomem *spllc;
  88         void __iomem *chip;
  89         void __iomem *phyd; /* include u3phyd_bank2 */
  90         void __iomem *phya; /* include u3phya_da */
  91 };
  92
  93 struct mtk_phy_instance {
  94         void __iomem *port_base;
  95         const struct device_node *np;
  96
  97         struct u3phy_banks u3_banks;
  98
  99         /* reference clock of anolog phy */
 100         struct clk ref_clk;
 101         u32 index;
 102         u8 type;
 103 };
 104
 105 struct mtk_tphy {
 106         void __iomem *sif_base;
 107         struct mtk_phy_instance **phys;
 108         int nphys;
 109 };
 110
 111 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 112                                    struct mtk_phy_instance *instance)
 113 {
 114         struct u3phy_banks *u3_banks = &instance->u3_banks;
 115
 116         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 117                         P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 118                         P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
 119                         P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
 120
 121         /* ref clk drive */
 122         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 123                         P3A_RG_CLKDRV_AMP_VAL(0x4));
 124         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 125                         P3A_RG_CLKDRV_OFF_VAL(0x1));
 126
 127         /* SSC delta -5000ppm */
 128         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
 129                         P3A_RG_PLL_DELTA1_PE2H,
 130                         P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
 131
 132         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
 133                         P3A_RG_PLL_DELTA_PE2H,
 134                         P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
 135
 136         /* change pll BW 0.6M */
 137         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
 138                         P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 139                         P3A_RG_PLL_BR_PE2H_VAL(0x1) |
 140                         P3A_RG_PLL_IC_PE2H_VAL(0x1));
 141         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
 142                         P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 143                         P3A_RG_PLL_BC_PE2H_VAL(0x3));
 144
 145         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
 146                         P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
 147         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
 148                         P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
 149
 150         /* Tx Detect Rx Timing: 10us -> 5us */
 151         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 152                         P3D_RG_RXDET_STB2_SET,
 153                         P3D_RG_RXDET_STB2_SET_VAL(0x10));
 154         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 155                         P3D_RG_RXDET_STB2_SET_P3,
 156                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 157
 158         /* wait for PCIe subsys register to active */
 159         udelay(3000);
 160 }
 161
 162 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 163                                        struct mtk_phy_instance *instance)
 164 {
 165         struct u3phy_banks *bank = &instance->u3_banks;
 166
 167         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 168                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 169         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 170                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 171 }
 172
 173 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 174                                         struct mtk_phy_instance *instance)
 175
 176 {
 177         struct u3phy_banks *bank = &instance->u3_banks;
 178
 179         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 180                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 181         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 182                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 183 }
 184
 185 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 186                               struct mtk_phy_instance *instance)
 187 {
 188         struct u3phy_banks *u3_banks = &instance->u3_banks;
 189
 190         switch (instance->type) {
 191         case PHY_TYPE_PCIE:
 192                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 193                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 194                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 195                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 196                 break;
 197         default:
 198                 return;
 199         }
 200 }
 201
 202 static int mtk_phy_init(struct phy *phy)
 203 {
 204         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 205         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 206         int ret;
 207
 208         ret = clk_enable(&instance->ref_clk);
 209         if (ret)
 210                 return ret;
 211
 212         switch (instance->type) {
 213         case PHY_TYPE_PCIE:
 214                 pcie_phy_instance_init(tphy, instance);
 215                 break;
 216         default:
 217                 return -EINVAL;
 218         }
 219
 220         return 0;
 221 }
 222
 223 static int mtk_phy_power_on(struct phy *phy)
 224 {
 225         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 226         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 227
 228         pcie_phy_instance_power_on(tphy, instance);
 229
 230         return 0;
 231 }
 232
 233 static int mtk_phy_power_off(struct phy *phy)
 234 {
 235         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 236         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 237
 238         pcie_phy_instance_power_off(tphy, instance);
 239
 240         return 0;
 241 }
 242
 243 static int mtk_phy_exit(struct phy *phy)
 244 {
 245         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 246         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 247
 248         clk_disable(&instance->ref_clk);
 249
 250         return 0;
 251 }
 252
 253 static int mtk_phy_xlate(struct phy *phy,
 254                          struct ofnode_phandle_args *args)
 255 {
 256         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 257         struct mtk_phy_instance *instance = NULL;
 258         const struct device_node *phy_np = ofnode_to_np(args->node);
 259         u32 index;
 260
 261         if (!phy_np) {
 262                 dev_err(phy->dev, "null pointer phy node\n");
 263                 return -EINVAL;
 264         }
 265
 266         if (args->args_count < 1) {
 267                 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
 268                 return -EINVAL;
 269         }
 270
 271         for (index = 0; index < tphy->nphys; index++)
 272                 if (phy_np == tphy->phys[index]->np) {
 273                         instance = tphy->phys[index];
 274                         break;
 275                 }
 276
 277         if (!instance) {
 278                 dev_err(phy->dev, "failed to find appropriate phy\n");
 279                 return -EINVAL;
 280         }
 281
 282         phy->id = index;
 283         instance->type = args->args[1];
 284         if (!(instance->type == PHY_TYPE_USB2 ||
 285               instance->type == PHY_TYPE_USB3 ||
 286               instance->type == PHY_TYPE_PCIE ||
 287               instance->type == PHY_TYPE_SATA)) {
 288                 dev_err(phy->dev, "unsupported device type\n");
 289                 return -EINVAL;
 290         }
 291
 292         phy_v1_banks_init(tphy, instance);
 293
 294         return 0;
 295 }
 296
 297 static const struct phy_ops mtk_tphy_ops = {
 298         .init           = mtk_phy_init,
 299         .exit           = mtk_phy_exit,
 300         .power_on       = mtk_phy_power_on,
 301         .power_off      = mtk_phy_power_off,
 302         .of_xlate       = mtk_phy_xlate,
 303 };
 304
 305 static int mtk_tphy_probe(struct udevice *dev)
 306 {
 307         struct mtk_tphy *tphy = dev_get_priv(dev);
 308         ofnode subnode;
 309         int index = 0;
 310
 311         dev_for_each_subnode(subnode, dev)
 312                 tphy->nphys++;
 313
 314         tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
 315                                   GFP_KERNEL);
 316         if (!tphy->phys)
 317                 return -ENOMEM;
 318
 319         tphy->sif_base = dev_read_addr_ptr(dev);
 320         if (!tphy->sif_base)
 321                 return -ENOENT;
 322
 323         dev_for_each_subnode(subnode, dev) {
 324                 struct mtk_phy_instance *instance;
 325                 fdt_addr_t addr;
 326                 int err;
 327
 328                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 329                 if (!instance)
 330                         return -ENOMEM;
 331
 332                 addr = ofnode_get_addr(subnode);
 333                 if (addr == FDT_ADDR_T_NONE)
 334                         return -ENOMEM;
 335
 336                 instance->port_base = map_sysmem(addr, 0);
 337                 instance->index = index;
 338                 instance->np = ofnode_to_np(subnode);
 339                 tphy->phys[index] = instance;
 340                 index++;
 341
 342                 err = clk_get_optional_nodev(subnode, "ref",
 343                                              &instance->ref_clk);
 344                 if (err)
 345                         return err;
 346         }
 347
 348         return 0;
 349 }
 350
 351 static const struct udevice_id mtk_tphy_id_table[] = {
 352         { .compatible = "mediatek,generic-tphy-v1", },
 353         { }
 354 };
 355
 356 U_BOOT_DRIVER(mtk_tphy) = {
 357         .name           = "mtk-tphy",
 358         .id             = UCLASS_PHY,
 359         .of_match       = mtk_tphy_id_table,
 360         .ops            = &mtk_tphy_ops,
 361         .probe          = mtk_tphy_probe,
 362         .priv_auto_alloc_size = sizeof(struct mtk_tphy),
 363 };