drivers/phy/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 - 2019 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <generic-phy.h>
  12 #include <malloc.h>
  13 #include <mapmem.h>
  14 #include <asm/io.h>
  15 #include <dm/device_compat.h>
  16 #include <dm/devres.h>
  17
  18 #include <dt-bindings/phy/phy.h>
  19
  20 /* version V1 sub-banks offset base address */
  21 /* banks shared by multiple phys */
  22 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  23 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  24 /* u3/pcie/sata phy banks */
  25 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  26 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  27
  28 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
  29 #define P3C_REG_IP_SW_RST               BIT(31)
  30 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
  31 #define P3C_FORCE_IP_SW_RST             BIT(29)
  32
  33 #define U3P_U3_CHIP_GPIO_CTLE           0x10
  34 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
  35 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
  36
  37 #define U3P_U3_PHYA_REG0                0x000
  38 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
  39 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
  40
  41 #define U3P_U3_PHYA_REG1                0x004
  42 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
  43 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
  44
  45 #define U3P_U3_PHYA_DA_REG0             0x100
  46 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
  47 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
  48 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
  49 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
  50 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
  51 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
  52
  53 #define U3P_U3_PHYA_DA_REG4             0x108
  54 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
  55 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
  56 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
  57
  58 #define U3P_U3_PHYA_DA_REG5             0x10c
  59 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
  60 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
  61 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
  62 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
  63
  64 #define U3P_U3_PHYA_DA_REG6             0x110
  65 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
  66 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
  67
  68 #define U3P_U3_PHYA_DA_REG7             0x114
  69 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
  70 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
  71
  72 #define U3P_U3_PHYA_DA_REG20            0x13c
  73 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
  74 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
  75
  76 #define U3P_U3_PHYA_DA_REG25            0x148
  77 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
  78 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
  79
  80 #define U3P_U3_PHYD_RXDET1              0x128
  81 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
  82 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
  83
  84 #define U3P_U3_PHYD_RXDET2              0x12c
  85 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
  86 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  87
  88 struct u3phy_banks {
  89         void __iomem *spllc;
  90         void __iomem *chip;
  91         void __iomem *phyd; /* include u3phyd_bank2 */
  92         void __iomem *phya; /* include u3phya_da */
  93 };
  94
  95 struct mtk_phy_instance {
  96         void __iomem *port_base;
  97         const struct device_node *np;
  98
  99         struct u3phy_banks u3_banks;
 100
 101         /* reference clock of anolog phy */
 102         struct clk ref_clk;
 103         u32 index;
 104         u8 type;
 105 };
 106
 107 struct mtk_tphy {
 108         void __iomem *sif_base;
 109         struct mtk_phy_instance **phys;
 110         int nphys;
 111 };
 112
 113 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 114                                    struct mtk_phy_instance *instance)
 115 {
 116         struct u3phy_banks *u3_banks = &instance->u3_banks;
 117
 118         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 119                         P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 120                         P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
 121                         P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
 122
 123         /* ref clk drive */
 124         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 125                         P3A_RG_CLKDRV_AMP_VAL(0x4));
 126         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 127                         P3A_RG_CLKDRV_OFF_VAL(0x1));
 128
 129         /* SSC delta -5000ppm */
 130         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
 131                         P3A_RG_PLL_DELTA1_PE2H,
 132                         P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
 133
 134         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
 135                         P3A_RG_PLL_DELTA_PE2H,
 136                         P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
 137
 138         /* change pll BW 0.6M */
 139         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
 140                         P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 141                         P3A_RG_PLL_BR_PE2H_VAL(0x1) |
 142                         P3A_RG_PLL_IC_PE2H_VAL(0x1));
 143         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
 144                         P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 145                         P3A_RG_PLL_BC_PE2H_VAL(0x3));
 146
 147         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
 148                         P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
 149         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
 150                         P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
 151
 152         /* Tx Detect Rx Timing: 10us -> 5us */
 153         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 154                         P3D_RG_RXDET_STB2_SET,
 155                         P3D_RG_RXDET_STB2_SET_VAL(0x10));
 156         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 157                         P3D_RG_RXDET_STB2_SET_P3,
 158                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 159
 160         /* wait for PCIe subsys register to active */
 161         udelay(3000);
 162 }
 163
 164 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 165                                        struct mtk_phy_instance *instance)
 166 {
 167         struct u3phy_banks *bank = &instance->u3_banks;
 168
 169         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 170                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 171         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 172                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 173 }
 174
 175 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 176                                         struct mtk_phy_instance *instance)
 177
 178 {
 179         struct u3phy_banks *bank = &instance->u3_banks;
 180
 181         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 182                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 183         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 184                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 185 }
 186
 187 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 188                               struct mtk_phy_instance *instance)
 189 {
 190         struct u3phy_banks *u3_banks = &instance->u3_banks;
 191
 192         switch (instance->type) {
 193         case PHY_TYPE_PCIE:
 194                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 195                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 196                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 197                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 198                 break;
 199         default:
 200                 return;
 201         }
 202 }
 203
 204 static int mtk_phy_init(struct phy *phy)
 205 {
 206         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 207         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 208         int ret;
 209
 210         ret = clk_enable(&instance->ref_clk);
 211         if (ret)
 212                 return ret;
 213
 214         switch (instance->type) {
 215         case PHY_TYPE_PCIE:
 216                 pcie_phy_instance_init(tphy, instance);
 217                 break;
 218         default:
 219                 return -EINVAL;
 220         }
 221
 222         return 0;
 223 }
 224
 225 static int mtk_phy_power_on(struct phy *phy)
 226 {
 227         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 228         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 229
 230         pcie_phy_instance_power_on(tphy, instance);
 231
 232         return 0;
 233 }
 234
 235 static int mtk_phy_power_off(struct phy *phy)
 236 {
 237         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 238         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 239
 240         pcie_phy_instance_power_off(tphy, instance);
 241
 242         return 0;
 243 }
 244
 245 static int mtk_phy_exit(struct phy *phy)
 246 {
 247         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 248         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 249
 250         clk_disable(&instance->ref_clk);
 251
 252         return 0;
 253 }
 254
 255 static int mtk_phy_xlate(struct phy *phy,
 256                          struct ofnode_phandle_args *args)
 257 {
 258         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 259         struct mtk_phy_instance *instance = NULL;
 260         const struct device_node *phy_np = ofnode_to_np(args->node);
 261         u32 index;
 262
 263         if (!phy_np) {
 264                 dev_err(phy->dev, "null pointer phy node\n");
 265                 return -EINVAL;
 266         }
 267
 268         if (args->args_count < 1) {
 269                 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
 270                 return -EINVAL;
 271         }
 272
 273         for (index = 0; index < tphy->nphys; index++)
 274                 if (phy_np == tphy->phys[index]->np) {
 275                         instance = tphy->phys[index];
 276                         break;
 277                 }
 278
 279         if (!instance) {
 280                 dev_err(phy->dev, "failed to find appropriate phy\n");
 281                 return -EINVAL;
 282         }
 283
 284         phy->id = index;
 285         instance->type = args->args[1];
 286         if (!(instance->type == PHY_TYPE_USB2 ||
 287               instance->type == PHY_TYPE_USB3 ||
 288               instance->type == PHY_TYPE_PCIE ||
 289               instance->type == PHY_TYPE_SATA)) {
 290                 dev_err(phy->dev, "unsupported device type\n");
 291                 return -EINVAL;
 292         }
 293
 294         phy_v1_banks_init(tphy, instance);
 295
 296         return 0;
 297 }
 298
 299 static const struct phy_ops mtk_tphy_ops = {
 300         .init           = mtk_phy_init,
 301         .exit           = mtk_phy_exit,
 302         .power_on       = mtk_phy_power_on,
 303         .power_off      = mtk_phy_power_off,
 304         .of_xlate       = mtk_phy_xlate,
 305 };
 306
 307 static int mtk_tphy_probe(struct udevice *dev)
 308 {
 309         struct mtk_tphy *tphy = dev_get_priv(dev);
 310         ofnode subnode;
 311         int index = 0;
 312
 313         dev_for_each_subnode(subnode, dev)
 314                 tphy->nphys++;
 315
 316         tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
 317                                   GFP_KERNEL);
 318         if (!tphy->phys)
 319                 return -ENOMEM;
 320
 321         tphy->sif_base = dev_read_addr_ptr(dev);
 322         if (!tphy->sif_base)
 323                 return -ENOENT;
 324
 325         dev_for_each_subnode(subnode, dev) {
 326                 struct mtk_phy_instance *instance;
 327                 fdt_addr_t addr;
 328                 int err;
 329
 330                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 331                 if (!instance)
 332                         return -ENOMEM;
 333
 334                 addr = ofnode_get_addr(subnode);
 335                 if (addr == FDT_ADDR_T_NONE)
 336                         return -ENOMEM;
 337
 338                 instance->port_base = map_sysmem(addr, 0);
 339                 instance->index = index;
 340                 instance->np = ofnode_to_np(subnode);
 341                 tphy->phys[index] = instance;
 342                 index++;
 343
 344                 err = clk_get_optional_nodev(subnode, "ref",
 345                                              &instance->ref_clk);
 346                 if (err)
 347                         return err;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static const struct udevice_id mtk_tphy_id_table[] = {
 354         { .compatible = "mediatek,generic-tphy-v1", },
 355         { }
 356 };
 357
 358 U_BOOT_DRIVER(mtk_tphy) = {
 359         .name           = "mtk-tphy",
 360         .id             = UCLASS_PHY,
 361         .of_match       = mtk_tphy_id_table,
 362         .ops            = &mtk_tphy_ops,
 363         .probe          = mtk_tphy_probe,
 364         .priv_auto_alloc_size = sizeof(struct mtk_tphy),
 365 };