drivers/phy/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 - 2019 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <generic-phy.h>
  12 #include <malloc.h>
  13 #include <mapmem.h>
  14 #include <asm/io.h>
  15 #include <dm/device_compat.h>
  16 #include <dm/devres.h>
  17 #include <linux/bitops.h>
  18 #include <linux/delay.h>
  19
  20 #include <dt-bindings/phy/phy.h>
  21
  22 /* version V1 sub-banks offset base address */
  23 /* banks shared by multiple phys */
  24 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  25 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  26 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  27 /* u2 phy bank */
  28 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  29 /* u3/pcie/sata phy banks */
  30 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  31 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  32
  33 /* version V2 sub-banks offset base address */
  34 /* u2 phy banks */
  35 #define SSUSB_SIFSLV_V2_MISC            0x000
  36 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  37 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  38 /* u3/pcie/sata phy banks */
  39 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  40 #define SSUSB_SIFSLV_V2_CHIP            0x100
  41 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  42 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  43
  44 #define U3P_USBPHYACR0                  0x000
  45 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  46 #define PA0_RG_USB20_INTR_EN            BIT(5)
  47
  48 #define U3P_USBPHYACR5                  0x014
  49 #define PA5_RG_U2_HSTX_SRCAL_EN         BIT(15)
  50 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  51 #define PA5_RG_U2_HSTX_SRCTRL_VAL(x)    ((0x7 & (x)) << 12)
  52 #define PA5_RG_U2_HS_100U_U3_EN         BIT(11)
  53
  54 #define U3P_USBPHYACR6                  0x018
  55 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  56 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  57 #define PA6_RG_U2_SQTH                  GENMASK(3, 0)
  58 #define PA6_RG_U2_SQTH_VAL(x)           (0xf & (x))
  59
  60 #define U3P_U2PHYACR4                   0x020
  61 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  62 #define P2C_USB20_GPIO_MODE             BIT(8)
  63 #define P2C_U2_GPIO_CTR_MSK     \
  64                 (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  65
  66 #define U3P_U2PHYDTM0                   0x068
  67 #define P2C_FORCE_UART_EN               BIT(26)
  68 #define P2C_FORCE_DATAIN                BIT(23)
  69 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
  70 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
  71 #define P2C_FORCE_XCVRSEL               BIT(19)
  72 #define P2C_FORCE_SUSPENDM              BIT(18)
  73 #define P2C_FORCE_TERMSEL               BIT(17)
  74 #define P2C_RG_DATAIN                   GENMASK(13, 10)
  75 #define P2C_RG_DATAIN_VAL(x)            ((0xf & (x)) << 10)
  76 #define P2C_RG_DMPULLDOWN               BIT(7)
  77 #define P2C_RG_DPPULLDOWN               BIT(6)
  78 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
  79 #define P2C_RG_XCVRSEL_VAL(x)           ((0x3 & (x)) << 4)
  80 #define P2C_RG_SUSPENDM                 BIT(3)
  81 #define P2C_RG_TERMSEL                  BIT(2)
  82 #define P2C_DTM0_PART_MASK      \
  83                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  84                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  85                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  86                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  87
  88 #define U3P_U2PHYDTM1                   0x06C
  89 #define P2C_RG_UART_EN                  BIT(16)
  90 #define P2C_FORCE_IDDIG                 BIT(9)
  91 #define P2C_RG_VBUSVALID                BIT(5)
  92 #define P2C_RG_SESSEND                  BIT(4)
  93 #define P2C_RG_AVALID                   BIT(2)
  94 #define P2C_RG_IDDIG                    BIT(1)
  95
  96 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
  97 #define P3C_REG_IP_SW_RST               BIT(31)
  98 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
  99 #define P3C_FORCE_IP_SW_RST             BIT(29)
 100
 101 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 102 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 103 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 104
 105 #define U3P_U3_PHYA_REG0                0x000
 106 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 107 #define P3A_RG_CLKDRV_OFF_VAL(x)        ((0x3 & (x)) << 2)
 108
 109 #define U3P_U3_PHYA_REG1                0x004
 110 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 111 #define P3A_RG_CLKDRV_AMP_VAL(x)        ((0x7 & (x)) << 29)
 112
 113 #define U3P_U3_PHYA_REG6                0x018
 114 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 115 #define P3A_RG_TX_EIDLE_CM_VAL(x)       ((0xf & (x)) << 28)
 116
 117 #define U3P_U3_PHYA_REG9                0x024
 118 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 119 #define P3A_RG_RX_DAC_MUX_VAL(x)        ((0x1f & (x)) << 1)
 120
 121 #define U3P_U3_PHYA_DA_REG0             0x100
 122 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 123 #define P3A_RG_XTAL_EXT_PE2H_VAL(x)     ((0x3 & (x)) << 16)
 124 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 125 #define P3A_RG_XTAL_EXT_PE1H_VAL(x)     ((0x3 & (x)) << 12)
 126 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 127 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)    ((0x3 & (x)) << 10)
 128
 129 #define U3P_U3_PHYA_DA_REG4             0x108
 130 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 131 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 132 #define P3A_RG_PLL_BC_PE2H_VAL(x)       ((0x3 & (x)) << 6)
 133
 134 #define U3P_U3_PHYA_DA_REG5             0x10c
 135 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 136 #define P3A_RG_PLL_BR_PE2H_VAL(x)       ((0x3 & (x)) << 28)
 137 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 138 #define P3A_RG_PLL_IC_PE2H_VAL(x)       ((0xf & (x)) << 12)
 139
 140 #define U3P_U3_PHYA_DA_REG6             0x110
 141 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 142 #define P3A_RG_PLL_IR_PE2H_VAL(x)       ((0xf & (x)) << 16)
 143
 144 #define U3P_U3_PHYA_DA_REG7             0x114
 145 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 146 #define P3A_RG_PLL_BP_PE2H_VAL(x)       ((0xf & (x)) << 16)
 147
 148 #define U3P_U3_PHYA_DA_REG20            0x13c
 149 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 150 #define P3A_RG_PLL_DELTA1_PE2H_VAL(x)   ((0xffff & (x)) << 16)
 151
 152 #define U3P_U3_PHYA_DA_REG25            0x148
 153 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 154 #define P3A_RG_PLL_DELTA_PE2H_VAL(x)    (0xffff & (x))
 155
 156 #define U3P_U3_PHYD_LFPS1               0x00c
 157 #define P3D_RG_FWAKE_TH                 GENMASK(21, 16)
 158 #define P3D_RG_FWAKE_TH_VAL(x)          ((0x3f & (x)) << 16)
 159
 160 #define U3P_U3_PHYD_CDR1                0x05c
 161 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 162 #define P3D_RG_CDR_BIR_LTD1_VAL(x)      ((0x1f & (x)) << 24)
 163 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 164 #define P3D_RG_CDR_BIR_LTD0_VAL(x)      ((0x1f & (x)) << 8)
 165
 166 #define U3P_U3_PHYD_RXDET1              0x128
 167 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 168 #define P3D_RG_RXDET_STB2_SET_VAL(x)    ((0x1ff & (x)) << 9)
 169
 170 #define U3P_U3_PHYD_RXDET2              0x12c
 171 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 172 #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
 173
 174 #define U3P_SPLLC_XTALCTL3              0x018
 175 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 176 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 177
 178 /* SATA register setting */
 179 #define PHYD_CTRL_SIGNAL_MODE4          0x1c
 180 /* CDR Charge Pump P-path current adjustment */
 181 #define RG_CDR_BICLTD1_GEN1_MSK         GENMASK(23, 20)
 182 #define RG_CDR_BICLTD1_GEN1_VAL(x)      ((0xf & (x)) << 20)
 183 #define RG_CDR_BICLTD0_GEN1_MSK         GENMASK(11, 8)
 184 #define RG_CDR_BICLTD0_GEN1_VAL(x)      ((0xf & (x)) << 8)
 185
 186 #define PHYD_DESIGN_OPTION2             0x24
 187 /* Symbol lock count selection */
 188 #define RG_LOCK_CNT_SEL_MSK             GENMASK(5, 4)
 189 #define RG_LOCK_CNT_SEL_VAL(x)          ((0x3 & (x)) << 4)
 190
 191 #define PHYD_DESIGN_OPTION9             0x40
 192 /* COMWAK GAP width window */
 193 #define RG_TG_MAX_MSK                   GENMASK(20, 16)
 194 #define RG_TG_MAX_VAL(x)                ((0x1f & (x)) << 16)
 195 /* COMINIT GAP width window */
 196 #define RG_T2_MAX_MSK                   GENMASK(13, 8)
 197 #define RG_T2_MAX_VAL(x)                ((0x3f & (x)) << 8)
 198 /* COMWAK GAP width window */
 199 #define RG_TG_MIN_MSK                   GENMASK(7, 5)
 200 #define RG_TG_MIN_VAL(x)                ((0x7 & (x)) << 5)
 201 /* COMINIT GAP width window */
 202 #define RG_T2_MIN_MSK                   GENMASK(4, 0)
 203 #define RG_T2_MIN_VAL(x)                (0x1f & (x))
 204
 205 #define ANA_RG_CTRL_SIGNAL1             0x4c
 206 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 207 #define RG_IDRV_0DB_GEN1_MSK            GENMASK(13, 8)
 208 #define RG_IDRV_0DB_GEN1_VAL(x)         ((0x3f & (x)) << 8)
 209
 210 #define ANA_RG_CTRL_SIGNAL4             0x58
 211 #define RG_CDR_BICLTR_GEN1_MSK          GENMASK(23, 20)
 212 #define RG_CDR_BICLTR_GEN1_VAL(x)       ((0xf & (x)) << 20)
 213 /* Loop filter R1 resistance adjustment for Gen1 speed */
 214 #define RG_CDR_BR_GEN2_MSK              GENMASK(10, 8)
 215 #define RG_CDR_BR_GEN2_VAL(x)           ((0x7 & (x)) << 8)
 216
 217 #define ANA_RG_CTRL_SIGNAL6             0x60
 218 /* I-path capacitance adjustment for Gen1 */
 219 #define RG_CDR_BC_GEN1_MSK              GENMASK(28, 24)
 220 #define RG_CDR_BC_GEN1_VAL(x)           ((0x1f & (x)) << 24)
 221 #define RG_CDR_BIRLTR_GEN1_MSK          GENMASK(4, 0)
 222 #define RG_CDR_BIRLTR_GEN1_VAL(x)       (0x1f & (x))
 223
 224 #define ANA_EQ_EYE_CTRL_SIGNAL1         0x6c
 225 /* RX Gen1 LEQ tuning step */
 226 #define RG_EQ_DLEQ_LFI_GEN1_MSK         GENMASK(11, 8)
 227 #define RG_EQ_DLEQ_LFI_GEN1_VAL(x)      ((0xf & (x)) << 8)
 228
 229 #define ANA_EQ_EYE_CTRL_SIGNAL4         0xd8
 230 #define RG_CDR_BIRLTD0_GEN1_MSK         GENMASK(20, 16)
 231 #define RG_CDR_BIRLTD0_GEN1_VAL(x)      ((0x1f & (x)) << 16)
 232
 233 #define ANA_EQ_EYE_CTRL_SIGNAL5         0xdc
 234 #define RG_CDR_BIRLTD0_GEN3_MSK         GENMASK(4, 0)
 235 #define RG_CDR_BIRLTD0_GEN3_VAL(x)      (0x1f & (x))
 236
 237 enum mtk_phy_version {
 238         MTK_TPHY_V1 = 1,
 239         MTK_TPHY_V2,
 240 };
 241
 242 struct u2phy_banks {
 243         void __iomem *misc;
 244         void __iomem *fmreg;
 245         void __iomem *com;
 246 };
 247
 248 struct u3phy_banks {
 249         void __iomem *spllc;
 250         void __iomem *chip;
 251         void __iomem *phyd; /* include u3phyd_bank2 */
 252         void __iomem *phya; /* include u3phya_da */
 253 };
 254
 255 struct mtk_phy_instance {
 256         void __iomem *port_base;
 257         const struct device_node *np;
 258         union {
 259                 struct u2phy_banks u2_banks;
 260                 struct u3phy_banks u3_banks;
 261         };
 262
 263         struct clk ref_clk;     /* reference clock of (digital) phy */
 264         struct clk da_ref_clk;  /* reference clock of analog phy */
 265         u32 index;
 266         u32 type;
 267 };
 268
 269 struct mtk_tphy {
 270         struct udevice *dev;
 271         void __iomem *sif_base;
 272         enum mtk_phy_version version;
 273         struct mtk_phy_instance **phys;
 274         int nphys;
 275 };
 276
 277 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 278                                  struct mtk_phy_instance *instance)
 279 {
 280         struct u2phy_banks *u2_banks = &instance->u2_banks;
 281
 282         /* switch to USB function, and enable usb pll */
 283         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 284                         P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
 285                         P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
 286
 287         clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 288         setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
 289
 290         /* disable switch 100uA current to SSUSB */
 291         clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 292
 293         clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 294
 295         /* DP/DM BC1.1 path Disable */
 296         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
 297                         PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
 298                         PA6_RG_U2_SQTH_VAL(2));
 299
 300         /* set HS slew rate */
 301         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
 302                         PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
 303
 304         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 305 }
 306
 307 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 308                                      struct mtk_phy_instance *instance)
 309 {
 310         struct u2phy_banks *u2_banks = &instance->u2_banks;
 311
 312         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 313                      P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 314
 315         /* OTG Enable */
 316         setbits_le32(u2_banks->com + U3P_USBPHYACR6,
 317                      PA6_RG_U2_OTG_VBUSCMP_EN);
 318
 319         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 320                         P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 321
 322         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 323 }
 324
 325 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 326                                       struct mtk_phy_instance *instance)
 327 {
 328         struct u2phy_banks *u2_banks = &instance->u2_banks;
 329
 330         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 331                      P2C_RG_XCVRSEL | P2C_RG_DATAIN);
 332
 333         /* OTG Disable */
 334         clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
 335                      PA6_RG_U2_OTG_VBUSCMP_EN);
 336
 337         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 338                         P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
 339
 340         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 341 }
 342
 343 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 344                                  struct mtk_phy_instance *instance)
 345 {
 346         struct u3phy_banks *u3_banks = &instance->u3_banks;
 347
 348         /* gating PCIe Analog XTAL clock */
 349         setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
 350                      XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
 351
 352         /* gating XSQ */
 353         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 354                         P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
 355
 356         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
 357                         P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
 358
 359         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
 360                         P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
 361
 362         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
 363                         P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
 364                         P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
 365                         P3D_RG_CDR_BIR_LTD1_VAL(0x3));
 366
 367         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
 368                         P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
 369
 370         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 371                         P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
 372
 373         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 374                         P3D_RG_RXDET_STB2_SET_P3,
 375                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 376
 377         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 378 }
 379
 380 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 381                                    struct mtk_phy_instance *instance)
 382 {
 383         struct u3phy_banks *u3_banks = &instance->u3_banks;
 384
 385         if (tphy->version != MTK_TPHY_V1)
 386                 return;
 387
 388         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 389                         P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 390                         P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
 391                         P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
 392
 393         /* ref clk drive */
 394         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 395                         P3A_RG_CLKDRV_AMP_VAL(0x4));
 396         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 397                         P3A_RG_CLKDRV_OFF_VAL(0x1));
 398
 399         /* SSC delta -5000ppm */
 400         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
 401                         P3A_RG_PLL_DELTA1_PE2H,
 402                         P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
 403
 404         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
 405                         P3A_RG_PLL_DELTA_PE2H,
 406                         P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
 407
 408         /* change pll BW 0.6M */
 409         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
 410                         P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 411                         P3A_RG_PLL_BR_PE2H_VAL(0x1) |
 412                         P3A_RG_PLL_IC_PE2H_VAL(0x1));
 413         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
 414                         P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 415                         P3A_RG_PLL_BC_PE2H_VAL(0x3));
 416
 417         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
 418                         P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
 419         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
 420                         P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
 421
 422         /* Tx Detect Rx Timing: 10us -> 5us */
 423         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 424                         P3D_RG_RXDET_STB2_SET,
 425                         P3D_RG_RXDET_STB2_SET_VAL(0x10));
 426         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 427                         P3D_RG_RXDET_STB2_SET_P3,
 428                         P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
 429
 430         /* wait for PCIe subsys register to active */
 431         udelay(3000);
 432 }
 433
 434 static void sata_phy_instance_init(struct mtk_tphy *tphy,
 435                                    struct mtk_phy_instance *instance)
 436 {
 437         struct u3phy_banks *u3_banks = &instance->u3_banks;
 438
 439         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
 440                         RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
 441                         RG_CDR_BIRLTR_GEN1_VAL(0x6) |
 442                         RG_CDR_BC_GEN1_VAL(0x1a));
 443         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
 444                         RG_CDR_BIRLTD0_GEN1_MSK,
 445                         RG_CDR_BIRLTD0_GEN1_VAL(0x18));
 446         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
 447                         RG_CDR_BIRLTD0_GEN3_MSK,
 448                         RG_CDR_BIRLTD0_GEN3_VAL(0x06));
 449         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
 450                         RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
 451                         RG_CDR_BICLTR_GEN1_VAL(0x0c) |
 452                         RG_CDR_BR_GEN2_VAL(0x07));
 453         clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
 454                         RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
 455                         RG_CDR_BICLTD0_GEN1_VAL(0x08) |
 456                         RG_CDR_BICLTD1_GEN1_VAL(0x02));
 457         clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
 458                         RG_LOCK_CNT_SEL_MSK,
 459                         RG_LOCK_CNT_SEL_VAL(0x02));
 460         clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
 461                         RG_T2_MIN_MSK | RG_TG_MIN_MSK |
 462                         RG_T2_MAX_MSK | RG_TG_MAX_MSK,
 463                         RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
 464                         RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
 465         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1,
 466                         RG_IDRV_0DB_GEN1_MSK,
 467                         RG_IDRV_0DB_GEN1_VAL(0x20));
 468         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1,
 469                         RG_EQ_DLEQ_LFI_GEN1_MSK,
 470                         RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
 471 }
 472
 473 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 474                                        struct mtk_phy_instance *instance)
 475 {
 476         struct u3phy_banks *bank = &instance->u3_banks;
 477
 478         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 479                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 480         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 481                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 482 }
 483
 484 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 485                                         struct mtk_phy_instance *instance)
 486
 487 {
 488         struct u3phy_banks *bank = &instance->u3_banks;
 489
 490         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 491                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 492         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 493                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 494 }
 495
 496 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 497                               struct mtk_phy_instance *instance)
 498 {
 499         struct u2phy_banks *u2_banks = &instance->u2_banks;
 500         struct u3phy_banks *u3_banks = &instance->u3_banks;
 501
 502         switch (instance->type) {
 503         case PHY_TYPE_USB2:
 504                 u2_banks->misc = NULL;
 505                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
 506                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
 507                 break;
 508         case PHY_TYPE_USB3:
 509         case PHY_TYPE_PCIE:
 510                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 511                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 512                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 513                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 514                 break;
 515         case PHY_TYPE_SATA:
 516                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 517                 break;
 518         default:
 519                 dev_err(tphy->dev, "incompatible PHY type\n");
 520                 return;
 521         }
 522 }
 523
 524 static void phy_v2_banks_init(struct mtk_tphy *tphy,
 525                               struct mtk_phy_instance *instance)
 526 {
 527         struct u2phy_banks *u2_banks = &instance->u2_banks;
 528         struct u3phy_banks *u3_banks = &instance->u3_banks;
 529
 530         switch (instance->type) {
 531         case PHY_TYPE_USB2:
 532                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
 533                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
 534                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
 535                 break;
 536         case PHY_TYPE_USB3:
 537         case PHY_TYPE_PCIE:
 538                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
 539                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
 540                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
 541                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
 542                 break;
 543         default:
 544                 dev_err(tphy->dev, "incompatible PHY type\n");
 545                 return;
 546         }
 547 }
 548
 549 static int mtk_phy_init(struct phy *phy)
 550 {
 551         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 552         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 553         int ret;
 554
 555         ret = clk_enable(&instance->ref_clk);
 556         if (ret < 0) {
 557                 dev_err(tphy->dev, "failed to enable ref_clk\n");
 558                 return ret;
 559         }
 560
 561         ret = clk_enable(&instance->da_ref_clk);
 562         if (ret < 0) {
 563                 dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
 564                 clk_disable(&instance->ref_clk);
 565                 return ret;
 566         }
 567
 568         switch (instance->type) {
 569         case PHY_TYPE_USB2:
 570                 u2_phy_instance_init(tphy, instance);
 571                 break;
 572         case PHY_TYPE_USB3:
 573                 u3_phy_instance_init(tphy, instance);
 574                 break;
 575         case PHY_TYPE_PCIE:
 576                 pcie_phy_instance_init(tphy, instance);
 577                 break;
 578         case PHY_TYPE_SATA:
 579                 sata_phy_instance_init(tphy, instance);
 580                 break;
 581         default:
 582                 dev_err(tphy->dev, "incompatible PHY type\n");
 583                 return -EINVAL;
 584         }
 585
 586         return 0;
 587 }
 588
 589 static int mtk_phy_power_on(struct phy *phy)
 590 {
 591         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 592         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 593
 594         if (instance->type == PHY_TYPE_USB2)
 595                 u2_phy_instance_power_on(tphy, instance);
 596         else if (instance->type == PHY_TYPE_PCIE)
 597                 pcie_phy_instance_power_on(tphy, instance);
 598
 599         return 0;
 600 }
 601
 602 static int mtk_phy_power_off(struct phy *phy)
 603 {
 604         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 605         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 606
 607         if (instance->type == PHY_TYPE_USB2)
 608                 u2_phy_instance_power_off(tphy, instance);
 609         else if (instance->type == PHY_TYPE_PCIE)
 610                 pcie_phy_instance_power_off(tphy, instance);
 611
 612         return 0;
 613 }
 614
 615 static int mtk_phy_exit(struct phy *phy)
 616 {
 617         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 618         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 619
 620         clk_disable(&instance->da_ref_clk);
 621         clk_disable(&instance->ref_clk);
 622
 623         return 0;
 624 }
 625
 626 static int mtk_phy_xlate(struct phy *phy,
 627                          struct ofnode_phandle_args *args)
 628 {
 629         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 630         struct mtk_phy_instance *instance = NULL;
 631         const struct device_node *phy_np = ofnode_to_np(args->node);
 632         u32 index;
 633
 634         if (!phy_np) {
 635                 dev_err(phy->dev, "null pointer phy node\n");
 636                 return -EINVAL;
 637         }
 638
 639         if (args->args_count < 1) {
 640                 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
 641                 return -EINVAL;
 642         }
 643
 644         for (index = 0; index < tphy->nphys; index++)
 645                 if (phy_np == tphy->phys[index]->np) {
 646                         instance = tphy->phys[index];
 647                         break;
 648                 }
 649
 650         if (!instance) {
 651                 dev_err(phy->dev, "failed to find appropriate phy\n");
 652                 return -EINVAL;
 653         }
 654
 655         phy->id = index;
 656         instance->type = args->args[1];
 657         if (!(instance->type == PHY_TYPE_USB2 ||
 658               instance->type == PHY_TYPE_USB3 ||
 659               instance->type == PHY_TYPE_SATA ||
 660               instance->type == PHY_TYPE_PCIE)) {
 661                 dev_err(phy->dev, "unsupported device type\n");
 662                 return -EINVAL;
 663         }
 664
 665         if (tphy->version == MTK_TPHY_V1) {
 666                 phy_v1_banks_init(tphy, instance);
 667         } else if (tphy->version == MTK_TPHY_V2) {
 668                 phy_v2_banks_init(tphy, instance);
 669         } else {
 670                 dev_err(phy->dev, "phy version is not supported\n");
 671                 return -EINVAL;
 672         }
 673
 674         return 0;
 675 }
 676
 677 static const struct phy_ops mtk_tphy_ops = {
 678         .init           = mtk_phy_init,
 679         .exit           = mtk_phy_exit,
 680         .power_on       = mtk_phy_power_on,
 681         .power_off      = mtk_phy_power_off,
 682         .of_xlate       = mtk_phy_xlate,
 683 };
 684
 685 static int mtk_tphy_probe(struct udevice *dev)
 686 {
 687         struct mtk_tphy *tphy = dev_get_priv(dev);
 688         ofnode subnode;
 689         int index = 0;
 690
 691         tphy->nphys = dev_get_child_count(dev);
 692
 693         tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
 694                                   GFP_KERNEL);
 695         if (!tphy->phys)
 696                 return -ENOMEM;
 697
 698         tphy->dev = dev;
 699         tphy->version = dev_get_driver_data(dev);
 700
 701         /* v1 has shared banks for usb/pcie mode, */
 702         /* but not for sata mode */
 703         if (tphy->version == MTK_TPHY_V1) {
 704                 tphy->sif_base = dev_read_addr_ptr(dev);
 705         }
 706
 707         dev_for_each_subnode(subnode, dev) {
 708                 struct mtk_phy_instance *instance;
 709                 fdt_addr_t addr;
 710                 int err;
 711
 712                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 713                 if (!instance)
 714                         return -ENOMEM;
 715
 716                 addr = ofnode_get_addr(subnode);
 717                 if (addr == FDT_ADDR_T_NONE)
 718                         return -ENOMEM;
 719
 720                 instance->port_base = map_sysmem(addr, 0);
 721                 instance->index = index;
 722                 instance->np = ofnode_to_np(subnode);
 723                 tphy->phys[index] = instance;
 724                 index++;
 725
 726                 err = clk_get_optional_nodev(subnode, "ref",
 727                                              &instance->ref_clk);
 728                 if (err)
 729                         return err;
 730
 731                 err = clk_get_optional_nodev(subnode, "da_ref",
 732                                              &instance->da_ref_clk);
 733                 if (err)
 734                         return err;
 735         }
 736
 737         return 0;
 738 }
 739
 740 static const struct udevice_id mtk_tphy_id_table[] = {
 741         { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
 742         { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
 743         { }
 744 };
 745
 746 U_BOOT_DRIVER(mtk_tphy) = {
 747         .name           = "mtk-tphy",
 748         .id             = UCLASS_PHY,
 749         .of_match       = mtk_tphy_id_table,
 750         .ops            = &mtk_tphy_ops,
 751         .probe          = mtk_tphy_probe,
 752         .priv_auto      = sizeof(struct mtk_tphy),
 753 };