drivers/phy/phy-mtk-tphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 - 2019 MediaTek Inc.
   4  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   5  *         Ryder Lee <ryder.lee@mediatek.com>
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <generic-phy.h>
  12 #include <malloc.h>
  13 #include <mapmem.h>
  14 #include <asm/io.h>
  15 #include <dm/device_compat.h>
  16 #include <dm/devres.h>
  17 #include <linux/bitfield.h>
  18 #include <linux/bitops.h>
  19 #include <linux/delay.h>
  20
  21 #include <dt-bindings/phy/phy.h>
  22
  23 /* version V1 sub-banks offset base address */
  24 /* banks shared by multiple phys */
  25 #define SSUSB_SIFSLV_V1_SPLLC           0x000   /* shared by u3 phys */
  26 #define SSUSB_SIFSLV_V1_U2FREQ          0x100   /* shared by u2 phys */
  27 #define SSUSB_SIFSLV_V1_CHIP            0x300   /* shared by u3 phys */
  28 /* u2 phy bank */
  29 #define SSUSB_SIFSLV_V1_U2PHY_COM       0x000
  30 /* u3/pcie/sata phy banks */
  31 #define SSUSB_SIFSLV_V1_U3PHYD          0x000
  32 #define SSUSB_SIFSLV_V1_U3PHYA          0x200
  33
  34 /* version V2 sub-banks offset base address */
  35 /* u2 phy banks */
  36 #define SSUSB_SIFSLV_V2_MISC            0x000
  37 #define SSUSB_SIFSLV_V2_U2FREQ          0x100
  38 #define SSUSB_SIFSLV_V2_U2PHY_COM       0x300
  39 /* u3/pcie/sata phy banks */
  40 #define SSUSB_SIFSLV_V2_SPLLC           0x000
  41 #define SSUSB_SIFSLV_V2_CHIP            0x100
  42 #define SSUSB_SIFSLV_V2_U3PHYD          0x200
  43 #define SSUSB_SIFSLV_V2_U3PHYA          0x400
  44
  45 #define U3P_USBPHYACR0                  0x000
  46 #define PA0_RG_U2PLL_FORCE_ON           BIT(15)
  47 #define PA0_USB20_PLL_PREDIV            GENMASK(7, 6)
  48 #define PA0_RG_USB20_INTR_EN            BIT(5)
  49
  50 #define U3P_USBPHYACR2                  0x008
  51 #define PA2_RG_U2PLL_BW                 GENMASK(21, 19)
  52
  53 #define U3P_USBPHYACR5                  0x014
  54 #define PA5_RG_U2_HSTX_SRCAL_EN         BIT(15)
  55 #define PA5_RG_U2_HSTX_SRCTRL           GENMASK(14, 12)
  56 #define PA5_RG_U2_HS_100U_U3_EN         BIT(11)
  57
  58 #define U3P_USBPHYACR6                  0x018
  59 #define PA6_RG_U2_BC11_SW_EN            BIT(23)
  60 #define PA6_RG_U2_OTG_VBUSCMP_EN        BIT(20)
  61 #define PA6_RG_U2_SQTH                  GENMASK(3, 0)
  62
  63 #define U3P_U2PHYACR4                   0x020
  64 #define P2C_RG_USB20_GPIO_CTL           BIT(9)
  65 #define P2C_USB20_GPIO_MODE             BIT(8)
  66 #define P2C_U2_GPIO_CTR_MSK     \
  67                 (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  68
  69 #define U3P_U2PHYA_RESV                 0x030
  70 #define P2R_RG_U2PLL_FBDIV_26M          0x1bb13b
  71 #define P2R_RG_U2PLL_FBDIV_48M          0x3c0000
  72
  73 #define U3P_U2PHYA_RESV1                0x044
  74 #define P2R_RG_U2PLL_REFCLK_SEL         BIT(5)
  75 #define P2R_RG_U2PLL_FRA_EN             BIT(3)
  76
  77 #define U3P_U2PHYDTM0                   0x068
  78 #define P2C_FORCE_UART_EN               BIT(26)
  79 #define P2C_FORCE_DATAIN                BIT(23)
  80 #define P2C_FORCE_DM_PULLDOWN           BIT(21)
  81 #define P2C_FORCE_DP_PULLDOWN           BIT(20)
  82 #define P2C_FORCE_XCVRSEL               BIT(19)
  83 #define P2C_FORCE_SUSPENDM              BIT(18)
  84 #define P2C_FORCE_TERMSEL               BIT(17)
  85 #define P2C_RG_DATAIN                   GENMASK(13, 10)
  86 #define P2C_RG_DMPULLDOWN               BIT(7)
  87 #define P2C_RG_DPPULLDOWN               BIT(6)
  88 #define P2C_RG_XCVRSEL                  GENMASK(5, 4)
  89 #define P2C_RG_SUSPENDM                 BIT(3)
  90 #define P2C_RG_TERMSEL                  BIT(2)
  91 #define P2C_DTM0_PART_MASK      \
  92                 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  93                 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  94                 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  95                 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  96
  97 #define U3P_U2PHYDTM1                   0x06C
  98 #define P2C_RG_UART_EN                  BIT(16)
  99 #define P2C_FORCE_IDDIG                 BIT(9)
 100 #define P2C_RG_VBUSVALID                BIT(5)
 101 #define P2C_RG_SESSEND                  BIT(4)
 102 #define P2C_RG_AVALID                   BIT(2)
 103 #define P2C_RG_IDDIG                    BIT(1)
 104
 105 #define U3P_U3_CHIP_GPIO_CTLD           0x0c
 106 #define P3C_REG_IP_SW_RST               BIT(31)
 107 #define P3C_MCU_BUS_CK_GATE_EN          BIT(30)
 108 #define P3C_FORCE_IP_SW_RST             BIT(29)
 109
 110 #define U3P_U3_CHIP_GPIO_CTLE           0x10
 111 #define P3C_RG_SWRST_U3_PHYD            BIT(25)
 112 #define P3C_RG_SWRST_U3_PHYD_FORCE_EN   BIT(24)
 113
 114 #define U3P_U3_PHYA_REG0                0x000
 115 #define P3A_RG_CLKDRV_OFF               GENMASK(3, 2)
 116
 117 #define U3P_U3_PHYA_REG1                0x004
 118 #define P3A_RG_CLKDRV_AMP               GENMASK(31, 29)
 119
 120 #define U3P_U3_PHYA_REG6                0x018
 121 #define P3A_RG_TX_EIDLE_CM              GENMASK(31, 28)
 122
 123 #define U3P_U3_PHYA_REG9                0x024
 124 #define P3A_RG_RX_DAC_MUX               GENMASK(5, 1)
 125
 126 #define U3P_U3_PHYA_DA_REG0             0x100
 127 #define P3A_RG_XTAL_EXT_PE2H            GENMASK(17, 16)
 128 #define P3A_RG_XTAL_EXT_PE1H            GENMASK(13, 12)
 129 #define P3A_RG_XTAL_EXT_EN_U3           GENMASK(11, 10)
 130
 131 #define U3P_U3_PHYA_DA_REG4             0x108
 132 #define P3A_RG_PLL_DIVEN_PE2H           GENMASK(21, 19)
 133 #define P3A_RG_PLL_BC_PE2H              GENMASK(7, 6)
 134
 135 #define U3P_U3_PHYA_DA_REG5             0x10c
 136 #define P3A_RG_PLL_BR_PE2H              GENMASK(29, 28)
 137 #define P3A_RG_PLL_IC_PE2H              GENMASK(15, 12)
 138
 139 #define U3P_U3_PHYA_DA_REG6             0x110
 140 #define P3A_RG_PLL_IR_PE2H              GENMASK(19, 16)
 141
 142 #define U3P_U3_PHYA_DA_REG7             0x114
 143 #define P3A_RG_PLL_BP_PE2H              GENMASK(19, 16)
 144
 145 #define U3P_U3_PHYA_DA_REG20            0x13c
 146 #define P3A_RG_PLL_DELTA1_PE2H          GENMASK(31, 16)
 147
 148 #define U3P_U3_PHYA_DA_REG25            0x148
 149 #define P3A_RG_PLL_DELTA_PE2H           GENMASK(15, 0)
 150
 151 #define U3P_U3_PHYD_LFPS1               0x00c
 152 #define P3D_RG_FWAKE_TH                 GENMASK(21, 16)
 153
 154 #define U3P_U3_PHYD_CDR1                0x05c
 155 #define P3D_RG_CDR_BIR_LTD1             GENMASK(28, 24)
 156 #define P3D_RG_CDR_BIR_LTD0             GENMASK(12, 8)
 157
 158 #define U3P_U3_PHYD_RXDET1              0x128
 159 #define P3D_RG_RXDET_STB2_SET           GENMASK(17, 9)
 160
 161 #define U3P_U3_PHYD_RXDET2              0x12c
 162 #define P3D_RG_RXDET_STB2_SET_P3        GENMASK(8, 0)
 163
 164 #define U3P_SPLLC_XTALCTL3              0x018
 165 #define XC3_RG_U3_XTAL_RX_PWD           BIT(9)
 166 #define XC3_RG_U3_FRC_XTAL_RX_PWD       BIT(8)
 167
 168 /* SATA register setting */
 169 #define PHYD_CTRL_SIGNAL_MODE4          0x1c
 170 /* CDR Charge Pump P-path current adjustment */
 171 #define RG_CDR_BICLTD1_GEN1_MSK         GENMASK(23, 20)
 172 #define RG_CDR_BICLTD0_GEN1_MSK         GENMASK(11, 8)
 173
 174 #define PHYD_DESIGN_OPTION2             0x24
 175 /* Symbol lock count selection */
 176 #define RG_LOCK_CNT_SEL_MSK             GENMASK(5, 4)
 177
 178 #define PHYD_DESIGN_OPTION9             0x40
 179 /* COMWAK GAP width window */
 180 #define RG_TG_MAX_MSK                   GENMASK(20, 16)
 181 /* COMINIT GAP width window */
 182 #define RG_T2_MAX_MSK                   GENMASK(13, 8)
 183 /* COMWAK GAP width window */
 184 #define RG_TG_MIN_MSK                   GENMASK(7, 5)
 185 /* COMINIT GAP width window */
 186 #define RG_T2_MIN_MSK                   GENMASK(4, 0)
 187
 188 #define ANA_RG_CTRL_SIGNAL1             0x4c
 189 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
 190 #define RG_IDRV_0DB_GEN1_MSK            GENMASK(13, 8)
 191
 192 #define ANA_RG_CTRL_SIGNAL4             0x58
 193 #define RG_CDR_BICLTR_GEN1_MSK          GENMASK(23, 20)
 194 /* Loop filter R1 resistance adjustment for Gen1 speed */
 195 #define RG_CDR_BR_GEN2_MSK              GENMASK(10, 8)
 196
 197 #define ANA_RG_CTRL_SIGNAL6             0x60
 198 /* I-path capacitance adjustment for Gen1 */
 199 #define RG_CDR_BC_GEN1_MSK              GENMASK(28, 24)
 200 #define RG_CDR_BIRLTR_GEN1_MSK          GENMASK(4, 0)
 201
 202 #define ANA_EQ_EYE_CTRL_SIGNAL1         0x6c
 203 /* RX Gen1 LEQ tuning step */
 204 #define RG_EQ_DLEQ_LFI_GEN1_MSK         GENMASK(11, 8)
 205
 206 #define ANA_EQ_EYE_CTRL_SIGNAL4         0xd8
 207 #define RG_CDR_BIRLTD0_GEN1_MSK         GENMASK(20, 16)
 208
 209 #define ANA_EQ_EYE_CTRL_SIGNAL5         0xdc
 210 #define RG_CDR_BIRLTD0_GEN3_MSK         GENMASK(4, 0)
 211
 212 enum mtk_phy_version {
 213         MTK_TPHY_V1 = 1,
 214         MTK_TPHY_V2,
 215 };
 216
 217 struct tphy_pdata {
 218         enum mtk_phy_version version;
 219
 220         /*
 221          * workaround only for mt8195:
 222          * u2phy should use integer mode instead of fractional mode of
 223          * 48M PLL, fix it by switching PLL to 26M from default 48M
 224          */
 225         bool sw_pll_48m_to_26m;
 226 };
 227
 228 struct u2phy_banks {
 229         void __iomem *misc;
 230         void __iomem *fmreg;
 231         void __iomem *com;
 232 };
 233
 234 struct u3phy_banks {
 235         void __iomem *spllc;
 236         void __iomem *chip;
 237         void __iomem *phyd; /* include u3phyd_bank2 */
 238         void __iomem *phya; /* include u3phya_da */
 239 };
 240
 241 struct mtk_phy_instance {
 242         void __iomem *port_base;
 243         const struct device_node *np;
 244         union {
 245                 struct u2phy_banks u2_banks;
 246                 struct u3phy_banks u3_banks;
 247         };
 248
 249         struct clk ref_clk;     /* reference clock of (digital) phy */
 250         struct clk da_ref_clk;  /* reference clock of analog phy */
 251         u32 index;
 252         u32 type;
 253 };
 254
 255 struct mtk_tphy {
 256         struct udevice *dev;
 257         void __iomem *sif_base;
 258         const struct tphy_pdata *pdata;
 259         struct mtk_phy_instance **phys;
 260         int nphys;
 261 };
 262
 263 /* workaround only for mt8195 */
 264 static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
 265                                struct mtk_phy_instance *instance)
 266 {
 267         struct u2phy_banks *u2_banks = &instance->u2_banks;
 268
 269         if (!tphy->pdata->sw_pll_48m_to_26m)
 270                 return;
 271
 272         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV,
 273                         FIELD_PREP(PA0_USB20_PLL_PREDIV, 0));
 274
 275         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW,
 276                         FIELD_PREP(PA2_RG_U2PLL_BW, 3));
 277
 278         writel(P2R_RG_U2PLL_FBDIV_26M, u2_banks->com + U3P_U2PHYA_RESV);
 279
 280         setbits_le32(u2_banks->com + U3P_U2PHYA_RESV1,
 281                      P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL);
 282 }
 283
 284 static void u2_phy_instance_init(struct mtk_tphy *tphy,
 285                                  struct mtk_phy_instance *instance)
 286 {
 287         struct u2phy_banks *u2_banks = &instance->u2_banks;
 288
 289         /* switch to USB function, and enable usb pll */
 290         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 291                         P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
 292                         FIELD_PREP(P2C_RG_XCVRSEL, 1) |
 293                         FIELD_PREP(P2C_RG_DATAIN, 0));
 294
 295         clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
 296         setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
 297
 298         /* disable switch 100uA current to SSUSB */
 299         clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
 300
 301         clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
 302
 303         /* DP/DM BC1.1 path Disable */
 304         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
 305                         PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
 306                         FIELD_PREP(PA6_RG_U2_SQTH, 2));
 307
 308         /* set HS slew rate */
 309         clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
 310                         PA5_RG_U2_HSTX_SRCTRL,
 311                         FIELD_PREP(PA5_RG_U2_HSTX_SRCTRL, 4));
 312
 313         u2_phy_pll_26m_set(tphy, instance);
 314
 315         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 316 }
 317
 318 static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
 319                                      struct mtk_phy_instance *instance)
 320 {
 321         struct u2phy_banks *u2_banks = &instance->u2_banks;
 322
 323         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 324                      P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
 325
 326         /* OTG Enable */
 327         setbits_le32(u2_banks->com + U3P_USBPHYACR6,
 328                      PA6_RG_U2_OTG_VBUSCMP_EN);
 329
 330         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 331                         P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
 332
 333         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 334 }
 335
 336 static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
 337                                       struct mtk_phy_instance *instance)
 338 {
 339         struct u2phy_banks *u2_banks = &instance->u2_banks;
 340
 341         clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
 342                      P2C_RG_XCVRSEL | P2C_RG_DATAIN);
 343
 344         /* OTG Disable */
 345         clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
 346                      PA6_RG_U2_OTG_VBUSCMP_EN);
 347
 348         clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
 349                         P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
 350
 351         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 352 }
 353
 354 static void u3_phy_instance_init(struct mtk_tphy *tphy,
 355                                  struct mtk_phy_instance *instance)
 356 {
 357         struct u3phy_banks *u3_banks = &instance->u3_banks;
 358
 359         /* gating PCIe Analog XTAL clock */
 360         setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
 361                      XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
 362
 363         /* gating XSQ */
 364         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 365                         P3A_RG_XTAL_EXT_EN_U3,
 366                         FIELD_PREP(P3A_RG_XTAL_EXT_EN_U3, 2));
 367
 368         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
 369                         P3A_RG_RX_DAC_MUX, FIELD_PREP(P3A_RG_RX_DAC_MUX, 4));
 370
 371         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
 372                         P3A_RG_TX_EIDLE_CM,
 373                         FIELD_PREP(P3A_RG_TX_EIDLE_CM, 0xe));
 374
 375         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
 376                         P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
 377                         FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) |
 378                         FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3));
 379
 380         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
 381                         P3D_RG_FWAKE_TH, FIELD_PREP(P3D_RG_FWAKE_TH, 0x34));
 382
 383         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 384                         P3D_RG_RXDET_STB2_SET,
 385                         FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10));
 386
 387         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 388                         P3D_RG_RXDET_STB2_SET_P3,
 389                         FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10));
 390
 391         dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
 392 }
 393
 394 static void pcie_phy_instance_init(struct mtk_tphy *tphy,
 395                                    struct mtk_phy_instance *instance)
 396 {
 397         struct u3phy_banks *u3_banks = &instance->u3_banks;
 398
 399         if (tphy->pdata->version != MTK_TPHY_V1)
 400                 return;
 401
 402         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
 403                         P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
 404                         FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
 405                         FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2));
 406
 407         /* ref clk drive */
 408         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
 409                         FIELD_PREP(P3A_RG_CLKDRV_AMP, 0x4));
 410         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
 411                         FIELD_PREP(P3A_RG_CLKDRV_OFF, 0x1));
 412
 413         /* SSC delta -5000ppm */
 414         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
 415                         P3A_RG_PLL_DELTA1_PE2H,
 416                         FIELD_PREP(P3A_RG_PLL_DELTA1_PE2H, 0x3c));
 417
 418         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
 419                         P3A_RG_PLL_DELTA_PE2H,
 420                         FIELD_PREP(P3A_RG_PLL_DELTA_PE2H, 0x36));
 421
 422         /* change pll BW 0.6M */
 423         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
 424                         P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
 425                         FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) |
 426                         FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1));
 427         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
 428                         P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
 429                         FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3));
 430
 431         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
 432                         P3A_RG_PLL_IR_PE2H,
 433                         FIELD_PREP(P3A_RG_PLL_IR_PE2H, 0x2));
 434         clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
 435                         P3A_RG_PLL_BP_PE2H,
 436                         FIELD_PREP(P3A_RG_PLL_BP_PE2H, 0xa));
 437
 438         /* Tx Detect Rx Timing: 10us -> 5us */
 439         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
 440                         P3D_RG_RXDET_STB2_SET,
 441                         FIELD_PREP(P3D_RG_RXDET_STB2_SET, 0x10));
 442         clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
 443                         P3D_RG_RXDET_STB2_SET_P3,
 444                         FIELD_PREP(P3D_RG_RXDET_STB2_SET_P3, 0x10));
 445
 446         /* wait for PCIe subsys register to active */
 447         udelay(3000);
 448 }
 449
 450 static void sata_phy_instance_init(struct mtk_tphy *tphy,
 451                                    struct mtk_phy_instance *instance)
 452 {
 453         struct u3phy_banks *u3_banks = &instance->u3_banks;
 454
 455         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
 456                         RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
 457                         FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) |
 458                         FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a));
 459         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
 460                         RG_CDR_BIRLTD0_GEN1_MSK,
 461                         FIELD_PREP(RG_CDR_BIRLTD0_GEN1_MSK, 0x18));
 462         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
 463                         RG_CDR_BIRLTD0_GEN3_MSK,
 464                         FIELD_PREP(RG_CDR_BIRLTD0_GEN3_MSK, 0x06));
 465         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
 466                         RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
 467                         FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) |
 468                         FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07));
 469         clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
 470                         RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
 471                         FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) |
 472                         FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02));
 473         clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
 474                         RG_LOCK_CNT_SEL_MSK,
 475                         FIELD_PREP(RG_LOCK_CNT_SEL_MSK, 0x02));
 476         clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
 477                         RG_T2_MIN_MSK | RG_TG_MIN_MSK |
 478                         RG_T2_MAX_MSK | RG_TG_MAX_MSK,
 479                         FIELD_PREP(RG_T2_MIN_MSK, 0x12) |
 480                         FIELD_PREP(RG_TG_MIN_MSK, 0x04) |
 481                         FIELD_PREP(RG_T2_MAX_MSK, 0x31) |
 482                         FIELD_PREP(RG_TG_MAX_MSK, 0x0e));
 483         clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1,
 484                         RG_IDRV_0DB_GEN1_MSK,
 485                         FIELD_PREP(RG_IDRV_0DB_GEN1_MSK, 0x20));
 486         clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1,
 487                         RG_EQ_DLEQ_LFI_GEN1_MSK,
 488                         FIELD_PREP(RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03));
 489 }
 490
 491 static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 492                                        struct mtk_phy_instance *instance)
 493 {
 494         struct u3phy_banks *bank = &instance->u3_banks;
 495
 496         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 497                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 498         clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 499                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 500 }
 501
 502 static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
 503                                         struct mtk_phy_instance *instance)
 504
 505 {
 506         struct u3phy_banks *bank = &instance->u3_banks;
 507
 508         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
 509                      P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 510         setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
 511                      P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
 512 }
 513
 514 static void phy_v1_banks_init(struct mtk_tphy *tphy,
 515                               struct mtk_phy_instance *instance)
 516 {
 517         struct u2phy_banks *u2_banks = &instance->u2_banks;
 518         struct u3phy_banks *u3_banks = &instance->u3_banks;
 519
 520         switch (instance->type) {
 521         case PHY_TYPE_USB2:
 522                 u2_banks->misc = NULL;
 523                 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
 524                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
 525                 break;
 526         case PHY_TYPE_USB3:
 527         case PHY_TYPE_PCIE:
 528                 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
 529                 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
 530                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 531                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
 532                 break;
 533         case PHY_TYPE_SATA:
 534                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
 535                 break;
 536         default:
 537                 dev_err(tphy->dev, "incompatible PHY type\n");
 538                 return;
 539         }
 540 }
 541
 542 static void phy_v2_banks_init(struct mtk_tphy *tphy,
 543                               struct mtk_phy_instance *instance)
 544 {
 545         struct u2phy_banks *u2_banks = &instance->u2_banks;
 546         struct u3phy_banks *u3_banks = &instance->u3_banks;
 547
 548         switch (instance->type) {
 549         case PHY_TYPE_USB2:
 550                 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
 551                 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
 552                 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
 553                 break;
 554         case PHY_TYPE_USB3:
 555         case PHY_TYPE_PCIE:
 556                 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
 557                 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
 558                 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
 559                 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
 560                 break;
 561         default:
 562                 dev_err(tphy->dev, "incompatible PHY type\n");
 563                 return;
 564         }
 565 }
 566
 567 static int mtk_phy_init(struct phy *phy)
 568 {
 569         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 570         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 571         int ret;
 572
 573         ret = clk_enable(&instance->ref_clk);
 574         if (ret < 0) {
 575                 dev_err(tphy->dev, "failed to enable ref_clk\n");
 576                 return ret;
 577         }
 578
 579         ret = clk_enable(&instance->da_ref_clk);
 580         if (ret < 0) {
 581                 dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
 582                 clk_disable(&instance->ref_clk);
 583                 return ret;
 584         }
 585
 586         switch (instance->type) {
 587         case PHY_TYPE_USB2:
 588                 u2_phy_instance_init(tphy, instance);
 589                 break;
 590         case PHY_TYPE_USB3:
 591                 u3_phy_instance_init(tphy, instance);
 592                 break;
 593         case PHY_TYPE_PCIE:
 594                 pcie_phy_instance_init(tphy, instance);
 595                 break;
 596         case PHY_TYPE_SATA:
 597                 sata_phy_instance_init(tphy, instance);
 598                 break;
 599         default:
 600                 dev_err(tphy->dev, "incompatible PHY type\n");
 601                 return -EINVAL;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int mtk_phy_power_on(struct phy *phy)
 608 {
 609         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 610         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 611
 612         if (instance->type == PHY_TYPE_USB2)
 613                 u2_phy_instance_power_on(tphy, instance);
 614         else if (instance->type == PHY_TYPE_PCIE)
 615                 pcie_phy_instance_power_on(tphy, instance);
 616
 617         return 0;
 618 }
 619
 620 static int mtk_phy_power_off(struct phy *phy)
 621 {
 622         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 623         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 624
 625         if (instance->type == PHY_TYPE_USB2)
 626                 u2_phy_instance_power_off(tphy, instance);
 627         else if (instance->type == PHY_TYPE_PCIE)
 628                 pcie_phy_instance_power_off(tphy, instance);
 629
 630         return 0;
 631 }
 632
 633 static int mtk_phy_exit(struct phy *phy)
 634 {
 635         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 636         struct mtk_phy_instance *instance = tphy->phys[phy->id];
 637
 638         clk_disable(&instance->da_ref_clk);
 639         clk_disable(&instance->ref_clk);
 640
 641         return 0;
 642 }
 643
 644 static int mtk_phy_xlate(struct phy *phy,
 645                          struct ofnode_phandle_args *args)
 646 {
 647         struct mtk_tphy *tphy = dev_get_priv(phy->dev);
 648         struct mtk_phy_instance *instance = NULL;
 649         const struct device_node *phy_np = ofnode_to_np(args->node);
 650         u32 index;
 651
 652         if (!phy_np) {
 653                 dev_err(phy->dev, "null pointer phy node\n");
 654                 return -EINVAL;
 655         }
 656
 657         if (args->args_count < 1) {
 658                 dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
 659                 return -EINVAL;
 660         }
 661
 662         for (index = 0; index < tphy->nphys; index++)
 663                 if (phy_np == tphy->phys[index]->np) {
 664                         instance = tphy->phys[index];
 665                         break;
 666                 }
 667
 668         if (!instance) {
 669                 dev_err(phy->dev, "failed to find appropriate phy\n");
 670                 return -EINVAL;
 671         }
 672
 673         phy->id = index;
 674         instance->type = args->args[1];
 675         if (!(instance->type == PHY_TYPE_USB2 ||
 676               instance->type == PHY_TYPE_USB3 ||
 677               instance->type == PHY_TYPE_SATA ||
 678               instance->type == PHY_TYPE_PCIE)) {
 679                 dev_err(phy->dev, "unsupported device type\n");
 680                 return -EINVAL;
 681         }
 682
 683         switch (tphy->pdata->version) {
 684         case MTK_TPHY_V1:
 685                 phy_v1_banks_init(tphy, instance);
 686                 break;
 687         case MTK_TPHY_V2:
 688                 phy_v2_banks_init(tphy, instance);
 689                 break;
 690         default:
 691                 dev_err(phy->dev, "phy version is not supported\n");
 692                 return -EINVAL;
 693         }
 694
 695         return 0;
 696 }
 697
 698 static const struct phy_ops mtk_tphy_ops = {
 699         .init           = mtk_phy_init,
 700         .exit           = mtk_phy_exit,
 701         .power_on       = mtk_phy_power_on,
 702         .power_off      = mtk_phy_power_off,
 703         .of_xlate       = mtk_phy_xlate,
 704 };
 705
 706 static int mtk_tphy_probe(struct udevice *dev)
 707 {
 708         struct mtk_tphy *tphy = dev_get_priv(dev);
 709         ofnode subnode;
 710         int index = 0;
 711
 712         tphy->nphys = dev_get_child_count(dev);
 713
 714         tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
 715                                   GFP_KERNEL);
 716         if (!tphy->phys)
 717                 return -ENOMEM;
 718
 719         tphy->dev = dev;
 720         tphy->pdata = (void *)dev_get_driver_data(dev);
 721
 722         /* v1 has shared banks for usb/pcie mode, */
 723         /* but not for sata mode */
 724         if (tphy->pdata->version == MTK_TPHY_V1)
 725                 tphy->sif_base = dev_read_addr_ptr(dev);
 726
 727         dev_for_each_subnode(subnode, dev) {
 728                 struct mtk_phy_instance *instance;
 729                 fdt_addr_t addr;
 730                 int err;
 731
 732                 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
 733                 if (!instance)
 734                         return -ENOMEM;
 735
 736                 addr = ofnode_get_addr(subnode);
 737                 if (addr == FDT_ADDR_T_NONE)
 738                         return -ENOMEM;
 739
 740                 instance->port_base = map_sysmem(addr, 0);
 741                 instance->index = index;
 742                 instance->np = ofnode_to_np(subnode);
 743                 tphy->phys[index] = instance;
 744                 index++;
 745
 746                 err = clk_get_by_name_nodev_optional(subnode, "ref",
 747                                                      &instance->ref_clk);
 748                 if (err)
 749                         return err;
 750
 751                 err = clk_get_by_name_nodev_optional(subnode, "da_ref",
 752                                                      &instance->da_ref_clk);
 753                 if (err)
 754                         return err;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static struct tphy_pdata tphy_v1_pdata = {
 761         .version = MTK_TPHY_V1,
 762 };
 763
 764 static struct tphy_pdata tphy_v2_pdata = {
 765         .version = MTK_TPHY_V2,
 766 };
 767
 768 static struct tphy_pdata mt8195_pdata = {
 769         .version = MTK_TPHY_V2,
 770         .sw_pll_48m_to_26m = true,
 771 };
 772
 773 static const struct udevice_id mtk_tphy_id_table[] = {
 774         {
 775                 .compatible = "mediatek,generic-tphy-v1",
 776                 .data = (ulong)&tphy_v1_pdata,
 777         },
 778         {
 779                 .compatible = "mediatek,generic-tphy-v2",
 780                 .data = (ulong)&tphy_v2_pdata,
 781         },
 782         {
 783                 .compatible = "mediatek,mt8195-tphy",
 784                 .data = (ulong)&mt8195_pdata,
 785         },
 786         { }
 787 };
 788
 789 U_BOOT_DRIVER(mtk_tphy) = {
 790         .name           = "mtk-tphy",
 791         .id             = UCLASS_PHY,
 792         .of_match       = mtk_tphy_id_table,
 793         .ops            = &mtk_tphy_ops,
 794         .probe          = mtk_tphy_probe,
 795         .priv_auto      = sizeof(struct mtk_tphy),
 796 };