1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2013 NVIDIA Corporation
4 * Copyright (C) 2018 Cadence Design Systems Inc.
10 #include <phy-mipi-dphy.h>
12 #define PSEC_PER_SEC 1000000000000LL
15 * Minimum D-PHY timings based on MIPI D-PHY specification. Derived
16 * from the valid ranges specified in Section 6.9, Table 14, Page 41
17 * of the D-PHY specification (v2.1).
19 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
22 struct phy_configure_opts_mipi_dphy *cfg)
24 unsigned long long hs_clk_rate;
25 unsigned long long ui;
30 hs_clk_rate = pixel_clock * bpp;
31 do_div(hs_clk_rate, lanes);
33 ui = ALIGN(PSEC_PER_SEC, hs_clk_rate);
34 do_div(ui, hs_clk_rate);
37 cfg->clk_post = 60000 + 52 * ui;
39 cfg->clk_prepare = 38000;
40 cfg->clk_settle = 95000;
42 cfg->clk_trail = 60000;
43 cfg->clk_zero = 262000;
46 cfg->hs_exit = 100000;
47 cfg->hs_prepare = 40000 + 4 * ui;
48 cfg->hs_zero = 105000 + 6 * ui;
49 cfg->hs_settle = 85000 + 6 * ui;
53 * The MIPI D-PHY specification (Section 6.9, v1.2, Table 14, Page 40)
54 * contains this formula as:
56 * T_HS-TRAIL = max(n * 8 * ui, 60 + n * 4 * ui)
58 * where n = 1 for forward-direction HS mode and n = 4 for reverse-
59 * direction HS mode. There's only one setting and this function does
60 * not parameterize on anything other that ui, so this code will
61 * assumes that reverse-direction HS mode is supported and uses n = 4.
63 cfg->hs_trail = max(4 * 8 * ui, 60000 + 4 * 4 * ui);
67 cfg->ta_get = 5 * cfg->lpx;
68 cfg->ta_go = 4 * cfg->lpx;
69 cfg->ta_sure = 2 * cfg->lpx;
72 cfg->hs_clk_rate = hs_clk_rate;
79 * Validate D-PHY configuration according to MIPI D-PHY specification
80 * (v1.2, Section Section 6.9 "Global Operation Timing Parameters").
82 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg)
84 unsigned long long ui;
89 ui = ALIGN(PSEC_PER_SEC, cfg->hs_clk_rate);
90 do_div(ui, cfg->hs_clk_rate);
92 if (cfg->clk_miss > 60000)
95 if (cfg->clk_post < (60000 + 52 * ui))
98 if (cfg->clk_pre < 8000)
101 if (cfg->clk_prepare < 38000 || cfg->clk_prepare > 95000)
104 if (cfg->clk_settle < 95000 || cfg->clk_settle > 300000)
107 if (cfg->clk_term_en > 38000)
110 if (cfg->clk_trail < 60000)
113 if ((cfg->clk_prepare + cfg->clk_zero) < 300000)
116 if (cfg->d_term_en > (35000 + 4 * ui))
119 if (cfg->eot > (105000 + 12 * ui))
122 if (cfg->hs_exit < 100000)
125 if (cfg->hs_prepare < (40000 + 4 * ui) ||
126 cfg->hs_prepare > (85000 + 6 * ui))
129 if ((cfg->hs_prepare + cfg->hs_zero) < (145000 + 10 * ui))
132 if ((cfg->hs_settle < (85000 + 6 * ui)) ||
133 (cfg->hs_settle > (145000 + 10 * ui)))
136 if (cfg->hs_skip < 40000 || cfg->hs_skip > (55000 + 4 * ui))
139 if (cfg->hs_trail < max(8 * ui, 60000 + 4 * ui))
145 if (cfg->lpx < 50000)
148 if (cfg->ta_get != (5 * cfg->lpx))
151 if (cfg->ta_go != (4 * cfg->lpx))
154 if (cfg->ta_sure < cfg->lpx || cfg->ta_sure > (2 * cfg->lpx))
157 if (cfg->wakeup < 1000)