1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019 Stefan Roese <sr@denx.de>
5 * Derived from linux/drivers/phy/ralink/phy-ralink-usb.c
6 * Copyright (C) 2017 John Crispin <john@phrozen.org>
12 #include <generic-phy.h>
15 #include <linux/bitops.h>
17 #define OFS_U2_PHY_AC0 0x800
18 #define USBPLL_FBDIV_S 16
19 #define USBPLL_FBDIV_M GENMASK(22, 16)
21 #define BG_TRIM_M GENMASK(11, 8)
23 #define BG_RBSEL_M GENMASK(7, 6)
25 #define BG_RASEL_M GENMASK(5, 4)
27 #define BGR_DIV_M GENMASK(3, 2)
30 #define OFS_U2_PHY_AC1 0x804
31 #define VRT_VREF_SEL_S 28
32 #define VRT_VREF_SEL_M GENMASK(30, 28)
33 #define TERM_VREF_SEL_S 24
34 #define TERM_VREF_SEL_M GENMASK(26, 24)
35 #define USBPLL_RSVD BIT(4)
36 #define USBPLL_ACCEN BIT(3)
37 #define USBPLL_LF BIT(2)
39 #define OFS_U2_PHY_AC2 0x808
41 #define OFS_U2_PHY_ACR0 0x810
42 #define HSTX_SRCAL_EN BIT(23)
43 #define HSTX_SRCTRL_S 16
44 #define HSTX_SRCTRL_M GENMASK(18, 16)
46 #define OFS_U2_PHY_ACR3 0x81C
47 #define HSTX_DBIST_S 28
48 #define HSTX_DBIST_M GENMASK(31, 28)
49 #define HSRX_BIAS_EN_SEL_S 20
50 #define HSRX_BIAS_EN_SEL_M GENMASK(21, 20)
52 #define OFS_U2_PHY_DCR0 0x860
53 #define PHYD_RESERVE_S 8
54 #define PHYD_RESERVE_M GENMASK(23, 8)
56 #define CDR_FILT_M GENMASK(3, 0)
58 #define OFS_U2_PHY_DTM0 0x868
59 #define FORCE_USB_CLKEN BIT(25)
61 #define OFS_FM_CR0 0xf00
62 #define FREQDET_EN BIT(24)
64 #define CYCLECNT_M GENMASK(23, 0)
66 #define OFS_FM_MONR0 0xf0c
68 #define OFS_FM_MONR1 0xf10
69 #define FRCK_EN BIT(8)
71 #define U2_SR_COEF_7628 32
73 struct mt76x8_usb_phy {
75 struct clk cg; /* for clock gating */
76 struct reset_ctl rst_phy;
79 static void phy_w32(struct mt76x8_usb_phy *phy, u32 reg, u32 val)
81 writel(val, phy->base + reg);
84 static u32 phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
86 return readl(phy->base + reg);
89 static void phy_rmw32(struct mt76x8_usb_phy *phy, u32 reg, u32 clr, u32 set)
91 clrsetbits_32(phy->base + reg, clr, set);
94 static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
96 phy_r32(phy, OFS_U2_PHY_AC2);
97 phy_r32(phy, OFS_U2_PHY_ACR0);
98 phy_r32(phy, OFS_U2_PHY_DCR0);
100 phy_w32(phy, OFS_U2_PHY_DCR0,
101 (0xffff << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
102 phy_r32(phy, OFS_U2_PHY_DCR0);
104 phy_w32(phy, OFS_U2_PHY_DCR0,
105 (0x5555 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
106 phy_r32(phy, OFS_U2_PHY_DCR0);
108 phy_w32(phy, OFS_U2_PHY_DCR0,
109 (0xaaaa << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
110 phy_r32(phy, OFS_U2_PHY_DCR0);
112 phy_w32(phy, OFS_U2_PHY_DCR0,
113 (4 << PHYD_RESERVE_S) | (2 << CDR_FILT_S));
114 phy_r32(phy, OFS_U2_PHY_DCR0);
116 phy_w32(phy, OFS_U2_PHY_AC0,
117 (0x48 << USBPLL_FBDIV_S) | (8 << BG_TRIM_S) |
118 (1 << BG_RBSEL_S) | (2 << BG_RASEL_S) | (2 << BGR_DIV_S) |
121 phy_w32(phy, OFS_U2_PHY_AC1,
122 (4 << VRT_VREF_SEL_S) | (4 << TERM_VREF_SEL_S) | USBPLL_RSVD |
123 USBPLL_ACCEN | USBPLL_LF);
125 phy_w32(phy, OFS_U2_PHY_ACR3,
126 (12 << HSTX_DBIST_S) | (2 << HSRX_BIAS_EN_SEL_S));
128 phy_w32(phy, OFS_U2_PHY_DTM0, FORCE_USB_CLKEN);
131 static void mt76x8_usb_phy_sr_calibrate(struct mt76x8_usb_phy *phy)
136 /* Enable HS TX SR calibration */
137 phy_rmw32(phy, OFS_U2_PHY_ACR0, 0, HSTX_SRCAL_EN);
140 /* Enable free run clock */
141 phy_rmw32(phy, OFS_FM_MONR1, 0, FRCK_EN);
143 /* Set cycle count = 0x400 */
144 phy_rmw32(phy, OFS_FM_CR0, CYCLECNT_M, 0x400 << CYCLECNT_S);
146 /* Enable frequency meter */
147 phy_rmw32(phy, OFS_FM_CR0, 0, FREQDET_EN);
149 /* Wait for FM detection done, set timeout to 10ms */
150 for (i = 0; i < 10; i++) {
151 fmout = phy_r32(phy, OFS_FM_MONR0);
159 /* Disable frequency meter */
160 phy_rmw32(phy, OFS_FM_CR0, FREQDET_EN, 0);
162 /* Disable free run clock */
163 phy_rmw32(phy, OFS_FM_MONR1, FRCK_EN, 0);
165 /* Disable HS TX SR calibration */
166 phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCAL_EN, 0);
171 * set reg = (1024 / FM_OUT) * 25 * 0.028
172 * (round to the nearest digits)
174 tmp = (((1024 * 25 * U2_SR_COEF_7628) / fmout) + 500) / 1000;
177 phy_rmw32(phy, OFS_U2_PHY_ACR0, HSTX_SRCTRL_M,
178 (tmp << HSTX_SRCTRL_S) & HSTX_SRCTRL_M);
181 static int mt76x8_usb_phy_power_on(struct phy *_phy)
183 struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
185 clk_enable(&phy->cg);
187 reset_deassert(&phy->rst_phy);
190 * The SDK kernel had a delay of 100ms. however on device
191 * testing showed that 10ms is enough
195 mt76x8_usb_phy_init(phy);
196 mt76x8_usb_phy_sr_calibrate(phy);
201 static int mt76x8_usb_phy_power_off(struct phy *_phy)
203 struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
205 clk_disable(&phy->cg);
207 reset_assert(&phy->rst_phy);
212 static int mt76x8_usb_phy_probe(struct udevice *dev)
214 struct mt76x8_usb_phy *phy = dev_get_priv(dev);
217 phy->base = dev_read_addr_ptr(dev);
222 ret = clk_get_by_name(dev, "cg", &phy->cg);
226 ret = reset_get_by_name(dev, "phy", &phy->rst_phy);
233 static struct phy_ops mt76x8_usb_phy_ops = {
234 .power_on = mt76x8_usb_phy_power_on,
235 .power_off = mt76x8_usb_phy_power_off,
238 static const struct udevice_id mt76x8_usb_phy_ids[] = {
239 { .compatible = "mediatek,mt7628-usbphy" },
243 U_BOOT_DRIVER(mt76x8_usb_phy) = {
244 .name = "mt76x8_usb_phy",
246 .of_match = mt76x8_usb_phy_ids,
247 .ops = &mt76x8_usb_phy_ops,
248 .probe = mt76x8_usb_phy_probe,
249 .priv_auto_alloc_size = sizeof(struct mt76x8_usb_phy),