drivers/phy/meson-gxl-usb2.c

   1 /*
   2  * Meson GXL and GXM USB2 PHY driver
   3  *
   4  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   5  * Copyright (C) 2018 BayLibre, SAS
   6  * Author: Neil Armstrong <narmstron@baylibre.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <asm/io.h>
  13 #include <bitfield.h>
  14 #include <dm.h>
  15 #include <errno.h>
  16 #include <generic-phy.h>
  17 #include <regmap.h>
  18 #include <power/regulator.h>
  19 #include <clk.h>
  20
  21 #include <linux/bitops.h>
  22 #include <linux/compat.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* bits [31:27] are read-only */
  27 #define U2P_R0                                                  0x0
  28         #define U2P_R0_BYPASS_SEL                               BIT(0)
  29         #define U2P_R0_BYPASS_DM_EN                             BIT(1)
  30         #define U2P_R0_BYPASS_DP_EN                             BIT(2)
  31         #define U2P_R0_TXBITSTUFF_ENH                           BIT(3)
  32         #define U2P_R0_TXBITSTUFF_EN                            BIT(4)
  33         #define U2P_R0_DM_PULLDOWN                              BIT(5)
  34         #define U2P_R0_DP_PULLDOWN                              BIT(6)
  35         #define U2P_R0_DP_VBUS_VLD_EXT_SEL                      BIT(7)
  36         #define U2P_R0_DP_VBUS_VLD_EXT                          BIT(8)
  37         #define U2P_R0_ADP_PRB_EN                               BIT(9)
  38         #define U2P_R0_ADP_DISCHARGE                            BIT(10)
  39         #define U2P_R0_ADP_CHARGE                               BIT(11)
  40         #define U2P_R0_DRV_VBUS                                 BIT(12)
  41         #define U2P_R0_ID_PULLUP                                BIT(13)
  42         #define U2P_R0_LOOPBACK_EN_B                            BIT(14)
  43         #define U2P_R0_OTG_DISABLE                              BIT(15)
  44         #define U2P_R0_COMMON_ONN                               BIT(16)
  45         #define U2P_R0_FSEL_MASK                                GENMASK(19, 17)
  46         #define U2P_R0_REF_CLK_SEL_MASK                         GENMASK(21, 20)
  47         #define U2P_R0_POWER_ON_RESET                           BIT(22)
  48         #define U2P_R0_V_ATE_TEST_EN_B_MASK                     GENMASK(24, 23)
  49         #define U2P_R0_ID_SET_ID_DQ                             BIT(25)
  50         #define U2P_R0_ATE_RESET                                BIT(26)
  51         #define U2P_R0_FSV_MINUS                                BIT(27)
  52         #define U2P_R0_FSV_PLUS                                 BIT(28)
  53         #define U2P_R0_BYPASS_DM_DATA                           BIT(29)
  54         #define U2P_R0_BYPASS_DP_DATA                           BIT(30)
  55
  56 #define U2P_R1                                                  0x4
  57         #define U2P_R1_BURN_IN_TEST                             BIT(0)
  58         #define U2P_R1_ACA_ENABLE                               BIT(1)
  59         #define U2P_R1_DCD_ENABLE                               BIT(2)
  60         #define U2P_R1_VDAT_SRC_EN_B                            BIT(3)
  61         #define U2P_R1_VDAT_DET_EN_B                            BIT(4)
  62         #define U2P_R1_CHARGES_SEL                              BIT(5)
  63         #define U2P_R1_TX_PREEMP_PULSE_TUNE                     BIT(6)
  64         #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK                  GENMASK(8, 7)
  65         #define U2P_R1_TX_RES_TUNE_MASK                         GENMASK(10, 9)
  66         #define U2P_R1_TX_RISE_TUNE_MASK                        GENMASK(12, 11)
  67         #define U2P_R1_TX_VREF_TUNE_MASK                        GENMASK(16, 13)
  68         #define U2P_R1_TX_FSLS_TUNE_MASK                        GENMASK(20, 17)
  69         #define U2P_R1_TX_HSXV_TUNE_MASK                        GENMASK(22, 21)
  70         #define U2P_R1_OTG_TUNE_MASK                            GENMASK(25, 23)
  71         #define U2P_R1_SQRX_TUNE_MASK                           GENMASK(28, 26)
  72         #define U2P_R1_COMP_DIS_TUNE_MASK                       GENMASK(31, 29)
  73
  74 /* bits [31:14] are read-only */
  75 #define U2P_R2                                                  0x8
  76         #define U2P_R2_TESTDATA_IN_MASK                         GENMASK(7, 0)
  77         #define U2P_R2_TESTADDR_MASK                            GENMASK(11, 8)
  78         #define U2P_R2_TESTDATA_OUT_SEL                         BIT(12)
  79         #define U2P_R2_TESTCLK                                  BIT(13)
  80         #define U2P_R2_TESTDATA_OUT_MASK                        GENMASK(17, 14)
  81         #define U2P_R2_ACA_PIN_RANGE_C                          BIT(18)
  82         #define U2P_R2_ACA_PIN_RANGE_B                          BIT(19)
  83         #define U2P_R2_ACA_PIN_RANGE_A                          BIT(20)
  84         #define U2P_R2_ACA_PIN_GND                              BIT(21)
  85         #define U2P_R2_ACA_PIN_FLOAT                            BIT(22)
  86         #define U2P_R2_CHARGE_DETECT                            BIT(23)
  87         #define U2P_R2_DEVICE_SESSION_VALID                     BIT(24)
  88         #define U2P_R2_ADP_PROBE                                BIT(25)
  89         #define U2P_R2_ADP_SENSE                                BIT(26)
  90         #define U2P_R2_SESSION_END                              BIT(27)
  91         #define U2P_R2_VBUS_VALID                               BIT(28)
  92         #define U2P_R2_B_VALID                                  BIT(29)
  93         #define U2P_R2_A_VALID                                  BIT(30)
  94         #define U2P_R2_ID_DIG                                   BIT(31)
  95
  96 #define U2P_R3                                                  0xc
  97
  98 #define RESET_COMPLETE_TIME                             500
  99
 100 struct phy_meson_gxl_usb2_priv {
 101         struct regmap           *regmap;
 102 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 103         struct udevice          *phy_supply;
 104 #endif
 105 #if CONFIG_IS_ENABLED(CLK)
 106         struct clk              clk;
 107 #endif
 108 };
 109
 110 static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
 111 {
 112         uint val;
 113
 114         regmap_read(priv->regmap, U2P_R0, &val);
 115
 116         /* reset the PHY and wait until settings are stabilized */
 117         val |= U2P_R0_POWER_ON_RESET;
 118         regmap_write(priv->regmap, U2P_R0, val);
 119         udelay(RESET_COMPLETE_TIME);
 120
 121         val &= ~U2P_R0_POWER_ON_RESET;
 122         regmap_write(priv->regmap, U2P_R0, val);
 123         udelay(RESET_COMPLETE_TIME);
 124 }
 125
 126 static void
 127 phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
 128 {
 129         uint val;
 130
 131         regmap_read(priv->regmap, U2P_R0, &val);
 132         val |= U2P_R0_DM_PULLDOWN;
 133         val |= U2P_R0_DP_PULLDOWN;
 134         val &= ~U2P_R0_ID_PULLUP;
 135         regmap_write(priv->regmap, U2P_R0, val);
 136
 137         phy_meson_gxl_usb2_reset(priv);
 138 }
 139
 140 static int phy_meson_gxl_usb2_power_on(struct phy *phy)
 141 {
 142         struct udevice *dev = phy->dev;
 143         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 144         uint val;
 145
 146         regmap_read(priv->regmap, U2P_R0, &val);
 147         /* power on the PHY by taking it out of reset mode */
 148         val &= ~U2P_R0_POWER_ON_RESET;
 149         regmap_write(priv->regmap, U2P_R0, val);
 150
 151         phy_meson_gxl_usb2_set_host_mode(priv);
 152
 153 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 154         if (priv->phy_supply) {
 155                 int ret = regulator_set_enable(priv->phy_supply, true);
 156                 if (ret)
 157                         return ret;
 158         }
 159 #endif
 160
 161         return 0;
 162 }
 163
 164 static int phy_meson_gxl_usb2_power_off(struct phy *phy)
 165 {
 166         struct udevice *dev = phy->dev;
 167         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 168         uint val;
 169
 170         regmap_read(priv->regmap, U2P_R0, &val);
 171         /* power off the PHY by putting it into reset mode */
 172         val |= U2P_R0_POWER_ON_RESET;
 173         regmap_write(priv->regmap, U2P_R0, val);
 174
 175 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 176         if (priv->phy_supply) {
 177                 int ret = regulator_set_enable(priv->phy_supply, false);
 178                 if (ret) {
 179                         pr_err("Error disabling PHY supply\n");
 180                         return ret;
 181                 }
 182         }
 183 #endif
 184
 185         return 0;
 186 }
 187
 188 struct phy_ops meson_gxl_usb2_phy_ops = {
 189         .power_on = phy_meson_gxl_usb2_power_on,
 190         .power_off = phy_meson_gxl_usb2_power_off,
 191 };
 192
 193 int meson_gxl_usb2_phy_probe(struct udevice *dev)
 194 {
 195         struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
 196         int ret;
 197
 198         ret = regmap_init_mem(dev, &priv->regmap);
 199         if (ret)
 200                 return ret;
 201
 202 #if CONFIG_IS_ENABLED(CLK)
 203         ret = clk_get_by_index(dev, 0, &priv->clk);
 204         if (ret < 0)
 205                 return ret;
 206
 207         ret = clk_enable(&priv->clk);
 208         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 209                 pr_err("failed to enable PHY clock\n");
 210                 clk_free(&priv->clk);
 211                 return ret;
 212         }
 213 #endif
 214
 215 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 216         ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
 217         if (ret && ret != -ENOENT) {
 218                 pr_err("Failed to get PHY regulator\n");
 219                 return ret;
 220         }
 221 #endif
 222
 223         return 0;
 224 }
 225
 226 static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
 227         { .compatible = "amlogic,meson-gxl-usb2-phy" },
 228         { }
 229 };
 230
 231 U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
 232         .name = "meson_gxl_usb2_phy",
 233         .id = UCLASS_PHY,
 234         .of_match = meson_gxl_usb2_phy_ids,
 235         .probe = meson_gxl_usb2_phy_probe,
 236         .ops = &meson_gxl_usb2_phy_ops,
 237         .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
 238 };