drivers/phy/meson-gxbb-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Meson8, Meson8b and GXBB USB2 PHY driver
   4  *
   5  * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  * Copyright (C) 2018 BayLibre, SAS
   7  *
   8  * Author: Beniamino Galvani <b.galvani@gmail.com>
   9  */
  10
  11 #include <common.h>
  12 #include <clk.h>
  13 #include <dm.h>
  14 #include <generic-phy.h>
  15 #include <regmap.h>
  16 #include <reset.h>
  17 #include <linux/bitops.h>
  18
  19 #define REG_CONFIG                                      0x00
  20         #define REG_CONFIG_CLK_EN                       BIT(0)
  21         #define REG_CONFIG_CLK_SEL_MASK                 GENMASK(3, 1)
  22         #define REG_CONFIG_CLK_DIV_MASK                 GENMASK(10, 4)
  23         #define REG_CONFIG_CLK_32k_ALTSEL               BIT(15)
  24         #define REG_CONFIG_TEST_TRIG                    BIT(31)
  25
  26 #define REG_CTRL                                        0x04
  27         #define REG_CTRL_SOFT_PRST                      BIT(0)
  28         #define REG_CTRL_SOFT_HRESET                    BIT(1)
  29         #define REG_CTRL_SS_SCALEDOWN_MODE_MASK         GENMASK(3, 2)
  30         #define REG_CTRL_CLK_DET_RST                    BIT(4)
  31         #define REG_CTRL_INTR_SEL                       BIT(5)
  32         #define REG_CTRL_CLK_DETECTED                   BIT(8)
  33         #define REG_CTRL_SOF_SENT_RCVD_TGL              BIT(9)
  34         #define REG_CTRL_SOF_TOGGLE_OUT                 BIT(10)
  35         #define REG_CTRL_POWER_ON_RESET                 BIT(15)
  36         #define REG_CTRL_SLEEPM                         BIT(16)
  37         #define REG_CTRL_TX_BITSTUFF_ENN_H              BIT(17)
  38         #define REG_CTRL_TX_BITSTUFF_ENN                BIT(18)
  39         #define REG_CTRL_COMMON_ON                      BIT(19)
  40         #define REG_CTRL_REF_CLK_SEL_MASK               GENMASK(21, 20)
  41         #define REG_CTRL_REF_CLK_SEL_SHIFT              20
  42         #define REG_CTRL_FSEL_MASK                      GENMASK(24, 22)
  43         #define REG_CTRL_FSEL_SHIFT                     22
  44         #define REG_CTRL_PORT_RESET                     BIT(25)
  45         #define REG_CTRL_THREAD_ID_MASK                 GENMASK(31, 26)
  46
  47 /* bits [31:26], [24:21] and [15:3] seem to be read-only */
  48 #define REG_ADP_BC                                      0x0c
  49         #define REG_ADP_BC_VBUS_VLD_EXT_SEL             BIT(0)
  50         #define REG_ADP_BC_VBUS_VLD_EXT                 BIT(1)
  51         #define REG_ADP_BC_OTG_DISABLE                  BIT(2)
  52         #define REG_ADP_BC_ID_PULLUP                    BIT(3)
  53         #define REG_ADP_BC_DRV_VBUS                     BIT(4)
  54         #define REG_ADP_BC_ADP_PRB_EN                   BIT(5)
  55         #define REG_ADP_BC_ADP_DISCHARGE                BIT(6)
  56         #define REG_ADP_BC_ADP_CHARGE                   BIT(7)
  57         #define REG_ADP_BC_SESS_END                     BIT(8)
  58         #define REG_ADP_BC_DEVICE_SESS_VLD              BIT(9)
  59         #define REG_ADP_BC_B_VALID                      BIT(10)
  60         #define REG_ADP_BC_A_VALID                      BIT(11)
  61         #define REG_ADP_BC_ID_DIG                       BIT(12)
  62         #define REG_ADP_BC_VBUS_VALID                   BIT(13)
  63         #define REG_ADP_BC_ADP_PROBE                    BIT(14)
  64         #define REG_ADP_BC_ADP_SENSE                    BIT(15)
  65         #define REG_ADP_BC_ACA_ENABLE                   BIT(16)
  66         #define REG_ADP_BC_DCD_ENABLE                   BIT(17)
  67         #define REG_ADP_BC_VDAT_DET_EN_B                BIT(18)
  68         #define REG_ADP_BC_VDAT_SRC_EN_B                BIT(19)
  69         #define REG_ADP_BC_CHARGE_SEL                   BIT(20)
  70         #define REG_ADP_BC_CHARGE_DETECT                BIT(21)
  71         #define REG_ADP_BC_ACA_PIN_RANGE_C              BIT(22)
  72         #define REG_ADP_BC_ACA_PIN_RANGE_B              BIT(23)
  73         #define REG_ADP_BC_ACA_PIN_RANGE_A              BIT(24)
  74         #define REG_ADP_BC_ACA_PIN_GND                  BIT(25)
  75         #define REG_ADP_BC_ACA_PIN_FLOAT                BIT(26)
  76
  77 #define RESET_COMPLETE_TIME                             500
  78 #define ACA_ENABLE_COMPLETE_TIME                        50
  79
  80 struct phy_meson_gxbb_usb2_priv {
  81         struct regmap *regmap;
  82         struct reset_ctl_bulk resets;
  83 };
  84
  85 static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
  86 {
  87         struct udevice *dev = phy->dev;
  88         struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
  89         uint val;
  90
  91         regmap_update_bits(priv->regmap, REG_CONFIG,
  92                            REG_CONFIG_CLK_32k_ALTSEL,
  93                            REG_CONFIG_CLK_32k_ALTSEL);
  94         regmap_update_bits(priv->regmap, REG_CTRL,
  95                            REG_CTRL_REF_CLK_SEL_MASK,
  96                            0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
  97         regmap_update_bits(priv->regmap, REG_CTRL,
  98                            REG_CTRL_FSEL_MASK,
  99                            0x5 << REG_CTRL_FSEL_SHIFT);
 100
 101         /* reset the PHY */
 102         regmap_update_bits(priv->regmap, REG_CTRL,
 103                            REG_CTRL_POWER_ON_RESET,
 104                            REG_CTRL_POWER_ON_RESET);
 105         udelay(RESET_COMPLETE_TIME);
 106         regmap_update_bits(priv->regmap, REG_CTRL,
 107                            REG_CTRL_POWER_ON_RESET,
 108                            0);
 109         udelay(RESET_COMPLETE_TIME);
 110
 111         regmap_update_bits(priv->regmap, REG_CTRL,
 112                            REG_CTRL_SOF_TOGGLE_OUT,
 113                            REG_CTRL_SOF_TOGGLE_OUT);
 114
 115         /* Set host mode */
 116         regmap_update_bits(priv->regmap, REG_ADP_BC,
 117                            REG_ADP_BC_ACA_ENABLE,
 118                            REG_ADP_BC_ACA_ENABLE);
 119         udelay(ACA_ENABLE_COMPLETE_TIME);
 120
 121         regmap_read(priv->regmap, REG_ADP_BC, &val);
 122         if (val & REG_ADP_BC_ACA_PIN_FLOAT) {
 123                 pr_err("Error powering on GXBB USB PHY\n");
 124                 return -EINVAL;
 125         }
 126
 127         return 0;
 128 }
 129
 130 static struct phy_ops meson_gxbb_usb2_phy_ops = {
 131         .power_on = phy_meson_gxbb_usb2_power_on,
 132 };
 133
 134 static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
 135 {
 136         struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
 137         struct clk clk_usb_general, clk_usb;
 138         int ret;
 139
 140         ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
 141         if (ret)
 142                 return ret;
 143
 144         ret = clk_get_by_name(dev, "usb_general", &clk_usb_general);
 145         if (ret)
 146                 return ret;
 147
 148         ret = clk_enable(&clk_usb_general);
 149         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 150                 pr_err("Failed to enable PHY general clock\n");
 151                 return ret;
 152         }
 153
 154         ret = clk_get_by_name(dev, "usb", &clk_usb);
 155         if (ret)
 156                 return ret;
 157
 158         ret = clk_enable(&clk_usb);
 159         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 160                 pr_err("Failed to enable PHY clock\n");
 161                 return ret;
 162         }
 163
 164         ret = reset_get_bulk(dev, &priv->resets);
 165         if (!ret) {
 166                 ret = reset_deassert_bulk(&priv->resets);
 167                 if (ret) {
 168                         pr_err("Failed to deassert reset\n");
 169                         return ret;
 170                 }
 171         }
 172
 173         return 0;
 174 }
 175
 176 static int meson_gxbb_usb2_phy_remove(struct udevice *dev)
 177 {
 178         struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
 179
 180         return reset_release_bulk(&priv->resets);
 181 }
 182
 183 static const struct udevice_id meson_gxbb_usb2_phy_ids[] = {
 184         { .compatible = "amlogic,meson8-usb2-phy" },
 185         { .compatible = "amlogic,meson8b-usb2-phy" },
 186         { .compatible = "amlogic,meson-gxbb-usb2-phy" },
 187         { }
 188 };
 189
 190 U_BOOT_DRIVER(meson_gxbb_usb2_phy) = {
 191         .name = "meson_gxbb_usb2_phy",
 192         .id = UCLASS_PHY,
 193         .of_match = meson_gxbb_usb2_phy_ids,
 194         .probe = meson_gxbb_usb2_phy_probe,
 195         .remove = meson_gxbb_usb2_phy_remove,
 196         .ops = &meson_gxbb_usb2_phy_ops,
 197         .priv_auto      = sizeof(struct phy_meson_gxbb_usb2_priv),
 198 };