1 // SPDX-License-Identifier: GPL-2.0+
3 * Meson G12A USB3+PCIE Combo PHY driver
5 * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 * Copyright (C) 2019 BayLibre, SAS
7 * Author: Neil Armstrong <narmstron@baylibre.com>
18 #include <generic-phy.h>
20 #include <linux/bitops.h>
21 #include <linux/compat.h>
22 #include <linux/bitfield.h>
25 #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
26 #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
29 #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
30 #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
31 #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
32 #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
33 #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
34 #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
35 #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
36 #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
39 #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
40 #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
41 #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
42 #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
45 #define PHY_R4_PHY_CR_WRITE BIT(0)
46 #define PHY_R4_PHY_CR_READ BIT(1)
47 #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
48 #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
49 #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
52 #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
53 #define PHY_R5_PHY_CR_ACK BIT(16)
54 #define PHY_R5_PHY_BS_OUT BIT(17)
56 struct phy_g12a_usb3_pcie_priv {
57 struct regmap *regmap;
58 #if CONFIG_IS_ENABLED(CLK)
61 struct reset_ctl_bulk resets;
64 static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
67 unsigned int val, reg;
70 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
72 regmap_write(priv->regmap, PHY_R4, reg);
73 regmap_write(priv->regmap, PHY_R4, reg);
75 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
77 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
78 (val & PHY_R5_PHY_CR_ACK),
83 regmap_write(priv->regmap, PHY_R4, reg);
85 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
86 !(val & PHY_R5_PHY_CR_ACK),
95 phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
96 unsigned int addr, unsigned int *data)
101 ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
105 regmap_write(priv->regmap, PHY_R4, 0);
106 regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
108 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
109 (val & PHY_R5_PHY_CR_ACK),
114 *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
116 regmap_write(priv->regmap, PHY_R4, 0);
118 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
119 !(val & PHY_R5_PHY_CR_ACK),
128 phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
129 unsigned int addr, unsigned int data)
131 unsigned int val, reg;
134 ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
138 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
140 regmap_write(priv->regmap, PHY_R4, reg);
141 regmap_write(priv->regmap, PHY_R4, reg);
143 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
145 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
146 (val & PHY_R5_PHY_CR_ACK),
151 regmap_write(priv->regmap, PHY_R4, reg);
153 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
154 (val & PHY_R5_PHY_CR_ACK) == 0,
159 regmap_write(priv->regmap, PHY_R4, reg);
161 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
163 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
164 (val & PHY_R5_PHY_CR_ACK),
169 regmap_write(priv->regmap, PHY_R4, reg);
171 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
172 (val & PHY_R5_PHY_CR_ACK) == 0,
181 phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
182 uint offset, uint mask, uint val)
187 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, ®);
193 return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
196 static int phy_meson_g12a_usb3_init(struct phy *phy)
198 struct udevice *dev = phy->dev;
199 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
203 /* TOFIX Handle PCIE mode */
205 ret = reset_assert_bulk(&priv->resets);
207 ret |= reset_deassert_bulk(&priv->resets);
211 /* Switch PHY to USB3 */
212 regmap_update_bits(priv->regmap, PHY_R0,
213 PHY_R0_PCIE_USB3_SWITCH,
214 PHY_R0_PCIE_USB3_SWITCH);
217 * WORKAROUND: There is SSPHY suspend bug due to
218 * which USB enumerates
219 * in HS mode instead of SS mode. Workaround it by asserting
220 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
223 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
228 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
233 * Fix RX Equalization setting as follows
234 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
235 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
236 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
237 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
239 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
248 ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
253 * Set EQ and TX launch amplitudes as follows
254 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
255 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
256 * LANE0.TX_OVRD_DRV_LO.EN set to 1.
258 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
265 data |= (0x7f | BIT(14));
266 ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
271 * MPLL_LOOP_CTL.PROP_CNTRL = 8
273 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
278 regmap_update_bits(priv->regmap, PHY_R2,
279 PHY_R2_PHY_TX_VBOOST_LVL,
280 FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
282 regmap_update_bits(priv->regmap, PHY_R1,
283 PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
284 FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
285 FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
290 static int phy_meson_g12a_usb3_exit(struct phy *phy)
292 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
294 return reset_assert_bulk(&priv->resets);
297 struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
298 .init = phy_meson_g12a_usb3_init,
299 .exit = phy_meson_g12a_usb3_exit,
302 int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
304 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
307 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
311 ret = reset_get_bulk(dev, &priv->resets);
312 if (ret == -ENOTSUPP)
317 #if CONFIG_IS_ENABLED(CLK)
318 ret = clk_get_by_index(dev, 0, &priv->clk);
322 ret = clk_enable(&priv->clk);
323 if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
324 pr_err("failed to enable PHY clock\n");
325 clk_free(&priv->clk);
333 static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
334 { .compatible = "amlogic,g12a-usb3-pcie-phy" },
338 U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
339 .name = "meson_g12a_usb3_pcie_phy",
341 .of_match = meson_g12a_usb3_pcie_phy_ids,
342 .probe = meson_g12a_usb3_pcie_phy_probe,
343 .ops = &meson_g12a_usb3_pcie_phy_ops,
344 .priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),