1 // SPDX-License-Identifier: GPL-2.0+
3 * Meson G12A USB3+PCIE Combo PHY driver
5 * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 * Copyright (C) 2019 BayLibre, SAS
7 * Author: Neil Armstrong <narmstron@baylibre.com>
19 #include <generic-phy.h>
20 #include <linux/delay.h>
22 #include <linux/bitops.h>
23 #include <linux/compat.h>
24 #include <linux/bitfield.h>
26 #define PHY_TYPE_PCIE 2
27 #define PHY_TYPE_USB3 4
30 #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
31 #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
34 #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
35 #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
36 #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
37 #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
38 #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
39 #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
40 #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
41 #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
44 #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
45 #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
46 #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
47 #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
50 #define PHY_R4_PHY_CR_WRITE BIT(0)
51 #define PHY_R4_PHY_CR_READ BIT(1)
52 #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
53 #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
54 #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
57 #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
58 #define PHY_R5_PHY_CR_ACK BIT(16)
59 #define PHY_R5_PHY_BS_OUT BIT(17)
61 #define PCIE_RESET_DELAY 500
63 struct phy_g12a_usb3_pcie_priv {
64 struct regmap *regmap;
65 #if CONFIG_IS_ENABLED(CLK)
68 struct reset_ctl_bulk resets;
71 static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
74 unsigned int val, reg;
77 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
79 regmap_write(priv->regmap, PHY_R4, reg);
80 regmap_write(priv->regmap, PHY_R4, reg);
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
85 (val & PHY_R5_PHY_CR_ACK),
90 regmap_write(priv->regmap, PHY_R4, reg);
92 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
93 !(val & PHY_R5_PHY_CR_ACK),
102 phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
103 unsigned int addr, unsigned int *data)
108 ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
112 regmap_write(priv->regmap, PHY_R4, 0);
113 regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
115 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
116 (val & PHY_R5_PHY_CR_ACK),
121 *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
123 regmap_write(priv->regmap, PHY_R4, 0);
125 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
126 !(val & PHY_R5_PHY_CR_ACK),
135 phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
136 unsigned int addr, unsigned int data)
138 unsigned int val, reg;
141 ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
145 reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
147 regmap_write(priv->regmap, PHY_R4, reg);
148 regmap_write(priv->regmap, PHY_R4, reg);
150 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
152 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
153 (val & PHY_R5_PHY_CR_ACK),
158 regmap_write(priv->regmap, PHY_R4, reg);
160 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
161 (val & PHY_R5_PHY_CR_ACK) == 0,
166 regmap_write(priv->regmap, PHY_R4, reg);
168 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
170 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
171 (val & PHY_R5_PHY_CR_ACK),
176 regmap_write(priv->regmap, PHY_R4, reg);
178 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
179 (val & PHY_R5_PHY_CR_ACK) == 0,
188 phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
189 uint offset, uint mask, uint val)
194 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, ®);
200 return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
203 static int phy_meson_g12a_usb3_init(struct phy *phy)
205 struct udevice *dev = phy->dev;
206 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
210 ret = reset_assert_bulk(&priv->resets);
212 ret |= reset_deassert_bulk(&priv->resets);
216 /* Switch PHY to USB3 */
217 regmap_update_bits(priv->regmap, PHY_R0,
218 PHY_R0_PCIE_USB3_SWITCH,
219 PHY_R0_PCIE_USB3_SWITCH);
222 * WORKAROUND: There is SSPHY suspend bug due to
223 * which USB enumerates
224 * in HS mode instead of SS mode. Workaround it by asserting
225 * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
228 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
233 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
238 * Fix RX Equalization setting as follows
239 * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
240 * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
241 * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
242 * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
244 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
253 ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
258 * Set EQ and TX launch amplitudes as follows
259 * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
260 * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
261 * LANE0.TX_OVRD_DRV_LO.EN set to 1.
263 ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
270 data |= (0x7f | BIT(14));
271 ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
276 * MPLL_LOOP_CTL.PROP_CNTRL = 8
278 ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
283 regmap_update_bits(priv->regmap, PHY_R2,
284 PHY_R2_PHY_TX_VBOOST_LVL,
285 FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
287 regmap_update_bits(priv->regmap, PHY_R1,
288 PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
289 FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
290 FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
295 static int phy_meson_g12a_usb3_exit(struct phy *phy)
297 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
299 return reset_assert_bulk(&priv->resets);
302 static int phy_meson_g12a_usb3_pcie_init(struct phy *phy)
304 if (phy->id == PHY_TYPE_USB3)
305 return phy_meson_g12a_usb3_init(phy);
310 static int phy_meson_g12a_usb3_pcie_exit(struct phy *phy)
312 if (phy->id == PHY_TYPE_USB3)
313 return phy_meson_g12a_usb3_exit(phy);
318 static int phy_meson_g12a_usb3_pcie_power_on(struct phy *phy)
320 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
322 if (phy->id == PHY_TYPE_USB3)
325 regmap_update_bits(priv->regmap, PHY_R0,
326 PHY_R0_PCIE_POWER_STATE,
327 FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
332 static int phy_meson_g12a_usb3_pcie_power_off(struct phy *phy)
334 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
336 if (phy->id == PHY_TYPE_USB3)
339 regmap_update_bits(priv->regmap, PHY_R0,
340 PHY_R0_PCIE_POWER_STATE,
341 FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
346 static int phy_meson_g12a_usb3_pcie_reset(struct phy *phy)
348 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
351 if (phy->id == PHY_TYPE_USB3)
354 ret = reset_assert_bulk(&priv->resets);
358 udelay(PCIE_RESET_DELAY);
360 ret = reset_deassert_bulk(&priv->resets);
364 udelay(PCIE_RESET_DELAY);
369 struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
370 .init = phy_meson_g12a_usb3_pcie_init,
371 .exit = phy_meson_g12a_usb3_pcie_exit,
372 .power_on = phy_meson_g12a_usb3_pcie_power_on,
373 .power_off = phy_meson_g12a_usb3_pcie_power_off,
374 .reset = phy_meson_g12a_usb3_pcie_reset,
377 int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
379 struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
382 ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
386 ret = reset_get_bulk(dev, &priv->resets);
387 if (ret == -ENOTSUPP)
392 #if CONFIG_IS_ENABLED(CLK)
393 ret = clk_get_by_index(dev, 0, &priv->clk);
397 ret = clk_enable(&priv->clk);
398 if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
399 pr_err("failed to enable PHY clock\n");
400 clk_free(&priv->clk);
408 static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
409 { .compatible = "amlogic,g12a-usb3-pcie-phy" },
413 U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
414 .name = "meson_g12a_usb3_pcie_phy",
416 .of_match = meson_g12a_usb3_pcie_phy_ids,
417 .probe = meson_g12a_usb3_pcie_phy_probe,
418 .ops = &meson_g12a_usb3_pcie_phy_ops,
419 .priv_auto = sizeof(struct phy_g12a_usb3_pcie_priv),