drivers/phy/mediatek/phy-mtk-xsphy.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * MediaTek USB3.1 gen2 xsphy Driver
   4  *
   5  * Copyright (c) 2018 MediaTek Inc.
   6  * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   7  *
   8  */
   9
  10 #include <dt-bindings/phy/phy.h>
  11 #include <linux/clk.h>
  12 #include <linux/delay.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/of_address.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18
  19 #include "phy-mtk-io.h"
  20
  21 /* u2 phy banks */
  22 #define SSUSB_SIFSLV_MISC               0x000
  23 #define SSUSB_SIFSLV_U2FREQ             0x100
  24 #define SSUSB_SIFSLV_U2PHY_COM  0x300
  25
  26 /* u3 phy shared banks */
  27 #define SSPXTP_SIFSLV_DIG_GLB           0x000
  28 #define SSPXTP_SIFSLV_PHYA_GLB          0x100
  29
  30 /* u3 phy banks */
  31 #define SSPXTP_SIFSLV_DIG_LN_TOP        0x000
  32 #define SSPXTP_SIFSLV_DIG_LN_TX0        0x100
  33 #define SSPXTP_SIFSLV_DIG_LN_RX0        0x200
  34 #define SSPXTP_SIFSLV_DIG_LN_DAIF       0x300
  35 #define SSPXTP_SIFSLV_PHYA_LN           0x400
  36
  37 #define XSP_U2FREQ_FMCR0        ((SSUSB_SIFSLV_U2FREQ) + 0x00)
  38 #define P2F_RG_FREQDET_EN       BIT(24)
  39 #define P2F_RG_CYCLECNT         GENMASK(23, 0)
  40 #define P2F_RG_CYCLECNT_VAL(x)  ((P2F_RG_CYCLECNT) & (x))
  41
  42 #define XSP_U2FREQ_MMONR0  ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
  43
  44 #define XSP_U2FREQ_FMMONR1      ((SSUSB_SIFSLV_U2FREQ) + 0x10)
  45 #define P2F_RG_FRCK_EN          BIT(8)
  46 #define P2F_USB_FM_VALID        BIT(0)
  47
  48 #define XSP_USBPHYACR0  ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
  49 #define P2A0_RG_INTR_EN BIT(5)
  50
  51 #define XSP_USBPHYACR1          ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
  52 #define P2A1_RG_INTR_CAL                GENMASK(23, 19)
  53 #define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
  54 #define P2A1_RG_VRT_SEL                 GENMASK(14, 12)
  55 #define P2A1_RG_VRT_SEL_VAL(x)  ((0x7 & (x)) << 12)
  56 #define P2A1_RG_TERM_SEL                GENMASK(10, 8)
  57 #define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
  58
  59 #define XSP_USBPHYACR5          ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
  60 #define P2A5_RG_HSTX_SRCAL_EN   BIT(15)
  61 #define P2A5_RG_HSTX_SRCTRL             GENMASK(14, 12)
  62 #define P2A5_RG_HSTX_SRCTRL_VAL(x)      ((0x7 & (x)) << 12)
  63
  64 #define XSP_USBPHYACR6          ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
  65 #define P2A6_RG_BC11_SW_EN      BIT(23)
  66 #define P2A6_RG_OTG_VBUSCMP_EN  BIT(20)
  67
  68 #define XSP_U2PHYDTM1           ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
  69 #define P2D_FORCE_IDDIG         BIT(9)
  70 #define P2D_RG_VBUSVALID        BIT(5)
  71 #define P2D_RG_SESSEND          BIT(4)
  72 #define P2D_RG_AVALID           BIT(2)
  73 #define P2D_RG_IDDIG            BIT(1)
  74
  75 #define SSPXTP_PHYA_GLB_00              ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
  76 #define RG_XTP_GLB_BIAS_INTR_CTRL               GENMASK(21, 16)
  77 #define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x)        ((0x3f & (x)) << 16)
  78
  79 #define SSPXTP_PHYA_LN_04       ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
  80 #define RG_XTP_LN0_TX_IMPSEL            GENMASK(4, 0)
  81 #define RG_XTP_LN0_TX_IMPSEL_VAL(x)     (0x1f & (x))
  82
  83 #define SSPXTP_PHYA_LN_14       ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
  84 #define RG_XTP_LN0_RX_IMPSEL            GENMASK(4, 0)
  85 #define RG_XTP_LN0_RX_IMPSEL_VAL(x)     (0x1f & (x))
  86
  87 #define XSP_REF_CLK             26      /* MHZ */
  88 #define XSP_SLEW_RATE_COEF      17
  89 #define XSP_SR_COEF_DIVISOR     1000
  90 #define XSP_FM_DET_CYCLE_CNT    1024
  91
  92 struct xsphy_instance {
  93         struct phy *phy;
  94         void __iomem *port_base;
  95         struct clk *ref_clk;    /* reference clock of anolog phy */
  96         u32 index;
  97         u32 type;
  98         /* only for HQA test */
  99         int efuse_intr;
 100         int efuse_tx_imp;
 101         int efuse_rx_imp;
 102         /* u2 eye diagram */
 103         int eye_src;
 104         int eye_vrt;
 105         int eye_term;
 106 };
 107
 108 struct mtk_xsphy {
 109         struct device *dev;
 110         void __iomem *glb_base; /* only shared u3 sif */
 111         struct xsphy_instance **phys;
 112         int nphys;
 113         int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
 114         int src_coef;    /* coefficient for slew rate calibrate */
 115 };
 116
 117 static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
 118                                         struct xsphy_instance *inst)
 119 {
 120         void __iomem *pbase = inst->port_base;
 121         int calib_val;
 122         int fm_out;
 123         u32 tmp;
 124
 125         /* use force value */
 126         if (inst->eye_src)
 127                 return;
 128
 129         /* enable USB ring oscillator */
 130         mtk_phy_set_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
 131         udelay(1);      /* wait clock stable */
 132
 133         /* enable free run clock */
 134         mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 135
 136         /* set cycle count as 1024 */
 137         mtk_phy_update_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
 138                             P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT));
 139
 140         /* enable frequency meter */
 141         mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 142
 143         /* ignore return value */
 144         readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
 145                            (tmp & P2F_USB_FM_VALID), 10, 200);
 146
 147         fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
 148
 149         /* disable frequency meter */
 150         mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
 151
 152         /* disable free run clock */
 153         mtk_phy_clear_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
 154
 155         if (fm_out) {
 156                 /* (1024 / FM_OUT) x reference clock frequency x coefficient */
 157                 tmp = xsphy->src_ref_clk * xsphy->src_coef;
 158                 tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
 159                 calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
 160         } else {
 161                 /* if FM detection fail, set default value */
 162                 calib_val = 3;
 163         }
 164         dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
 165                 inst->index, fm_out, calib_val,
 166                 xsphy->src_ref_clk, xsphy->src_coef);
 167
 168         /* set HS slew rate */
 169         mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
 170                             P2A5_RG_HSTX_SRCTRL_VAL(calib_val));
 171
 172         /* disable USB ring oscillator */
 173         mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
 174 }
 175
 176 static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
 177                                  struct xsphy_instance *inst)
 178 {
 179         void __iomem *pbase = inst->port_base;
 180
 181         /* DP/DM BC1.1 path Disable */
 182         mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_BC11_SW_EN);
 183
 184         mtk_phy_set_bits(pbase + XSP_USBPHYACR0, P2A0_RG_INTR_EN);
 185 }
 186
 187 static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
 188                                      struct xsphy_instance *inst)
 189 {
 190         void __iomem *pbase = inst->port_base;
 191         u32 index = inst->index;
 192
 193         mtk_phy_set_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
 194
 195         mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
 196                             P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND,
 197                             P2D_RG_VBUSVALID | P2D_RG_AVALID);
 198
 199         dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
 200 }
 201
 202 static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
 203                                       struct xsphy_instance *inst)
 204 {
 205         void __iomem *pbase = inst->port_base;
 206         u32 index = inst->index;
 207
 208         mtk_phy_clear_bits(pbase + XSP_USBPHYACR6, P2A6_RG_OTG_VBUSCMP_EN);
 209
 210         mtk_phy_update_bits(pbase + XSP_U2PHYDTM1,
 211                             P2D_RG_VBUSVALID | P2D_RG_AVALID | P2D_RG_SESSEND,
 212                             P2D_RG_SESSEND);
 213
 214         dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
 215 }
 216
 217 static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
 218                                      struct xsphy_instance *inst,
 219                                      enum phy_mode mode)
 220 {
 221         u32 tmp;
 222
 223         tmp = readl(inst->port_base + XSP_U2PHYDTM1);
 224         switch (mode) {
 225         case PHY_MODE_USB_DEVICE:
 226                 tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
 227                 break;
 228         case PHY_MODE_USB_HOST:
 229                 tmp |= P2D_FORCE_IDDIG;
 230                 tmp &= ~P2D_RG_IDDIG;
 231                 break;
 232         case PHY_MODE_USB_OTG:
 233                 tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
 234                 break;
 235         default:
 236                 return;
 237         }
 238         writel(tmp, inst->port_base + XSP_U2PHYDTM1);
 239 }
 240
 241 static void phy_parse_property(struct mtk_xsphy *xsphy,
 242                                 struct xsphy_instance *inst)
 243 {
 244         struct device *dev = &inst->phy->dev;
 245
 246         switch (inst->type) {
 247         case PHY_TYPE_USB2:
 248                 device_property_read_u32(dev, "mediatek,efuse-intr",
 249                                          &inst->efuse_intr);
 250                 device_property_read_u32(dev, "mediatek,eye-src",
 251                                          &inst->eye_src);
 252                 device_property_read_u32(dev, "mediatek,eye-vrt",
 253                                          &inst->eye_vrt);
 254                 device_property_read_u32(dev, "mediatek,eye-term",
 255                                          &inst->eye_term);
 256                 dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
 257                         inst->efuse_intr, inst->eye_src,
 258                         inst->eye_vrt, inst->eye_term);
 259                 break;
 260         case PHY_TYPE_USB3:
 261                 device_property_read_u32(dev, "mediatek,efuse-intr",
 262                                          &inst->efuse_intr);
 263                 device_property_read_u32(dev, "mediatek,efuse-tx-imp",
 264                                          &inst->efuse_tx_imp);
 265                 device_property_read_u32(dev, "mediatek,efuse-rx-imp",
 266                                          &inst->efuse_rx_imp);
 267                 dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
 268                         inst->efuse_intr, inst->efuse_tx_imp,
 269                         inst->efuse_rx_imp);
 270                 break;
 271         default:
 272                 dev_err(xsphy->dev, "incompatible phy type\n");
 273                 return;
 274         }
 275 }
 276
 277 static void u2_phy_props_set(struct mtk_xsphy *xsphy,
 278                              struct xsphy_instance *inst)
 279 {
 280         void __iomem *pbase = inst->port_base;
 281
 282         if (inst->efuse_intr)
 283                 mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
 284                                     P2A1_RG_INTR_CAL_VAL(inst->efuse_intr));
 285
 286         if (inst->eye_src)
 287                 mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
 288                                     P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src));
 289
 290         if (inst->eye_vrt)
 291                 mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
 292                                     P2A1_RG_VRT_SEL_VAL(inst->eye_vrt));
 293
 294         if (inst->eye_term)
 295                 mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
 296                                     P2A1_RG_TERM_SEL_VAL(inst->eye_term));
 297 }
 298
 299 static void u3_phy_props_set(struct mtk_xsphy *xsphy,
 300                              struct xsphy_instance *inst)
 301 {
 302         void __iomem *pbase = inst->port_base;
 303
 304         if (inst->efuse_intr)
 305                 mtk_phy_update_bits(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
 306                                     RG_XTP_GLB_BIAS_INTR_CTRL,
 307                                     RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr));
 308
 309         if (inst->efuse_tx_imp)
 310                 mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_04,
 311                                     RG_XTP_LN0_TX_IMPSEL,
 312                                     RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp));
 313
 314         if (inst->efuse_rx_imp)
 315                 mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_14,
 316                                     RG_XTP_LN0_RX_IMPSEL,
 317                                     RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp));
 318 }
 319
 320 static int mtk_phy_init(struct phy *phy)
 321 {
 322         struct xsphy_instance *inst = phy_get_drvdata(phy);
 323         struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
 324         int ret;
 325
 326         ret = clk_prepare_enable(inst->ref_clk);
 327         if (ret) {
 328                 dev_err(xsphy->dev, "failed to enable ref_clk\n");
 329                 return ret;
 330         }
 331
 332         switch (inst->type) {
 333         case PHY_TYPE_USB2:
 334                 u2_phy_instance_init(xsphy, inst);
 335                 u2_phy_props_set(xsphy, inst);
 336                 break;
 337         case PHY_TYPE_USB3:
 338                 u3_phy_props_set(xsphy, inst);
 339                 break;
 340         default:
 341                 dev_err(xsphy->dev, "incompatible phy type\n");
 342                 clk_disable_unprepare(inst->ref_clk);
 343                 return -EINVAL;
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int mtk_phy_power_on(struct phy *phy)
 350 {
 351         struct xsphy_instance *inst = phy_get_drvdata(phy);
 352         struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
 353
 354         if (inst->type == PHY_TYPE_USB2) {
 355                 u2_phy_instance_power_on(xsphy, inst);
 356                 u2_phy_slew_rate_calibrate(xsphy, inst);
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int mtk_phy_power_off(struct phy *phy)
 363 {
 364         struct xsphy_instance *inst = phy_get_drvdata(phy);
 365         struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
 366
 367         if (inst->type == PHY_TYPE_USB2)
 368                 u2_phy_instance_power_off(xsphy, inst);
 369
 370         return 0;
 371 }
 372
 373 static int mtk_phy_exit(struct phy *phy)
 374 {
 375         struct xsphy_instance *inst = phy_get_drvdata(phy);
 376
 377         clk_disable_unprepare(inst->ref_clk);
 378         return 0;
 379 }
 380
 381 static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
 382 {
 383         struct xsphy_instance *inst = phy_get_drvdata(phy);
 384         struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
 385
 386         if (inst->type == PHY_TYPE_USB2)
 387                 u2_phy_instance_set_mode(xsphy, inst, mode);
 388
 389         return 0;
 390 }
 391
 392 static struct phy *mtk_phy_xlate(struct device *dev,
 393                                  struct of_phandle_args *args)
 394 {
 395         struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
 396         struct xsphy_instance *inst = NULL;
 397         struct device_node *phy_np = args->np;
 398         int index;
 399
 400         if (args->args_count != 1) {
 401                 dev_err(dev, "invalid number of cells in 'phy' property\n");
 402                 return ERR_PTR(-EINVAL);
 403         }
 404
 405         for (index = 0; index < xsphy->nphys; index++)
 406                 if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
 407                         inst = xsphy->phys[index];
 408                         break;
 409                 }
 410
 411         if (!inst) {
 412                 dev_err(dev, "failed to find appropriate phy\n");
 413                 return ERR_PTR(-EINVAL);
 414         }
 415
 416         inst->type = args->args[0];
 417         if (!(inst->type == PHY_TYPE_USB2 ||
 418               inst->type == PHY_TYPE_USB3)) {
 419                 dev_err(dev, "unsupported phy type: %d\n", inst->type);
 420                 return ERR_PTR(-EINVAL);
 421         }
 422
 423         phy_parse_property(xsphy, inst);
 424
 425         return inst->phy;
 426 }
 427
 428 static const struct phy_ops mtk_xsphy_ops = {
 429         .init           = mtk_phy_init,
 430         .exit           = mtk_phy_exit,
 431         .power_on       = mtk_phy_power_on,
 432         .power_off      = mtk_phy_power_off,
 433         .set_mode       = mtk_phy_set_mode,
 434         .owner          = THIS_MODULE,
 435 };
 436
 437 static const struct of_device_id mtk_xsphy_id_table[] = {
 438         { .compatible = "mediatek,xsphy", },
 439         { },
 440 };
 441 MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
 442
 443 static int mtk_xsphy_probe(struct platform_device *pdev)
 444 {
 445         struct device *dev = &pdev->dev;
 446         struct device_node *np = dev->of_node;
 447         struct device_node *child_np;
 448         struct phy_provider *provider;
 449         struct resource *glb_res;
 450         struct mtk_xsphy *xsphy;
 451         struct resource res;
 452         int port, retval;
 453
 454         xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
 455         if (!xsphy)
 456                 return -ENOMEM;
 457
 458         xsphy->nphys = of_get_child_count(np);
 459         xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
 460                                        sizeof(*xsphy->phys), GFP_KERNEL);
 461         if (!xsphy->phys)
 462                 return -ENOMEM;
 463
 464         xsphy->dev = dev;
 465         platform_set_drvdata(pdev, xsphy);
 466
 467         glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 468         /* optional, may not exist if no u3 phys */
 469         if (glb_res) {
 470                 /* get banks shared by multiple u3 phys */
 471                 xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
 472                 if (IS_ERR(xsphy->glb_base)) {
 473                         dev_err(dev, "failed to remap glb regs\n");
 474                         return PTR_ERR(xsphy->glb_base);
 475                 }
 476         }
 477
 478         xsphy->src_ref_clk = XSP_REF_CLK;
 479         xsphy->src_coef = XSP_SLEW_RATE_COEF;
 480         /* update parameters of slew rate calibrate if exist */
 481         device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
 482                                  &xsphy->src_ref_clk);
 483         device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
 484
 485         port = 0;
 486         for_each_child_of_node(np, child_np) {
 487                 struct xsphy_instance *inst;
 488                 struct phy *phy;
 489
 490                 inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
 491                 if (!inst) {
 492                         retval = -ENOMEM;
 493                         goto put_child;
 494                 }
 495
 496                 xsphy->phys[port] = inst;
 497
 498                 phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
 499                 if (IS_ERR(phy)) {
 500                         dev_err(dev, "failed to create phy\n");
 501                         retval = PTR_ERR(phy);
 502                         goto put_child;
 503                 }
 504
 505                 retval = of_address_to_resource(child_np, 0, &res);
 506                 if (retval) {
 507                         dev_err(dev, "failed to get address resource(id-%d)\n",
 508                                 port);
 509                         goto put_child;
 510                 }
 511
 512                 inst->port_base = devm_ioremap_resource(&phy->dev, &res);
 513                 if (IS_ERR(inst->port_base)) {
 514                         dev_err(dev, "failed to remap phy regs\n");
 515                         retval = PTR_ERR(inst->port_base);
 516                         goto put_child;
 517                 }
 518
 519                 inst->phy = phy;
 520                 inst->index = port;
 521                 phy_set_drvdata(phy, inst);
 522                 port++;
 523
 524                 inst->ref_clk = devm_clk_get(&phy->dev, "ref");
 525                 if (IS_ERR(inst->ref_clk)) {
 526                         dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
 527                         retval = PTR_ERR(inst->ref_clk);
 528                         goto put_child;
 529                 }
 530         }
 531
 532         provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
 533         return PTR_ERR_OR_ZERO(provider);
 534
 535 put_child:
 536         of_node_put(child_np);
 537         return retval;
 538 }
 539
 540 static struct platform_driver mtk_xsphy_driver = {
 541         .probe          = mtk_xsphy_probe,
 542         .driver         = {
 543                 .name   = "mtk-xsphy",
 544                 .of_match_table = mtk_xsphy_id_table,
 545         },
 546 };
 547
 548 module_platform_driver(mtk_xsphy_driver);
 549
 550 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
 551 MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
 552 MODULE_LICENSE("GPL v2");