drivers/phy/marvell/comphy_cp110.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Marvell International Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <log.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <linux/delay.h>
  15
  16 #include "comphy_core.h"
  17 #include "sata.h"
  18 #include "utmi_phy.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* Firmware related definitions used for SMC calls */
  23 #define MV_SIP_COMPHY_POWER_ON  0x82000001
  24 #define MV_SIP_COMPHY_POWER_OFF 0x82000002
  25 #define MV_SIP_COMPHY_PLL_LOCK  0x82000003
  26 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
  27
  28 /* Used to distinguish between different possible callers (U-boot/Linux) */
  29 #define COMPHY_CALLER_UBOOT                     (0x1 << 21)
  30
  31 #define COMPHY_FW_MODE_FORMAT(mode)             ((mode) << 12)
  32 #define COMPHY_FW_FORMAT(mode, idx, speeds)     \
  33                         (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
  34
  35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds)        \
  36                         (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) |   \
  37                         ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
  38
  39 /* Invert polarity are bits 1-0 of the mode */
  40 #define COMPHY_FW_SATA_FORMAT(mode, invert)     \
  41                         ((invert) | COMPHY_FW_MODE_FORMAT(mode))
  42
  43 #define COMPHY_SATA_MODE        0x1
  44 #define COMPHY_SGMII_MODE       0x2     /* SGMII 1G */
  45 #define COMPHY_HS_SGMII_MODE    0x3     /* SGMII 2.5G */
  46 #define COMPHY_USB3H_MODE       0x4
  47 #define COMPHY_USB3D_MODE       0x5
  48 #define COMPHY_PCIE_MODE        0x6
  49 #define COMPHY_RXAUI_MODE       0x7
  50 #define COMPHY_XFI_MODE         0x8
  51 #define COMPHY_SFI_MODE         0x9
  52 #define COMPHY_USB3_MODE        0xa
  53 #define COMPHY_AP_MODE          0xb
  54
  55 /* Comphy unit index macro */
  56 #define COMPHY_UNIT_ID0         0
  57 #define COMPHY_UNIT_ID1         1
  58 #define COMPHY_UNIT_ID2         2
  59 #define COMPHY_UNIT_ID3         3
  60
  61 struct utmi_phy_data {
  62         void __iomem *utmi_pll_addr;
  63         void __iomem *utmi_base_addr;
  64         void __iomem *usb_cfg_addr;
  65         void __iomem *utmi_cfg_addr;
  66         u32 utmi_phy_port;
  67 };
  68
  69 static u32 polling_with_timeout(void __iomem *addr, u32 val,
  70                                 u32 mask, unsigned long usec_timout)
  71 {
  72         u32 data;
  73
  74         do {
  75                 udelay(1);
  76                 data = readl(addr) & mask;
  77         } while (data != val  && --usec_timout > 0);
  78
  79         if (usec_timout == 0)
  80                 return data;
  81
  82         return 0;
  83 }
  84
  85 static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
  86                       u32 lane, u32 mode)
  87 {
  88         struct pt_regs pregs = {0};
  89
  90         pregs.regs[0] = function_id;
  91         pregs.regs[1] = (unsigned long)comphy_base_addr;
  92         pregs.regs[2] = lane;
  93         pregs.regs[3] = mode;
  94
  95         smc_call(&pregs);
  96
  97         /*
  98          * TODO: Firmware return 0 on success, temporary map it to u-boot
  99          * convention, but after all comphy will be reworked the convention in
 100          * u-boot should be change and this conversion removed
 101          */
 102         return pregs.regs[0] ? 0 : 1;
 103 }
 104
 105 /* This function performs RX training for all FFE possible values.
 106  * We get the result for each FFE and eventually the best FFE will
 107  * be used and set to the HW.
 108  *
 109  * Return '1' on succsess.
 110  * Return '0' on failure.
 111  */
 112 int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
 113                                  u32 lane)
 114 {
 115         int ret;
 116         u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
 117
 118         debug_enter();
 119
 120         if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
 121                 pr_err("Comphy %d isn't configured to SFI\n", lane);
 122                 return 0;
 123         }
 124
 125         /* Mode is not relevant for xfi training */
 126         ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
 127                          ptr_chip_cfg->comphy_base_addr, lane, 0);
 128
 129         debug_exit();
 130
 131         return ret;
 132 }
 133
 134 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
 135                                 void __iomem *comphy_base_addr, int cp_index,
 136                                 u32 type)
 137 {
 138         u32 mask, data, i, ret = 1;
 139         void __iomem *sata_base = NULL;
 140         int sata_node = -1; /* Set to -1 in order to read the first sata node */
 141
 142         debug_enter();
 143
 144         /*
 145          * Assumption - each CP has only one SATA controller
 146          * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
 147          * will return the first node always.
 148          * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
 149          * must be called again (according to the CP id)
 150          */
 151         for (i = 0; i < (cp_index + 1); i++)
 152                 sata_node = fdt_node_offset_by_compatible(
 153                         gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
 154
 155         if (sata_node == 0) {
 156                 pr_err("SATA node not found in FDT\n");
 157                 return 0;
 158         }
 159
 160         sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 161                 gd->fdt_blob, sata_node, "reg", 0, NULL, true);
 162         if (sata_base == NULL) {
 163                 pr_err("SATA address not found in FDT\n");
 164                 return 0;
 165         }
 166
 167         debug("SATA address found in FDT %p\n", sata_base);
 168
 169         debug("stage: MAC configuration - power down comphy\n");
 170         /*
 171          * MAC configuration powe down comphy use indirect address for
 172          * vendor spesific SATA control register
 173          */
 174         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 175                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 176                 SATA3_VENDOR_ADDR_MASK);
 177         /* SATA 0 power down */
 178         mask = SATA3_CTRL_SATA0_PD_MASK;
 179         data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
 180         /* SATA 1 power down */
 181         mask |= SATA3_CTRL_SATA1_PD_MASK;
 182         data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
 183         /* SATA SSU disable */
 184         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 185         data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 186         /* SATA port 1 disable */
 187         mask |= SATA3_CTRL_SATA_SSU_MASK;
 188         data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
 189         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 190
 191         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type);
 192
 193         /*
 194          * MAC configuration power up comphy - power up PLL/TX/RX
 195          * use indirect address for vendor spesific SATA control register
 196          */
 197         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 198                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 199                 SATA3_VENDOR_ADDR_MASK);
 200         /* SATA 0 power up */
 201         mask = SATA3_CTRL_SATA0_PD_MASK;
 202         data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
 203         /* SATA 1 power up */
 204         mask |= SATA3_CTRL_SATA1_PD_MASK;
 205         data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
 206         /* SATA SSU enable */
 207         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 208         data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 209         /* SATA port 1 enable */
 210         mask |= SATA3_CTRL_SATA_SSU_MASK;
 211         data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
 212         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 213
 214         /* MBUS request size and interface select register */
 215         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 216                 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
 217                 SATA3_VENDOR_ADDR_MASK);
 218         /* Mbus regret enable */
 219         reg_set(sata_base + SATA3_VENDOR_DATA,
 220                 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
 221
 222         ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type);
 223
 224         debug_exit();
 225         return ret;
 226 }
 227
 228 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
 229                                    void __iomem *usb_cfg_addr,
 230                                    void __iomem *utmi_cfg_addr,
 231                                    u32 utmi_phy_port)
 232 {
 233         u32 mask, data;
 234
 235         debug_enter();
 236         debug("stage:  UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
 237               utmi_index);
 238         /* Power down UTMI PHY */
 239         reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
 240                 UTMI_PHY_CFG_PU_MASK);
 241
 242         /*
 243          * If UTMI connected to USB Device, configure mux prior to PHY init
 244          * (Device can be connected to UTMI0 or to UTMI1)
 245          */
 246         if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
 247                 debug("stage:  UTMI %d - Enable Device mode and configure UTMI mux\n",
 248                       utmi_index);
 249                 /* USB3 Device UTMI enable */
 250                 mask = UTMI_USB_CFG_DEVICE_EN_MASK;
 251                 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
 252                 /* USB3 Device UTMI MUX */
 253                 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
 254                 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
 255                 reg_set(usb_cfg_addr,  data, mask);
 256         }
 257
 258         /* Set Test suspendm mode */
 259         mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
 260         data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
 261         /* Enable Test UTMI select */
 262         mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
 263         data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
 264         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
 265
 266         /* Wait for UTMI power down */
 267         mdelay(1);
 268
 269         debug_exit();
 270         return;
 271 }
 272
 273 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
 274                                    void __iomem *utmi_base_addr,
 275                                    void __iomem *usb_cfg_addr,
 276                                    void __iomem *utmi_cfg_addr,
 277                                    u32 utmi_phy_port)
 278 {
 279         u32 mask, data;
 280
 281         debug_exit();
 282         debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
 283         /* Reference Clock Divider Select */
 284         mask = UTMI_PLL_CTRL_REFDIV_MASK;
 285         data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
 286         /* Feedback Clock Divider Select - 90 for 25Mhz*/
 287         mask |= UTMI_PLL_CTRL_FBDIV_MASK;
 288         data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
 289         /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
 290         mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
 291         data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
 292         reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
 293
 294         /* Impedance Calibration Threshold Setting */
 295         mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
 296         data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
 297         reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
 298
 299         /* Start Impedance and PLL Calibration */
 300         mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
 301         data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
 302         mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
 303         data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
 304         reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
 305
 306         /* Set LS TX driver strength coarse control */
 307         mask = UTMI_TX_CH_CTRL_AMP_MASK;
 308         data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
 309         mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
 310         data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
 311         mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
 312         data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
 313         reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
 314
 315         /* Enable SQ */
 316         mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
 317         data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
 318         /* Enable analog squelch detect */
 319         mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
 320         data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
 321         mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
 322         data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
 323         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
 324
 325         /* Set External squelch calibration number */
 326         mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
 327         data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
 328         /* Enable the External squelch calibration */
 329         mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
 330         data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
 331         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
 332
 333         /* Set Control VDAT Reference Voltage - 0.325V */
 334         mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
 335         data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
 336         /* Set Control VSRC Reference Voltage - 0.6V */
 337         mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
 338         data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
 339         reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
 340
 341         debug_exit();
 342         return;
 343 }
 344
 345 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
 346                                 void __iomem *utmi_base_addr,
 347                                 void __iomem *usb_cfg_addr,
 348                                 void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
 349 {
 350         u32 data, mask, ret = 1;
 351         void __iomem *addr;
 352
 353         debug_enter();
 354         debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
 355               utmi_index);
 356         /* Power UP UTMI PHY */
 357         reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
 358                 UTMI_PHY_CFG_PU_MASK);
 359         /* Disable Test UTMI select */
 360         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
 361                 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
 362                 UTMI_CTRL_STATUS0_TEST_SEL_MASK);
 363
 364         debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
 365         addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
 366         data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
 367         mask = data;
 368         data = polling_with_timeout(addr, data, mask, 100);
 369         if (data != 0) {
 370                 pr_err("Impedance calibration is not done\n");
 371                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 372                 ret = 0;
 373         }
 374
 375         data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
 376         mask = data;
 377         data = polling_with_timeout(addr, data, mask, 100);
 378         if (data != 0) {
 379                 pr_err("PLL calibration is not done\n");
 380                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 381                 ret = 0;
 382         }
 383
 384         addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
 385         data = UTMI_PLL_CTRL_PLL_RDY_MASK;
 386         mask = data;
 387         data = polling_with_timeout(addr, data, mask, 100);
 388         if (data != 0) {
 389                 pr_err("PLL is not ready\n");
 390                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 391                 ret = 0;
 392         }
 393
 394         if (ret)
 395                 debug("Passed\n");
 396         else
 397                 debug("\n");
 398
 399         debug_exit();
 400         return ret;
 401 }
 402
 403 /*
 404  * comphy_utmi_phy_init initialize the UTMI PHY
 405  * the init split in 3 parts:
 406  * 1. Power down transceiver and PLL
 407  * 2. UTMI PHY configure
 408  * 3. Power up transceiver and PLL
 409  * Note: - Power down/up should be once for both UTMI PHYs
 410  *       - comphy_dedicated_phys_init call this function if at least there is
 411  *         one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
 412  *         legal
 413  */
 414 static void comphy_utmi_phy_init(u32 utmi_phy_count,
 415                                  struct utmi_phy_data *cp110_utmi_data)
 416 {
 417         u32 i;
 418
 419         debug_enter();
 420         /* UTMI Power down */
 421         for (i = 0; i < utmi_phy_count; i++) {
 422                 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
 423                                        cp110_utmi_data[i].usb_cfg_addr,
 424                                        cp110_utmi_data[i].utmi_cfg_addr,
 425                                        cp110_utmi_data[i].utmi_phy_port);
 426         }
 427         /* PLL Power down */
 428         debug("stage: UTMI PHY power down PLL\n");
 429         for (i = 0; i < utmi_phy_count; i++) {
 430                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 431                         0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 432         }
 433         /* UTMI configure */
 434         for (i = 0; i < utmi_phy_count; i++) {
 435                 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
 436                                        cp110_utmi_data[i].utmi_base_addr,
 437                                        cp110_utmi_data[i].usb_cfg_addr,
 438                                        cp110_utmi_data[i].utmi_cfg_addr,
 439                                        cp110_utmi_data[i].utmi_phy_port);
 440         }
 441         /* UTMI Power up */
 442         for (i = 0; i < utmi_phy_count; i++) {
 443                 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
 444                                           cp110_utmi_data[i].utmi_base_addr,
 445                                           cp110_utmi_data[i].usb_cfg_addr,
 446                                           cp110_utmi_data[i].utmi_cfg_addr,
 447                                           cp110_utmi_data[i].utmi_phy_port)) {
 448                         pr_err("Failed to initialize UTMI PHY %d\n", i);
 449                         continue;
 450                 }
 451                 printf("UTMI PHY %d initialized to ", i);
 452                 if (cp110_utmi_data[i].utmi_phy_port ==
 453                     UTMI_PHY_TO_USB3_DEVICE0)
 454                         printf("USB Device\n");
 455                 else
 456                         printf("USB Host%d\n",
 457                                cp110_utmi_data[i].utmi_phy_port);
 458         }
 459         /* PLL Power up */
 460         debug("stage: UTMI PHY power up PLL\n");
 461         for (i = 0; i < utmi_phy_count; i++) {
 462                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 463                         0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 464         }
 465
 466         debug_exit();
 467         return;
 468 }
 469
 470 /*
 471  * comphy_dedicated_phys_init initialize the dedicated PHYs
 472  * - not muxed SerDes lanes e.g. UTMI PHY
 473  */
 474 void comphy_dedicated_phys_init(void)
 475 {
 476         struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
 477         int node = -1;
 478         int node_idx;
 479         int parent = -1;
 480
 481         debug_enter();
 482         debug("Initialize USB UTMI PHYs\n");
 483
 484         for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
 485                 /* Find the UTMI phy node in device tree */
 486                 node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
 487                                                      "marvell,mvebu-utmi-2.6.0");
 488                 if (node <= 0)
 489                         break;
 490
 491                 /* check if node is enabled */
 492                 if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
 493                         continue;
 494
 495                 parent = fdt_parent_offset(gd->fdt_blob, node);
 496                 if (parent <= 0)
 497                         break;
 498
 499                 /* get base address of UTMI PLL */
 500                 cp110_utmi_data[node_idx].utmi_pll_addr =
 501                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 502                                 gd->fdt_blob, parent, "reg", 0, NULL, true);
 503                 if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
 504                         pr_err("UTMI PHY PLL address is invalid\n");
 505                         continue;
 506                 }
 507
 508                 /* get base address of UTMI phy */
 509                 cp110_utmi_data[node_idx].utmi_base_addr =
 510                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 511                                 gd->fdt_blob, node, "reg", 0, NULL, true);
 512                 if (!cp110_utmi_data[node_idx].utmi_base_addr) {
 513                         pr_err("UTMI PHY base address is invalid\n");
 514                         continue;
 515                 }
 516
 517                 /* get usb config address */
 518                 cp110_utmi_data[node_idx].usb_cfg_addr =
 519                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 520                                 gd->fdt_blob, node, "reg", 1, NULL, true);
 521                 if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
 522                         pr_err("UTMI PHY base address is invalid\n");
 523                         continue;
 524                 }
 525
 526                 /* get UTMI config address */
 527                 cp110_utmi_data[node_idx].utmi_cfg_addr =
 528                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 529                                 gd->fdt_blob, node, "reg", 2, NULL, true);
 530                 if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
 531                         pr_err("UTMI PHY base address is invalid\n");
 532                         continue;
 533                 }
 534
 535                 /*
 536                  * get the port number (to check if the utmi connected to
 537                  * host/device)
 538                  */
 539                 cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
 540                         gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
 541                 if (cp110_utmi_data[node_idx].utmi_phy_port ==
 542                                                         UTMI_PHY_INVALID) {
 543                         pr_err("UTMI PHY port type is invalid\n");
 544                         continue;
 545                 }
 546
 547                 /* count valid UTMI unit */
 548                 node_idx++;
 549         }
 550
 551         if (node_idx > 0)
 552                 comphy_utmi_phy_init(node_idx, cp110_utmi_data);
 553
 554         debug_exit();
 555 }
 556
 557 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 558                       struct comphy_map *serdes_map)
 559 {
 560         struct comphy_map *ptr_comphy_map;
 561         void __iomem *comphy_base_addr, *hpipe_base_addr;
 562         u32 comphy_max_count, lane, id, ret = 0;
 563         u32 pcie_width = 0;
 564         u32 mode;
 565
 566         debug_enter();
 567
 568         comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
 569         comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
 570         hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
 571
 572         /* Check if the first 4 lanes configured as By-4 */
 573         for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
 574              lane++, ptr_comphy_map++) {
 575                 if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
 576                         break;
 577                 pcie_width++;
 578         }
 579
 580         for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
 581              lane++, ptr_comphy_map++) {
 582                 debug("Initialize serdes number %d\n", lane);
 583                 debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
 584                 if (lane == 4) {
 585                         /*
 586                          * PCIe lanes above the first 4 lanes, can be only
 587                          * by1
 588                          */
 589                         pcie_width = 1;
 590                 }
 591                 switch (ptr_comphy_map->type) {
 592                 case COMPHY_TYPE_UNCONNECTED:
 593                         mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
 594                         ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
 595                                          ptr_chip_cfg->comphy_base_addr,
 596                                          lane, mode);
 597                 case COMPHY_TYPE_IGNORE:
 598                         continue;
 599                         break;
 600                 case COMPHY_TYPE_PEX0:
 601                 case COMPHY_TYPE_PEX1:
 602                 case COMPHY_TYPE_PEX2:
 603                 case COMPHY_TYPE_PEX3:
 604                         mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
 605                                                      ptr_comphy_map->clk_src,
 606                                                      COMPHY_PCIE_MODE,
 607                                                      ptr_comphy_map->speed);
 608                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 609                                          ptr_chip_cfg->comphy_base_addr, lane,
 610                                          mode);
 611                         break;
 612                 case COMPHY_TYPE_SATA0:
 613                 case COMPHY_TYPE_SATA1:
 614                         mode = COMPHY_FW_SATA_FORMAT(COMPHY_SATA_MODE,
 615                                                      serdes_map[lane].invert);
 616                         ret = comphy_sata_power_up(lane, hpipe_base_addr,
 617                                                    comphy_base_addr,
 618                                                    ptr_chip_cfg->cp_index,
 619                                                    mode);
 620                         break;
 621                 case COMPHY_TYPE_USB3_HOST0:
 622                 case COMPHY_TYPE_USB3_HOST1:
 623                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
 624                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 625                                          ptr_chip_cfg->comphy_base_addr, lane,
 626                                          mode);
 627                         break;
 628                 case COMPHY_TYPE_USB3_DEVICE:
 629                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
 630                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 631                                          ptr_chip_cfg->comphy_base_addr, lane,
 632                                          mode);
 633                         break;
 634                 case COMPHY_TYPE_SGMII0:
 635                 case COMPHY_TYPE_SGMII1:
 636                 case COMPHY_TYPE_SGMII2:
 637                         /* Calculate SGMII ID */
 638                         id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
 639
 640                         if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
 641                                 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
 642                                       lane);
 643                                 ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
 644                         }
 645
 646                         mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
 647                                                 ptr_comphy_map->speed);
 648                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 649                                          ptr_chip_cfg->comphy_base_addr, lane,
 650                                          mode);
 651                         break;
 652                 case COMPHY_TYPE_SFI0:
 653                 case COMPHY_TYPE_SFI1:
 654                         /* Calculate SFI id */
 655                         id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
 656                         mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
 657                                                 ptr_comphy_map->speed);
 658                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 659                                 ptr_chip_cfg->comphy_base_addr, lane, mode);
 660                         break;
 661                 case COMPHY_TYPE_RXAUI0:
 662                 case COMPHY_TYPE_RXAUI1:
 663                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
 664                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 665                                          ptr_chip_cfg->comphy_base_addr, lane,
 666                                          mode);
 667                         break;
 668                 default:
 669                         debug("Unknown SerDes type, skip initialize SerDes %d\n",
 670                               lane);
 671                         break;
 672                 }
 673                 if (ret == 0) {
 674                         /*
 675                          * If interface wans't initialized, set the lane to
 676                          * COMPHY_TYPE_UNCONNECTED state.
 677                          */
 678                         ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
 679                         pr_err("PLL is not locked - Failed to initialize lane %d\n",
 680                               lane);
 681                 }
 682         }
 683
 684         debug_exit();
 685         return 0;
 686 }