drivers/phy/marvell/comphy_cp110.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Marvell International Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <log.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <linux/delay.h>
  15
  16 #include "comphy_core.h"
  17 #include "sata.h"
  18 #include "utmi_phy.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 /* Firmware related definitions used for SMC calls */
  23 #define MV_SIP_COMPHY_POWER_ON  0x82000001
  24 #define MV_SIP_COMPHY_POWER_OFF 0x82000002
  25 #define MV_SIP_COMPHY_PLL_LOCK  0x82000003
  26 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
  27
  28 /* Used to distinguish between different possible callers (U-boot/Linux) */
  29 #define COMPHY_CALLER_UBOOT                     (0x1 << 21)
  30
  31 #define COMPHY_FW_MODE_FORMAT(mode)             ((mode) << 12)
  32 #define COMPHY_FW_FORMAT(mode, idx, speeds)     \
  33                         (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
  34
  35 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds)        \
  36                         (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) |   \
  37                         ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
  38
  39 #define COMPHY_SATA_MODE        0x1
  40 #define COMPHY_SGMII_MODE       0x2     /* SGMII 1G */
  41 #define COMPHY_HS_SGMII_MODE    0x3     /* SGMII 2.5G */
  42 #define COMPHY_USB3H_MODE       0x4
  43 #define COMPHY_USB3D_MODE       0x5
  44 #define COMPHY_PCIE_MODE        0x6
  45 #define COMPHY_RXAUI_MODE       0x7
  46 #define COMPHY_XFI_MODE         0x8
  47 #define COMPHY_SFI_MODE         0x9
  48 #define COMPHY_USB3_MODE        0xa
  49 #define COMPHY_AP_MODE          0xb
  50
  51 /* Comphy unit index macro */
  52 #define COMPHY_UNIT_ID0         0
  53 #define COMPHY_UNIT_ID1         1
  54 #define COMPHY_UNIT_ID2         2
  55 #define COMPHY_UNIT_ID3         3
  56
  57 struct utmi_phy_data {
  58         void __iomem *utmi_pll_addr;
  59         void __iomem *utmi_base_addr;
  60         void __iomem *usb_cfg_addr;
  61         void __iomem *utmi_cfg_addr;
  62         u32 utmi_phy_port;
  63 };
  64
  65 static u32 polling_with_timeout(void __iomem *addr, u32 val,
  66                                 u32 mask, unsigned long usec_timout)
  67 {
  68         u32 data;
  69
  70         do {
  71                 udelay(1);
  72                 data = readl(addr) & mask;
  73         } while (data != val  && --usec_timout > 0);
  74
  75         if (usec_timout == 0)
  76                 return data;
  77
  78         return 0;
  79 }
  80
  81 static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
  82                       u32 lane, u32 mode)
  83 {
  84         struct pt_regs pregs = {0};
  85
  86         pregs.regs[0] = function_id;
  87         pregs.regs[1] = (unsigned long)comphy_base_addr;
  88         pregs.regs[2] = lane;
  89         pregs.regs[3] = mode;
  90
  91         smc_call(&pregs);
  92
  93         /*
  94          * TODO: Firmware return 0 on success, temporary map it to u-boot
  95          * convention, but after all comphy will be reworked the convention in
  96          * u-boot should be change and this conversion removed
  97          */
  98         return pregs.regs[0] ? 0 : 1;
  99 }
 100
 101 /* This function performs RX training for all FFE possible values.
 102  * We get the result for each FFE and eventually the best FFE will
 103  * be used and set to the HW.
 104  *
 105  * Return '1' on succsess.
 106  * Return '0' on failure.
 107  */
 108 int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
 109                                  u32 lane)
 110 {
 111         int ret;
 112         u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
 113
 114         debug_enter();
 115
 116         if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
 117                 pr_err("Comphy %d isn't configured to SFI\n", lane);
 118                 return 0;
 119         }
 120
 121         /* Mode is not relevant for xfi training */
 122         ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
 123                          ptr_chip_cfg->comphy_base_addr, lane, 0);
 124
 125         debug_exit();
 126
 127         return ret;
 128 }
 129
 130 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
 131                                 void __iomem *comphy_base_addr, int cp_index,
 132                                 u32 type)
 133 {
 134         u32 mask, data, i, ret = 1;
 135         void __iomem *sata_base = NULL;
 136         int sata_node = -1; /* Set to -1 in order to read the first sata node */
 137
 138         debug_enter();
 139
 140         /*
 141          * Assumption - each CP has only one SATA controller
 142          * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
 143          * will return the first node always.
 144          * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
 145          * must be called again (according to the CP id)
 146          */
 147         for (i = 0; i < (cp_index + 1); i++)
 148                 sata_node = fdt_node_offset_by_compatible(
 149                         gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
 150
 151         if (sata_node == 0) {
 152                 pr_err("SATA node not found in FDT\n");
 153                 return 0;
 154         }
 155
 156         sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 157                 gd->fdt_blob, sata_node, "reg", 0, NULL, true);
 158         if (sata_base == NULL) {
 159                 pr_err("SATA address not found in FDT\n");
 160                 return 0;
 161         }
 162
 163         debug("SATA address found in FDT %p\n", sata_base);
 164
 165         debug("stage: MAC configuration - power down comphy\n");
 166         /*
 167          * MAC configuration powe down comphy use indirect address for
 168          * vendor spesific SATA control register
 169          */
 170         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 171                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 172                 SATA3_VENDOR_ADDR_MASK);
 173         /* SATA 0 power down */
 174         mask = SATA3_CTRL_SATA0_PD_MASK;
 175         data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
 176         /* SATA 1 power down */
 177         mask |= SATA3_CTRL_SATA1_PD_MASK;
 178         data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
 179         /* SATA SSU disable */
 180         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 181         data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 182         /* SATA port 1 disable */
 183         mask |= SATA3_CTRL_SATA_SSU_MASK;
 184         data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
 185         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 186
 187         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type);
 188
 189         /*
 190          * MAC configuration power up comphy - power up PLL/TX/RX
 191          * use indirect address for vendor spesific SATA control register
 192          */
 193         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 194                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 195                 SATA3_VENDOR_ADDR_MASK);
 196         /* SATA 0 power up */
 197         mask = SATA3_CTRL_SATA0_PD_MASK;
 198         data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
 199         /* SATA 1 power up */
 200         mask |= SATA3_CTRL_SATA1_PD_MASK;
 201         data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
 202         /* SATA SSU enable */
 203         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 204         data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 205         /* SATA port 1 enable */
 206         mask |= SATA3_CTRL_SATA_SSU_MASK;
 207         data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
 208         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 209
 210         /* MBUS request size and interface select register */
 211         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 212                 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
 213                 SATA3_VENDOR_ADDR_MASK);
 214         /* Mbus regret enable */
 215         reg_set(sata_base + SATA3_VENDOR_DATA,
 216                 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
 217
 218         ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type);
 219
 220         debug_exit();
 221         return ret;
 222 }
 223
 224 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
 225                                    void __iomem *usb_cfg_addr,
 226                                    void __iomem *utmi_cfg_addr,
 227                                    u32 utmi_phy_port)
 228 {
 229         u32 mask, data;
 230
 231         debug_enter();
 232         debug("stage:  UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
 233               utmi_index);
 234         /* Power down UTMI PHY */
 235         reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
 236                 UTMI_PHY_CFG_PU_MASK);
 237
 238         /*
 239          * If UTMI connected to USB Device, configure mux prior to PHY init
 240          * (Device can be connected to UTMI0 or to UTMI1)
 241          */
 242         if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
 243                 debug("stage:  UTMI %d - Enable Device mode and configure UTMI mux\n",
 244                       utmi_index);
 245                 /* USB3 Device UTMI enable */
 246                 mask = UTMI_USB_CFG_DEVICE_EN_MASK;
 247                 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
 248                 /* USB3 Device UTMI MUX */
 249                 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
 250                 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
 251                 reg_set(usb_cfg_addr,  data, mask);
 252         }
 253
 254         /* Set Test suspendm mode */
 255         mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
 256         data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
 257         /* Enable Test UTMI select */
 258         mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
 259         data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
 260         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
 261
 262         /* Wait for UTMI power down */
 263         mdelay(1);
 264
 265         debug_exit();
 266         return;
 267 }
 268
 269 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
 270                                    void __iomem *utmi_base_addr,
 271                                    void __iomem *usb_cfg_addr,
 272                                    void __iomem *utmi_cfg_addr,
 273                                    u32 utmi_phy_port)
 274 {
 275         u32 mask, data;
 276
 277         debug_exit();
 278         debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
 279         /* Reference Clock Divider Select */
 280         mask = UTMI_PLL_CTRL_REFDIV_MASK;
 281         data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
 282         /* Feedback Clock Divider Select - 90 for 25Mhz*/
 283         mask |= UTMI_PLL_CTRL_FBDIV_MASK;
 284         data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
 285         /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
 286         mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
 287         data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
 288         reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
 289
 290         /* Impedance Calibration Threshold Setting */
 291         mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
 292         data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
 293         reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
 294
 295         /* Start Impedance and PLL Calibration */
 296         mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
 297         data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
 298         mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
 299         data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
 300         reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
 301
 302         /* Set LS TX driver strength coarse control */
 303         mask = UTMI_TX_CH_CTRL_AMP_MASK;
 304         data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
 305         mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
 306         data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
 307         mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
 308         data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
 309         reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
 310
 311         /* Enable SQ */
 312         mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
 313         data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
 314         /* Enable analog squelch detect */
 315         mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
 316         data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
 317         mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
 318         data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
 319         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
 320
 321         /* Set External squelch calibration number */
 322         mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
 323         data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
 324         /* Enable the External squelch calibration */
 325         mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
 326         data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
 327         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
 328
 329         /* Set Control VDAT Reference Voltage - 0.325V */
 330         mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
 331         data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
 332         /* Set Control VSRC Reference Voltage - 0.6V */
 333         mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
 334         data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
 335         reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
 336
 337         debug_exit();
 338         return;
 339 }
 340
 341 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
 342                                 void __iomem *utmi_base_addr,
 343                                 void __iomem *usb_cfg_addr,
 344                                 void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
 345 {
 346         u32 data, mask, ret = 1;
 347         void __iomem *addr;
 348
 349         debug_enter();
 350         debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
 351               utmi_index);
 352         /* Power UP UTMI PHY */
 353         reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
 354                 UTMI_PHY_CFG_PU_MASK);
 355         /* Disable Test UTMI select */
 356         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
 357                 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
 358                 UTMI_CTRL_STATUS0_TEST_SEL_MASK);
 359
 360         debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
 361         addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
 362         data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
 363         mask = data;
 364         data = polling_with_timeout(addr, data, mask, 100);
 365         if (data != 0) {
 366                 pr_err("Impedance calibration is not done\n");
 367                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 368                 ret = 0;
 369         }
 370
 371         data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
 372         mask = data;
 373         data = polling_with_timeout(addr, data, mask, 100);
 374         if (data != 0) {
 375                 pr_err("PLL calibration is not done\n");
 376                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 377                 ret = 0;
 378         }
 379
 380         addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
 381         data = UTMI_PLL_CTRL_PLL_RDY_MASK;
 382         mask = data;
 383         data = polling_with_timeout(addr, data, mask, 100);
 384         if (data != 0) {
 385                 pr_err("PLL is not ready\n");
 386                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 387                 ret = 0;
 388         }
 389
 390         if (ret)
 391                 debug("Passed\n");
 392         else
 393                 debug("\n");
 394
 395         debug_exit();
 396         return ret;
 397 }
 398
 399 /*
 400  * comphy_utmi_phy_init initialize the UTMI PHY
 401  * the init split in 3 parts:
 402  * 1. Power down transceiver and PLL
 403  * 2. UTMI PHY configure
 404  * 3. Power up transceiver and PLL
 405  * Note: - Power down/up should be once for both UTMI PHYs
 406  *       - comphy_dedicated_phys_init call this function if at least there is
 407  *         one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
 408  *         legal
 409  */
 410 static void comphy_utmi_phy_init(u32 utmi_phy_count,
 411                                  struct utmi_phy_data *cp110_utmi_data)
 412 {
 413         u32 i;
 414
 415         debug_enter();
 416         /* UTMI Power down */
 417         for (i = 0; i < utmi_phy_count; i++) {
 418                 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
 419                                        cp110_utmi_data[i].usb_cfg_addr,
 420                                        cp110_utmi_data[i].utmi_cfg_addr,
 421                                        cp110_utmi_data[i].utmi_phy_port);
 422         }
 423         /* PLL Power down */
 424         debug("stage: UTMI PHY power down PLL\n");
 425         for (i = 0; i < utmi_phy_count; i++) {
 426                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 427                         0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 428         }
 429         /* UTMI configure */
 430         for (i = 0; i < utmi_phy_count; i++) {
 431                 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
 432                                        cp110_utmi_data[i].utmi_base_addr,
 433                                        cp110_utmi_data[i].usb_cfg_addr,
 434                                        cp110_utmi_data[i].utmi_cfg_addr,
 435                                        cp110_utmi_data[i].utmi_phy_port);
 436         }
 437         /* UTMI Power up */
 438         for (i = 0; i < utmi_phy_count; i++) {
 439                 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
 440                                           cp110_utmi_data[i].utmi_base_addr,
 441                                           cp110_utmi_data[i].usb_cfg_addr,
 442                                           cp110_utmi_data[i].utmi_cfg_addr,
 443                                           cp110_utmi_data[i].utmi_phy_port)) {
 444                         pr_err("Failed to initialize UTMI PHY %d\n", i);
 445                         continue;
 446                 }
 447                 printf("UTMI PHY %d initialized to ", i);
 448                 if (cp110_utmi_data[i].utmi_phy_port ==
 449                     UTMI_PHY_TO_USB3_DEVICE0)
 450                         printf("USB Device\n");
 451                 else
 452                         printf("USB Host%d\n",
 453                                cp110_utmi_data[i].utmi_phy_port);
 454         }
 455         /* PLL Power up */
 456         debug("stage: UTMI PHY power up PLL\n");
 457         for (i = 0; i < utmi_phy_count; i++) {
 458                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 459                         0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 460         }
 461
 462         debug_exit();
 463         return;
 464 }
 465
 466 /*
 467  * comphy_dedicated_phys_init initialize the dedicated PHYs
 468  * - not muxed SerDes lanes e.g. UTMI PHY
 469  */
 470 void comphy_dedicated_phys_init(void)
 471 {
 472         struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
 473         int node = -1;
 474         int node_idx;
 475         int parent = -1;
 476
 477         debug_enter();
 478         debug("Initialize USB UTMI PHYs\n");
 479
 480         for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
 481                 /* Find the UTMI phy node in device tree */
 482                 node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
 483                                                      "marvell,mvebu-utmi-2.6.0");
 484                 if (node <= 0)
 485                         break;
 486
 487                 /* check if node is enabled */
 488                 if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
 489                         continue;
 490
 491                 parent = fdt_parent_offset(gd->fdt_blob, node);
 492                 if (parent <= 0)
 493                         break;
 494
 495                 /* get base address of UTMI PLL */
 496                 cp110_utmi_data[node_idx].utmi_pll_addr =
 497                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 498                                 gd->fdt_blob, parent, "reg", 0, NULL, true);
 499                 if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
 500                         pr_err("UTMI PHY PLL address is invalid\n");
 501                         continue;
 502                 }
 503
 504                 /* get base address of UTMI phy */
 505                 cp110_utmi_data[node_idx].utmi_base_addr =
 506                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 507                                 gd->fdt_blob, node, "reg", 0, NULL, true);
 508                 if (!cp110_utmi_data[node_idx].utmi_base_addr) {
 509                         pr_err("UTMI PHY base address is invalid\n");
 510                         continue;
 511                 }
 512
 513                 /* get usb config address */
 514                 cp110_utmi_data[node_idx].usb_cfg_addr =
 515                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 516                                 gd->fdt_blob, node, "reg", 1, NULL, true);
 517                 if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
 518                         pr_err("UTMI PHY base address is invalid\n");
 519                         continue;
 520                 }
 521
 522                 /* get UTMI config address */
 523                 cp110_utmi_data[node_idx].utmi_cfg_addr =
 524                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 525                                 gd->fdt_blob, node, "reg", 2, NULL, true);
 526                 if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
 527                         pr_err("UTMI PHY base address is invalid\n");
 528                         continue;
 529                 }
 530
 531                 /*
 532                  * get the port number (to check if the utmi connected to
 533                  * host/device)
 534                  */
 535                 cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
 536                         gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
 537                 if (cp110_utmi_data[node_idx].utmi_phy_port ==
 538                                                         UTMI_PHY_INVALID) {
 539                         pr_err("UTMI PHY port type is invalid\n");
 540                         continue;
 541                 }
 542
 543                 /* count valid UTMI unit */
 544                 node_idx++;
 545         }
 546
 547         if (node_idx > 0)
 548                 comphy_utmi_phy_init(node_idx, cp110_utmi_data);
 549
 550         debug_exit();
 551 }
 552
 553 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 554                       struct comphy_map *serdes_map)
 555 {
 556         struct comphy_map *ptr_comphy_map;
 557         void __iomem *comphy_base_addr, *hpipe_base_addr;
 558         u32 comphy_max_count, lane, id, ret = 0;
 559         u32 pcie_width = 0;
 560         u32 mode;
 561
 562         debug_enter();
 563
 564         comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
 565         comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
 566         hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
 567
 568         /* Check if the first 4 lanes configured as By-4 */
 569         for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
 570              lane++, ptr_comphy_map++) {
 571                 if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
 572                         break;
 573                 pcie_width++;
 574         }
 575
 576         for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
 577              lane++, ptr_comphy_map++) {
 578                 debug("Initialize serdes number %d\n", lane);
 579                 debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
 580                 if (lane == 4) {
 581                         /*
 582                          * PCIe lanes above the first 4 lanes, can be only
 583                          * by1
 584                          */
 585                         pcie_width = 1;
 586                 }
 587                 switch (ptr_comphy_map->type) {
 588                 case COMPHY_TYPE_UNCONNECTED:
 589                         mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
 590                         ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
 591                                          ptr_chip_cfg->comphy_base_addr,
 592                                          lane, mode);
 593                 case COMPHY_TYPE_IGNORE:
 594                         continue;
 595                         break;
 596                 case COMPHY_TYPE_PEX0:
 597                 case COMPHY_TYPE_PEX1:
 598                 case COMPHY_TYPE_PEX2:
 599                 case COMPHY_TYPE_PEX3:
 600                         mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
 601                                                      ptr_comphy_map->clk_src,
 602                                                      COMPHY_PCIE_MODE,
 603                                                      ptr_comphy_map->speed);
 604                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 605                                          ptr_chip_cfg->comphy_base_addr, lane,
 606                                          mode);
 607                         break;
 608                 case COMPHY_TYPE_SATA0:
 609                 case COMPHY_TYPE_SATA1:
 610                         mode =  COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
 611                         ret = comphy_sata_power_up(lane, hpipe_base_addr,
 612                                                    comphy_base_addr,
 613                                                    ptr_chip_cfg->cp_index,
 614                                                    mode);
 615                         break;
 616                 case COMPHY_TYPE_USB3_HOST0:
 617                 case COMPHY_TYPE_USB3_HOST1:
 618                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
 619                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 620                                          ptr_chip_cfg->comphy_base_addr, lane,
 621                                          mode);
 622                         break;
 623                 case COMPHY_TYPE_USB3_DEVICE:
 624                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
 625                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 626                                          ptr_chip_cfg->comphy_base_addr, lane,
 627                                          mode);
 628                         break;
 629                 case COMPHY_TYPE_SGMII0:
 630                 case COMPHY_TYPE_SGMII1:
 631                 case COMPHY_TYPE_SGMII2:
 632                         /* Calculate SGMII ID */
 633                         id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
 634
 635                         if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
 636                                 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
 637                                       lane);
 638                                 ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
 639                         }
 640
 641                         mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
 642                                                 ptr_comphy_map->speed);
 643                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 644                                          ptr_chip_cfg->comphy_base_addr, lane,
 645                                          mode);
 646                         break;
 647                 case COMPHY_TYPE_SFI0:
 648                 case COMPHY_TYPE_SFI1:
 649                         /* Calculate SFI id */
 650                         id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
 651                         mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
 652                                                 ptr_comphy_map->speed);
 653                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 654                                 ptr_chip_cfg->comphy_base_addr, lane, mode);
 655                         break;
 656                 case COMPHY_TYPE_RXAUI0:
 657                 case COMPHY_TYPE_RXAUI1:
 658                         mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
 659                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 660                                          ptr_chip_cfg->comphy_base_addr, lane,
 661                                          mode);
 662                         break;
 663                 default:
 664                         debug("Unknown SerDes type, skip initialize SerDes %d\n",
 665                               lane);
 666                         break;
 667                 }
 668                 if (ret == 0) {
 669                         /*
 670                          * If interface wans't initialized, set the lane to
 671                          * COMPHY_TYPE_UNCONNECTED state.
 672                          */
 673                         ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
 674                         pr_err("PLL is not locked - Failed to initialize lane %d\n",
 675                               lane);
 676                 }
 677         }
 678
 679         debug_exit();
 680         return 0;
 681 }