drivers/phy/marvell/comphy_cp110.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015-2016 Marvell International Ltd.
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <log.h>
   9 #include <asm/global_data.h>
  10 #include <asm/io.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/soc.h>
  14 #include <linux/delay.h>
  15
  16 #include "comphy_core.h"
  17 #include "comphy_hpipe.h"
  18 #include "sata.h"
  19 #include "utmi_phy.h"
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define SD_ADDR(base, lane)                     (base + 0x1000 * lane)
  24 #define HPIPE_ADDR(base, lane)                  (SD_ADDR(base, lane) + 0x800)
  25 #define COMPHY_ADDR(base, lane)                 (base + 0x28 * lane)
  26
  27 /* Firmware related definitions used for SMC calls */
  28 #define MV_SIP_COMPHY_POWER_ON  0x82000001
  29 #define MV_SIP_COMPHY_POWER_OFF 0x82000002
  30 #define MV_SIP_COMPHY_PLL_LOCK  0x82000003
  31
  32 /* Used to distinguish between different possible callers (U-boot/Linux) */
  33 #define COMPHY_CALLER_UBOOT                     (0x1 << 21)
  34
  35 #define COMPHY_FW_MODE_FORMAT(mode)             ((mode) << 12)
  36 #define COMPHY_FW_FORMAT(mode, idx, speeds)     \
  37                         (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
  38
  39 #define COMPHY_FW_PCIE_FORMAT(pcie_width, clk_src, mode, speeds)        \
  40                         (COMPHY_CALLER_UBOOT | ((pcie_width) << 18) |   \
  41                         ((clk_src) << 17) | COMPHY_FW_FORMAT(mode, 0, speeds))
  42
  43 #define COMPHY_SATA_MODE        0x1
  44 #define COMPHY_SGMII_MODE       0x2     /* SGMII 1G */
  45 #define COMPHY_HS_SGMII_MODE    0x3     /* SGMII 2.5G */
  46 #define COMPHY_USB3H_MODE       0x4
  47 #define COMPHY_USB3D_MODE       0x5
  48 #define COMPHY_PCIE_MODE        0x6
  49 #define COMPHY_RXAUI_MODE       0x7
  50 #define COMPHY_XFI_MODE         0x8
  51 #define COMPHY_SFI_MODE         0x9
  52 #define COMPHY_USB3_MODE        0xa
  53 #define COMPHY_AP_MODE          0xb
  54
  55 /* Comphy unit index macro */
  56 #define COMPHY_UNIT_ID0         0
  57 #define COMPHY_UNIT_ID1         1
  58 #define COMPHY_UNIT_ID2         2
  59 #define COMPHY_UNIT_ID3         3
  60
  61 struct utmi_phy_data {
  62         void __iomem *utmi_base_addr;
  63         void __iomem *usb_cfg_addr;
  64         void __iomem *utmi_cfg_addr;
  65         u32 utmi_phy_port;
  66 };
  67
  68 /*
  69  * For CP-110 we have 2 Selector registers "PHY Selectors",
  70  * and "PIPE Selectors".
  71  * PIPE selector include USB and PCIe options.
  72  * PHY selector include the Ethernet and SATA options, every Ethernet
  73  * option has different options, for example: serdes lane2 had option
  74  * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
  75  */
  76 struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
  77         {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
  78              {PHY_TYPE_SATA1, 0x4} } },
  79         {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
  80              {PHY_TYPE_SATA0, 0x4} } },
  81         {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
  82              {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
  83              {PHY_TYPE_SATA0, 0x4} } },
  84         {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
  85              {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
  86         {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
  87              {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
  88              {PHY_TYPE_SGMII1, 0x1} } },
  89         {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
  90              {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
  91 };
  92
  93 struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
  94         {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
  95         {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
  96              {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
  97              {PHY_TYPE_PEX0, 0x4} } },
  98         {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
  99              {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
 100         {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
 101              {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
 102         {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
 103              {PHY_TYPE_USB3_HOST1, 0x1},
 104              {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
 105         {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
 106 };
 107
 108 static u32 polling_with_timeout(void __iomem *addr, u32 val,
 109                                 u32 mask, unsigned long usec_timout)
 110 {
 111         u32 data;
 112
 113         do {
 114                 udelay(1);
 115                 data = readl(addr) & mask;
 116         } while (data != val  && --usec_timout > 0);
 117
 118         if (usec_timout == 0)
 119                 return data;
 120
 121         return 0;
 122 }
 123
 124 static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
 125                                 void __iomem *comphy_base)
 126 {
 127         u32 mask, data, ret = 1;
 128         void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
 129         void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
 130         void __iomem *addr;
 131
 132         debug_enter();
 133         debug("stage: RFU configurations - hard reset comphy\n");
 134         /* RFU configurations - hard reset comphy */
 135         mask = COMMON_PHY_CFG1_PWR_UP_MASK;
 136         data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
 137         mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
 138         data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
 139         mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
 140         data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
 141         mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
 142         data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
 143         mask |= COMMON_PHY_PHY_MODE_MASK;
 144         data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
 145         reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
 146
 147         /* release from hard reset */
 148         mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
 149         data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
 150         mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
 151         data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
 152         reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
 153
 154         /* Wait 1ms - until band gap and ref clock ready */
 155         mdelay(1);
 156
 157         /* Start comphy Configuration */
 158         debug("stage: Comphy configuration\n");
 159         /* Set PIPE soft reset */
 160         mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
 161         data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
 162         /* Set PHY datapath width mode for V0 */
 163         mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
 164         data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
 165         /* Set Data bus width USB mode for V0 */
 166         mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
 167         data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
 168         /* Set CORE_CLK output frequency for 250Mhz */
 169         mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
 170         data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
 171         reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
 172         /* Set PLL ready delay for 0x2 */
 173         reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
 174                 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
 175                 HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
 176         /* Set reference clock to come from group 1 - 25Mhz */
 177         reg_set(hpipe_addr + HPIPE_MISC_REG,
 178                 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
 179                 HPIPE_MISC_REFCLK_SEL_MASK);
 180         /* Set reference frequcency select - 0x2 */
 181         mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
 182         data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
 183         /* Set PHY mode to USB - 0x5 */
 184         mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
 185         data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
 186         reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
 187         /* Set the amount of time spent in the LoZ state - set for 0x7 */
 188         reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
 189                 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
 190                 HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
 191         /* Set max PHY generation setting - 5Gbps */
 192         reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
 193                 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
 194                 HPIPE_INTERFACE_GEN_MAX_MASK);
 195         /* Set select data width 20Bit (SEL_BITS[2:0]) */
 196         reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
 197                 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
 198                 HPIPE_LOOPBACK_SEL_MASK);
 199         /* select de-emphasize 3.5db */
 200         reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
 201                 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
 202                 HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
 203         /* override tx margining from the MAC */
 204         reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
 205                 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
 206                 HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
 207
 208         /* Start analog paramters from ETP(HW) */
 209         debug("stage: Analog paramters from ETP(HW)\n");
 210         /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
 211         mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
 212         data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
 213         /* Set Override PHY DFE control pins for 0x1 */
 214         mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
 215         data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
 216         /* Set Spread Spectrum Clock Enable fot 0x1 */
 217         mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
 218         data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
 219         reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
 220         /* End of analog parameters */
 221
 222         debug("stage: Comphy power up\n");
 223         /* Release from PIPE soft reset */
 224         reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
 225                 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
 226                 HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
 227
 228         /* wait 15ms - for comphy calibration done */
 229         debug("stage: Check PLL\n");
 230         /* Read lane status */
 231         addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
 232         data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
 233         mask = data;
 234         data = polling_with_timeout(addr, data, mask, 15000);
 235         if (data != 0) {
 236                 debug("Read from reg = %p - value = 0x%x\n",
 237                       hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
 238                 pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
 239                 ret = 0;
 240         }
 241
 242         debug_exit();
 243         return ret;
 244 }
 245
 246 static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
 247                       u32 lane, u32 mode)
 248 {
 249         struct pt_regs pregs = {0};
 250
 251         pregs.regs[0] = function_id;
 252         pregs.regs[1] = (unsigned long)comphy_base_addr;
 253         pregs.regs[2] = lane;
 254         pregs.regs[3] = mode;
 255
 256         smc_call(&pregs);
 257
 258         /*
 259          * TODO: Firmware return 0 on success, temporary map it to u-boot
 260          * convention, but after all comphy will be reworked the convention in
 261          * u-boot should be change and this conversion removed
 262          */
 263         return pregs.regs[0] ? 0 : 1;
 264 }
 265
 266 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
 267                                 void __iomem *comphy_base_addr, int cp_index,
 268                                 u32 type)
 269 {
 270         u32 mask, data, i, ret = 1;
 271         void __iomem *sata_base = NULL;
 272         int sata_node = -1; /* Set to -1 in order to read the first sata node */
 273
 274         debug_enter();
 275
 276         /*
 277          * Assumption - each CP has only one SATA controller
 278          * Calling fdt_node_offset_by_compatible first time (with sata_node = -1
 279          * will return the first node always.
 280          * In order to parse each CPs SATA node, fdt_node_offset_by_compatible
 281          * must be called again (according to the CP id)
 282          */
 283         for (i = 0; i < (cp_index + 1); i++)
 284                 sata_node = fdt_node_offset_by_compatible(
 285                         gd->fdt_blob, sata_node, "marvell,armada-8k-ahci");
 286
 287         if (sata_node == 0) {
 288                 pr_err("SATA node not found in FDT\n");
 289                 return 0;
 290         }
 291
 292         sata_base = (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 293                 gd->fdt_blob, sata_node, "reg", 0, NULL, true);
 294         if (sata_base == NULL) {
 295                 pr_err("SATA address not found in FDT\n");
 296                 return 0;
 297         }
 298
 299         debug("SATA address found in FDT %p\n", sata_base);
 300
 301         debug("stage: MAC configuration - power down comphy\n");
 302         /*
 303          * MAC configuration powe down comphy use indirect address for
 304          * vendor spesific SATA control register
 305          */
 306         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 307                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 308                 SATA3_VENDOR_ADDR_MASK);
 309         /* SATA 0 power down */
 310         mask = SATA3_CTRL_SATA0_PD_MASK;
 311         data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET;
 312         /* SATA 1 power down */
 313         mask |= SATA3_CTRL_SATA1_PD_MASK;
 314         data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET;
 315         /* SATA SSU disable */
 316         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 317         data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 318         /* SATA port 1 disable */
 319         mask |= SATA3_CTRL_SATA_SSU_MASK;
 320         data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
 321         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 322
 323         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, comphy_base_addr, lane, type);
 324
 325         /*
 326          * MAC configuration power up comphy - power up PLL/TX/RX
 327          * use indirect address for vendor spesific SATA control register
 328          */
 329         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 330                 SATA_CONTROL_REG << SATA3_VENDOR_ADDR_OFSSET,
 331                 SATA3_VENDOR_ADDR_MASK);
 332         /* SATA 0 power up */
 333         mask = SATA3_CTRL_SATA0_PD_MASK;
 334         data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET;
 335         /* SATA 1 power up */
 336         mask |= SATA3_CTRL_SATA1_PD_MASK;
 337         data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET;
 338         /* SATA SSU enable */
 339         mask |= SATA3_CTRL_SATA1_ENABLE_MASK;
 340         data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET;
 341         /* SATA port 1 enable */
 342         mask |= SATA3_CTRL_SATA_SSU_MASK;
 343         data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET;
 344         reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 345
 346         /* MBUS request size and interface select register */
 347         reg_set(sata_base + SATA3_VENDOR_ADDRESS,
 348                 SATA_MBUS_SIZE_SELECT_REG << SATA3_VENDOR_ADDR_OFSSET,
 349                 SATA3_VENDOR_ADDR_MASK);
 350         /* Mbus regret enable */
 351         reg_set(sata_base + SATA3_VENDOR_DATA,
 352                 0x1 << SATA_MBUS_REGRET_EN_OFFSET, SATA_MBUS_REGRET_EN_MASK);
 353
 354         ret = comphy_smc(MV_SIP_COMPHY_PLL_LOCK, comphy_base_addr, lane, type);
 355
 356         debug_exit();
 357         return ret;
 358 }
 359
 360 static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
 361                                   void __iomem *comphy_base)
 362 {
 363         u32 mask, data, ret = 1;
 364         void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
 365         void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
 366         void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
 367         void __iomem *addr;
 368
 369         debug_enter();
 370         debug("stage: RFU configurations - hard reset comphy\n");
 371         /* RFU configurations - hard reset comphy */
 372         mask = COMMON_PHY_CFG1_PWR_UP_MASK;
 373         data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
 374         mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
 375         data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
 376         reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
 377
 378         if (lane == 2) {
 379                 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
 380                         0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
 381                         COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
 382         }
 383         if (lane == 4) {
 384                 reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
 385                         0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
 386                         COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
 387         }
 388
 389         /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
 390         mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
 391         data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
 392         mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
 393         data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
 394         mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
 395         data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
 396         mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
 397         data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
 398         mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
 399         data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
 400         mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
 401         data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
 402         mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
 403         data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
 404         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
 405
 406         /* release from hard reset */
 407         mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
 408         data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
 409         mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
 410         data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
 411         mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
 412         data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
 413         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
 414
 415         mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
 416         data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
 417         mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
 418         data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
 419         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
 420
 421         /* Wait 1ms - until band gap and ref clock ready */
 422         mdelay(1);
 423
 424         /* Start comphy Configuration */
 425         debug("stage: Comphy configuration\n");
 426         /* set reference clock */
 427         reg_set(hpipe_addr + HPIPE_MISC_REG,
 428                 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
 429                 HPIPE_MISC_REFCLK_SEL_MASK);
 430         /* Power and PLL Control */
 431         mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
 432         data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
 433         mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
 434         data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
 435         reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
 436         /* Loopback register */
 437         reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
 438                 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
 439         /* rx control 1 */
 440         mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
 441         data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
 442         mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
 443         data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
 444         reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
 445         /* DTL Control */
 446         reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
 447                 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
 448                 HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
 449
 450         /* Set analog paramters from ETP(HW) */
 451         debug("stage: Analog paramters from ETP(HW)\n");
 452         /* SERDES External Configuration 2 */
 453         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
 454                 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
 455                 SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
 456         /* 0x7-DFE Resolution control */
 457         reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
 458                 HPIPE_DFE_RES_FORCE_MASK);
 459         /* 0xd-G1_Setting_0 */
 460         reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
 461                 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
 462                 HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
 463         /* 0xE-G1_Setting_1 */
 464         mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
 465         data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
 466         mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
 467         data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
 468         mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
 469         data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
 470         reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
 471         /* 0xA-DFE_Reg3 */
 472         mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
 473         data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
 474         mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
 475         data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
 476         reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
 477
 478         /* 0x111-G1_Setting_4 */
 479         mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
 480         data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
 481         reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
 482
 483         debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
 484         /* SERDES External Configuration */
 485         mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
 486         data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
 487         mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
 488         data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
 489         mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
 490         data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
 491         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
 492
 493
 494         /* check PLL rx & tx ready */
 495         addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
 496         data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
 497                 SD_EXTERNAL_STATUS0_PLL_TX_MASK;
 498         mask = data;
 499         data = polling_with_timeout(addr, data, mask, 15000);
 500         if (data != 0) {
 501                 debug("Read from reg = %p - value = 0x%x\n",
 502                       sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
 503                 pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
 504                       (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
 505                       (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
 506                 ret = 0;
 507         }
 508
 509         /* RX init */
 510         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
 511                 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
 512                 SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
 513
 514         /* check that RX init done */
 515         addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
 516         data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
 517         mask = data;
 518         data = polling_with_timeout(addr, data, mask, 100);
 519         if (data != 0) {
 520                 debug("Read from reg = %p - value = 0x%x\n",
 521                       sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
 522                 pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
 523                 ret = 0;
 524         }
 525
 526         debug("stage: RF Reset\n");
 527         /* RF Reset */
 528         mask =  SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
 529         data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
 530         mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
 531         data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
 532         reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
 533
 534         debug_exit();
 535         return ret;
 536 }
 537
 538 static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
 539                                    void __iomem *usb_cfg_addr,
 540                                    void __iomem *utmi_cfg_addr,
 541                                    u32 utmi_phy_port)
 542 {
 543         u32 mask, data;
 544
 545         debug_enter();
 546         debug("stage:  UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n",
 547               utmi_index);
 548         /* Power down UTMI PHY */
 549         reg_set(utmi_cfg_addr, 0x0 << UTMI_PHY_CFG_PU_OFFSET,
 550                 UTMI_PHY_CFG_PU_MASK);
 551
 552         /*
 553          * If UTMI connected to USB Device, configure mux prior to PHY init
 554          * (Device can be connected to UTMI0 or to UTMI1)
 555          */
 556         if (utmi_phy_port == UTMI_PHY_TO_USB3_DEVICE0) {
 557                 debug("stage:  UTMI %d - Enable Device mode and configure UTMI mux\n",
 558                       utmi_index);
 559                 /* USB3 Device UTMI enable */
 560                 mask = UTMI_USB_CFG_DEVICE_EN_MASK;
 561                 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET;
 562                 /* USB3 Device UTMI MUX */
 563                 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK;
 564                 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET;
 565                 reg_set(usb_cfg_addr,  data, mask);
 566         }
 567
 568         /* Set Test suspendm mode */
 569         mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK;
 570         data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET;
 571         /* Enable Test UTMI select */
 572         mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK;
 573         data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET;
 574         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask);
 575
 576         /* Wait for UTMI power down */
 577         mdelay(1);
 578
 579         debug_exit();
 580         return;
 581 }
 582
 583 static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
 584                                    void __iomem *usb_cfg_addr,
 585                                    void __iomem *utmi_cfg_addr,
 586                                    u32 utmi_phy_port)
 587 {
 588         u32 mask, data;
 589
 590         debug_exit();
 591         debug("stage: Configure UTMI PHY %d registers\n", utmi_index);
 592         /* Reference Clock Divider Select */
 593         mask = UTMI_PLL_CTRL_REFDIV_MASK;
 594         data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET;
 595         /* Feedback Clock Divider Select - 90 for 25Mhz*/
 596         mask |= UTMI_PLL_CTRL_FBDIV_MASK;
 597         data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET;
 598         /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
 599         mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
 600         data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
 601         reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
 602
 603         /* Impedance Calibration Threshold Setting */
 604         reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
 605                 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
 606                 UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
 607
 608         /* Set LS TX driver strength coarse control */
 609         mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
 610         data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
 611         /* Set LS TX driver fine adjustment */
 612         mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
 613         data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
 614         reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
 615
 616         /* Enable SQ */
 617         mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
 618         data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
 619         /* Enable analog squelch detect */
 620         mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
 621         data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
 622         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
 623
 624         /* Set External squelch calibration number */
 625         mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK;
 626         data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET;
 627         /* Enable the External squelch calibration */
 628         mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK;
 629         data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET;
 630         reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask);
 631
 632         /* Set Control VDAT Reference Voltage - 0.325V */
 633         mask = UTMI_CHGDTC_CTRL_VDAT_MASK;
 634         data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET;
 635         /* Set Control VSRC Reference Voltage - 0.6V */
 636         mask |= UTMI_CHGDTC_CTRL_VSRC_MASK;
 637         data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET;
 638         reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask);
 639
 640         debug_exit();
 641         return;
 642 }
 643
 644 static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
 645                                 void __iomem *usb_cfg_addr,
 646                                 void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
 647 {
 648         u32 data, mask, ret = 1;
 649         void __iomem *addr;
 650
 651         debug_enter();
 652         debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n",
 653               utmi_index);
 654         /* Power UP UTMI PHY */
 655         reg_set(utmi_cfg_addr, 0x1 << UTMI_PHY_CFG_PU_OFFSET,
 656                 UTMI_PHY_CFG_PU_MASK);
 657         /* Disable Test UTMI select */
 658         reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG,
 659                 0x0 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET,
 660                 UTMI_CTRL_STATUS0_TEST_SEL_MASK);
 661
 662         debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
 663         addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
 664         data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
 665         mask = data;
 666         data = polling_with_timeout(addr, data, mask, 100);
 667         if (data != 0) {
 668                 pr_err("Impedance calibration is not done\n");
 669                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 670                 ret = 0;
 671         }
 672
 673         data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK;
 674         mask = data;
 675         data = polling_with_timeout(addr, data, mask, 100);
 676         if (data != 0) {
 677                 pr_err("PLL calibration is not done\n");
 678                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 679                 ret = 0;
 680         }
 681
 682         addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
 683         data = UTMI_PLL_CTRL_PLL_RDY_MASK;
 684         mask = data;
 685         data = polling_with_timeout(addr, data, mask, 100);
 686         if (data != 0) {
 687                 pr_err("PLL is not ready\n");
 688                 debug("Read from reg = %p - value = 0x%x\n", addr, data);
 689                 ret = 0;
 690         }
 691
 692         if (ret)
 693                 debug("Passed\n");
 694         else
 695                 debug("\n");
 696
 697         debug_exit();
 698         return ret;
 699 }
 700
 701 /*
 702  * comphy_utmi_phy_init initialize the UTMI PHY
 703  * the init split in 3 parts:
 704  * 1. Power down transceiver and PLL
 705  * 2. UTMI PHY configure
 706  * 3. Powe up transceiver and PLL
 707  * Note: - Power down/up should be once for both UTMI PHYs
 708  *       - comphy_dedicated_phys_init call this function if at least there is
 709  *         one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
 710  *         legal
 711  */
 712 static void comphy_utmi_phy_init(u32 utmi_phy_count,
 713                                  struct utmi_phy_data *cp110_utmi_data)
 714 {
 715         u32 i;
 716
 717         debug_enter();
 718         /* UTMI Power down */
 719         for (i = 0; i < utmi_phy_count; i++) {
 720                 comphy_utmi_power_down(i, cp110_utmi_data[i].utmi_base_addr,
 721                                        cp110_utmi_data[i].usb_cfg_addr,
 722                                        cp110_utmi_data[i].utmi_cfg_addr,
 723                                        cp110_utmi_data[i].utmi_phy_port);
 724         }
 725         /* PLL Power down */
 726         debug("stage: UTMI PHY power down PLL\n");
 727         for (i = 0; i < utmi_phy_count; i++) {
 728                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 729                         0x0 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 730         }
 731         /* UTMI configure */
 732         for (i = 0; i < utmi_phy_count; i++) {
 733                 comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
 734                                        cp110_utmi_data[i].usb_cfg_addr,
 735                                        cp110_utmi_data[i].utmi_cfg_addr,
 736                                        cp110_utmi_data[i].utmi_phy_port);
 737         }
 738         /* UTMI Power up */
 739         for (i = 0; i < utmi_phy_count; i++) {
 740                 if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
 741                                           cp110_utmi_data[i].usb_cfg_addr,
 742                                           cp110_utmi_data[i].utmi_cfg_addr,
 743                                           cp110_utmi_data[i].utmi_phy_port)) {
 744                         pr_err("Failed to initialize UTMI PHY %d\n", i);
 745                         continue;
 746                 }
 747                 printf("UTMI PHY %d initialized to ", i);
 748                 if (cp110_utmi_data[i].utmi_phy_port ==
 749                     UTMI_PHY_TO_USB3_DEVICE0)
 750                         printf("USB Device\n");
 751                 else
 752                         printf("USB Host%d\n",
 753                                cp110_utmi_data[i].utmi_phy_port);
 754         }
 755         /* PLL Power up */
 756         debug("stage: UTMI PHY power up PLL\n");
 757         for (i = 0; i < utmi_phy_count; i++) {
 758                 reg_set(cp110_utmi_data[i].usb_cfg_addr,
 759                         0x1 << UTMI_USB_CFG_PLL_OFFSET, UTMI_USB_CFG_PLL_MASK);
 760         }
 761
 762         debug_exit();
 763         return;
 764 }
 765
 766 /*
 767  * comphy_dedicated_phys_init initialize the dedicated PHYs
 768  * - not muxed SerDes lanes e.g. UTMI PHY
 769  */
 770 void comphy_dedicated_phys_init(void)
 771 {
 772         struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
 773         int node;
 774         int i;
 775
 776         debug_enter();
 777         debug("Initialize USB UTMI PHYs\n");
 778
 779         /* Find the UTMI phy node in device tree and go over them */
 780         node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
 781                                              "marvell,mvebu-utmi-2.6.0");
 782
 783         i = 0;
 784         while (node > 0) {
 785                 /* get base address of UTMI phy */
 786                 cp110_utmi_data[i].utmi_base_addr =
 787                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 788                                 gd->fdt_blob, node, "reg", 0, NULL, true);
 789                 if (cp110_utmi_data[i].utmi_base_addr == NULL) {
 790                         pr_err("UTMI PHY base address is invalid\n");
 791                         i++;
 792                         continue;
 793                 }
 794
 795                 /* get usb config address */
 796                 cp110_utmi_data[i].usb_cfg_addr =
 797                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 798                                 gd->fdt_blob, node, "reg", 1, NULL, true);
 799                 if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
 800                         pr_err("UTMI PHY base address is invalid\n");
 801                         i++;
 802                         continue;
 803                 }
 804
 805                 /* get UTMI config address */
 806                 cp110_utmi_data[i].utmi_cfg_addr =
 807                         (void __iomem *)fdtdec_get_addr_size_auto_noparent(
 808                                 gd->fdt_blob, node, "reg", 2, NULL, true);
 809                 if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
 810                         pr_err("UTMI PHY base address is invalid\n");
 811                         i++;
 812                         continue;
 813                 }
 814
 815                 /*
 816                  * get the port number (to check if the utmi connected to
 817                  * host/device)
 818                  */
 819                 cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
 820                         gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
 821                 if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
 822                         pr_err("UTMI PHY port type is invalid\n");
 823                         i++;
 824                         continue;
 825                 }
 826
 827                 node = fdt_node_offset_by_compatible(
 828                         gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
 829                 i++;
 830         }
 831
 832         if (i > 0)
 833                 comphy_utmi_phy_init(i, cp110_utmi_data);
 834
 835         debug_exit();
 836 }
 837
 838 static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 839                                   struct comphy_map *serdes_map)
 840 {
 841         void __iomem *comphy_base_addr;
 842         struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
 843         struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
 844         u32 lane, comphy_max_count;
 845
 846         comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
 847         comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
 848
 849         /*
 850          * Copy the SerDes map configuration for PIPE map and PHY map
 851          * the comphy_mux_init modify the type of the lane if the type
 852          * is not valid because we have 2 selectores run the
 853          * comphy_mux_init twice and after that update the original
 854          * serdes_map
 855          */
 856         for (lane = 0; lane < comphy_max_count; lane++) {
 857                 comphy_map_pipe_data[lane].type = serdes_map[lane].type;
 858                 comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
 859                 comphy_map_phy_data[lane].type = serdes_map[lane].type;
 860                 comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
 861         }
 862         ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
 863         comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
 864                         comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
 865
 866         ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
 867         comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
 868                         comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
 869         /* Fix the type after check the PHY and PIPE configuration */
 870         for (lane = 0; lane < comphy_max_count; lane++) {
 871                 if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
 872                     (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
 873                         serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
 874         }
 875 }
 876
 877 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
 878                       struct comphy_map *serdes_map)
 879 {
 880         struct comphy_map *ptr_comphy_map;
 881         void __iomem *comphy_base_addr, *hpipe_base_addr;
 882         u32 comphy_max_count, lane, ret = 0;
 883         u32 pcie_width = 0;
 884         u32 mode;
 885
 886         debug_enter();
 887
 888         comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
 889         comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
 890         hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
 891
 892         /* Config Comphy mux configuration */
 893         comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
 894
 895         /* Check if the first 4 lanes configured as By-4 */
 896         for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
 897              lane++, ptr_comphy_map++) {
 898                 if (ptr_comphy_map->type != PHY_TYPE_PEX0)
 899                         break;
 900                 pcie_width++;
 901         }
 902
 903         for (lane = 0, ptr_comphy_map = serdes_map; lane < comphy_max_count;
 904              lane++, ptr_comphy_map++) {
 905                 debug("Initialize serdes number %d\n", lane);
 906                 debug("Serdes type = 0x%x\n", ptr_comphy_map->type);
 907                 if (lane == 4) {
 908                         /*
 909                          * PCIe lanes above the first 4 lanes, can be only
 910                          * by1
 911                          */
 912                         pcie_width = 1;
 913                 }
 914                 switch (ptr_comphy_map->type) {
 915                 case PHY_TYPE_UNCONNECTED:
 916                 case PHY_TYPE_IGNORE:
 917                         continue;
 918                         break;
 919                 case PHY_TYPE_PEX0:
 920                 case PHY_TYPE_PEX1:
 921                 case PHY_TYPE_PEX2:
 922                 case PHY_TYPE_PEX3:
 923                         mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
 924                                                      ptr_comphy_map->clk_src,
 925                                                      COMPHY_PCIE_MODE,
 926                                                      ptr_comphy_map->speed);
 927                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 928                                          ptr_chip_cfg->comphy_base_addr, lane,
 929                                          mode);
 930                         break;
 931                 case PHY_TYPE_SATA0:
 932                 case PHY_TYPE_SATA1:
 933                 case PHY_TYPE_SATA2:
 934                 case PHY_TYPE_SATA3:
 935                         mode =  COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
 936                         ret = comphy_sata_power_up(lane, hpipe_base_addr,
 937                                                    comphy_base_addr,
 938                                                    ptr_chip_cfg->cp_index,
 939                                                    mode);
 940                         break;
 941                 case PHY_TYPE_USB3_HOST0:
 942                 case PHY_TYPE_USB3_HOST1:
 943                 case PHY_TYPE_USB3_DEVICE:
 944                         ret = comphy_usb3_power_up(lane, hpipe_base_addr,
 945                                                    comphy_base_addr);
 946                         break;
 947                 case PHY_TYPE_SGMII0:
 948                 case PHY_TYPE_SGMII1:
 949                         if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
 950                                 debug("Warning: ");
 951                                 debug("SGMII PHY speed in lane %d is invalid,",
 952                                       lane);
 953                                 debug(" set PHY speed to 1.25G\n");
 954                                 ptr_comphy_map->speed = PHY_SPEED_1_25G;
 955                         }
 956
 957                         /*
 958                          * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
 959                          * ignored by firmware
 960                          */
 961                         mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
 962                                                 COMPHY_UNIT_ID0,
 963                                                 ptr_comphy_map->speed);
 964                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 965                                          ptr_chip_cfg->comphy_base_addr, lane,
 966                                          mode);
 967                         break;
 968                 case PHY_TYPE_SGMII2:
 969                 case PHY_TYPE_SGMII3:
 970                         if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
 971                                 debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
 972                                       lane);
 973                                 ptr_comphy_map->speed = PHY_SPEED_1_25G;
 974                         }
 975
 976                         mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
 977                                                 COMPHY_UNIT_ID2,
 978                                                 ptr_comphy_map->speed);
 979                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 980                                          ptr_chip_cfg->comphy_base_addr, lane,
 981                                          mode);
 982                         break;
 983                 case PHY_TYPE_SFI:
 984                         mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
 985                                                 COMPHY_UNIT_ID0,
 986                                                 ptr_comphy_map->speed);
 987                         ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
 988                                          ptr_chip_cfg->comphy_base_addr, lane,
 989                                          mode);
 990                         break;
 991                 case PHY_TYPE_RXAUI0:
 992                 case PHY_TYPE_RXAUI1:
 993                         ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
 994                                                      comphy_base_addr);
 995                         break;
 996                 default:
 997                         debug("Unknown SerDes type, skip initialize SerDes %d\n",
 998                               lane);
 999                         break;
1000                 }
1001                 if (ret == 0) {
1002                         /*
1003                          * If interface wans't initialized, set the lane to
1004                          * PHY_TYPE_UNCONNECTED state.
1005                          */
1006                         ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
1007                         pr_err("PLL is not locked - Failed to initialize lane %d\n",
1008                               lane);
1009                 }
1010         }
1011
1012         debug_exit();
1013         return 0;
1014 }