1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Marvell International Ltd.
6 #ifndef _COMPHY_CORE_H_
7 #define _COMPHY_CORE_H_
10 #include <mvebu/comphy.h>
13 #define debug_enter() printf("----> Enter %s\n", __func__);
14 #define debug_exit() printf("<---- Exit %s\n", __func__);
20 /* COMPHY registers */
21 #define COMMON_PHY_CFG1_REG 0x0
22 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
23 #define COMMON_PHY_CFG1_PWR_UP_MASK \
24 (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
25 #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
26 #define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
27 (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
28 #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
29 #define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
30 (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
31 #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
32 #define COMMON_PHY_CFG1_CORE_RSTN_MASK \
33 (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
34 #define COMMON_PHY_PHY_MODE_OFFSET 15
35 #define COMMON_PHY_PHY_MODE_MASK \
36 (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
38 #define COMMON_PHY_CFG6_REG 0x14
39 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
40 #define COMMON_PHY_CFG6_IF_40_SEL_MASK \
41 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
43 #define COMMON_SELECTOR_PHY_OFFSET 0x140
44 #define COMMON_SELECTOR_PIPE_OFFSET 0x144
46 #define COMMON_PHY_SD_CTRL1 0x148
47 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
48 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
49 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
50 #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
51 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
52 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
53 #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
54 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
55 #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
56 #define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
57 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
58 #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
59 #define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
60 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
62 /* ToDo: Get this address via DT */
63 #define MVEBU_CP0_REGS_BASE 0xF2000000UL
65 #define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
66 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
67 #define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
68 (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
70 #define MAX_LANE_OPTIONS 10
71 #define MAX_UTMI_PHY_COUNT 3
73 struct comphy_mux_options {
78 struct comphy_mux_data {
80 struct comphy_mux_options mux_values[MAX_LANE_OPTIONS];
83 struct chip_serdes_phy_config {
84 struct comphy_mux_data *mux_data;
85 int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
87 void __iomem *comphy_base_addr;
88 void __iomem *hpipe3_base_addr;
89 u32 comphy_lanes_count;
90 u32 comphy_mux_bitcount;
91 const fdt32_t *comphy_mux_lane_order;
93 struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
96 /* Register helper functions */
97 static inline void reg_set_silent(void __iomem *addr, u32 data, u32 mask)
101 reg_data = readl(addr);
104 writel(reg_data, addr);
107 static inline void reg_set(void __iomem *addr, u32 data, u32 mask)
109 debug("Write to address = %#010lx, data = %#010x (mask = %#010x) - ",
110 (unsigned long)addr, data, mask);
111 debug("old value = %#010x ==> ", readl(addr));
112 reg_set_silent(addr, data, mask);
113 debug("new value %#010x\n", readl(addr));
116 static inline void reg_set_silent16(void __iomem *addr, u16 data, u16 mask)
120 reg_data = readw(addr);
123 writew(reg_data, addr);
126 static inline void reg_set16(void __iomem *addr, u16 data, u16 mask)
128 debug("Write to address = %#010lx, data = %#06x (mask = %#06x) - ",
129 (unsigned long)addr, data, mask);
130 debug("old value = %#06x ==> ", readw(addr));
131 reg_set_silent16(addr, data, mask);
132 debug("new value %#06x\n", readw(addr));
135 /* SoC specific init functions */
136 #ifdef CONFIG_ARMADA_3700
137 int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
138 struct comphy_map *serdes_map);
140 static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
141 struct comphy_map *serdes_map)
144 * This function should never be called in this configuration, so
145 * lets return an error here.
151 #ifdef CONFIG_ARMADA_8K
152 int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
153 struct comphy_map *serdes_map);
155 static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
156 struct comphy_map *serdes_map)
159 * This function should never be called in this configuration, so
160 * lets return an error here.
166 void comphy_dedicated_phys_init(void);
169 void comphy_mux_init(struct chip_serdes_phy_config *ptr_chip_cfg,
170 struct comphy_map *comphy_map_data,
171 void __iomem *selector_base);
173 void comphy_pcie_config_set(u32 comphy_max_count,
174 struct comphy_map *serdes_map);
175 void comphy_pcie_config_detect(u32 comphy_max_count,
176 struct comphy_map *serdes_map);
177 void comphy_pcie_unit_general_config(u32 pex_index);
179 #endif /* _COMPHY_CORE_H_ */