drivers/phy/m31/phy-m31-dphy-tx0.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Rockchip MIPI Synopsys DPHY RX0 driver
   4  *
   5  * Copyright (C) 2019 Collabora, Ltd.
   6  *
   7  * Based on:
   8  *
   9  * drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
  10  * in https://chromium.googlesource.com/chromiumos/third_party/kernel,
  11  * chromeos-4.4 branch.
  12  *
  13  * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
  14  *   Jacob Chen <jacob2.chen@rock-chips.com>
  15  *   Shunqian Zheng <zhengsq@rock-chips.com>
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/io.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/module.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/phy/phy.h>
  26 #include <linux/phy/phy-mipi-dphy.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/regmap.h>
  29 #include<linux/reset.h>
  30
  31 #include <linux/regulator/consumer.h>
  32 #include "7110-m31-dphy.h"
  33
  34 //syscfg registers
  35 #define SCFG_DSI_CSI_SEL                0x2c
  36 #define SCFG_PHY_RESETB             0x30
  37 #define SCFG_REFCLK_SEL             0x34
  38 #define SCFG_DBUS_PW_PLL_SSC_LD0        0x38
  39 #define SCFG_GRS_CDTX_PLL               0x3c
  40
  41 #define SCFG_RG_CDTX_PLL_FBK_PRE        0x44
  42 #define SCFG_RG_CLANE_DLANE_TIME        0x58
  43 #define SCFG_RG_CLANE_HS_TIME           0x58
  44
  45 #define SCFG_RG_EXTD_CYCLE_SEL          0x5c
  46
  47 #define SCFG_L0N_L0P_HSTX               0x60
  48 #define SCFG_L1N_L1P_HSTX               0x64
  49 #define SCFG_L2N_L2P_HSTX               0x68
  50 #define SCFG_L3N_L3P_HSTX               0x6c
  51 #define SCFG_L4N_L4P_HSTX               0x70
  52 #define SCFG_LX_SWAP_SEL                0x78
  53
  54 #define SCFG_HS_PRE_ZERO_T_D        0xc4
  55 #define SCFG_TXREADY_SRC_SEL_D      0xc8
  56 #define SCFG_HS_PRE_ZERO_T_C        0xd4
  57 #define SCFG_TXREADY_SRC_SEL_C      0xd8
  58
  59 //reg SCFG_LX_SWAP_SEL
  60 #define OFFSET_CFG_L0_SWAP_SEL  0
  61 #define OFFSET_CFG_L1_SWAP_SEL  3
  62 #define OFFSET_CFG_L2_SWAP_SEL  6
  63 #define OFFSET_CFG_L3_SWAP_SEL  9
  64 #define OFFSET_CFG_L4_SWAP_SEL  12
  65
  66 //reg SCFG_DBUS_PW_PLL_SSC_LD0
  67 #define OFFSET_SCFG_CFG_DATABUD16_SEL    0
  68 #define OFFSET_SCFG_PWRON_READY_N        1
  69 #define OFFSET_RG_CDTX_PLL_FM_EN         2
  70 #define OFFSET_SCFG_PLLSSC_EN            3
  71 #define OFFSET_RG_CDTX_PLL_LDO_STB_X2_EN 4
  72
  73 //reg SCFG_RG_CLANE_DLANE_TIME
  74 #define OFFSET_DHS_PRE_TIME          8
  75 #define OFFSET_DHS_TRIAL_TIME        16
  76 #define OFFSET_DHS_ZERO_TIME         24
  77
  78 //reg SCFG_RG_CLANE_HS_TIME
  79 #define OFFSET_CHS_PRE_TIME          8
  80 #define OFFSET_CHS_TRIAL_TIME        16
  81 #define OFFSET_CHS_ZERO_TIME         24
  82
  83 //dsitx registers
  84 #define  VID_MCTL_MAIN_DATA_CTL         0x04
  85 #define  VID_MCTL_MAIN_PHY_CTL          0x08
  86 #define  VID_MCTL_MAIN_EN                   0x0c
  87 #define  VID_MAIN_CTRL_ADDR    0xb0
  88 #define  VID_VSIZE1_ADDR       0xb4
  89 #define  VID_VSIZE2_ADDR       0xb8
  90 #define  VID_HSIZE1_ADDR       0xc0
  91 #define  VID_HSIZE2_ADDR       0xc4
  92 #define  VID_BLKSIZE1_ADDR     0xCC
  93 #define  VID_BLKSIZE2_ADDR     0xd0
  94 #define  VID_PCK_TIME_ADDR     0xd8
  95 #define  VID_DPHY_TIME_ADDR    0xdc
  96 #define  VID_ERR_COLOR1_ADDR   0xe0
  97 #define  VID_ERR_COLOR2_ADDR   0xe4
  98 #define  VID_VPOS_ADDR         0xe8
  99 #define  VID_HPOS_ADDR         0xec
 100 #define  VID_MODE_STAT_ADDR    0xf0
 101 #define  VID_VCA_SET1_ADDR     0xf4
 102 #define  VID_VCA_SET2_ADDR     0xf8
 103
 104
 105 #define  VID_MODE_STAT_CLR_ADDR    0x160
 106 #define  VID_MODE_STAT_FLAG_ADDR   0x180
 107
 108 #define  TVG_CTRL_ADDR      0x0fc
 109 #define  TVG_IMG_SIZE_ADDR  0x100
 110 #define  TVG_COLOR1_ADDR    0x104
 111 #define  TVG_COLOR1BIT_ADDR 0x108
 112 #define  TVG_COLOR2_ADDR    0x10c
 113 #define  TVG_COLOR2BIT_ADDR 0x110
 114 #define  TVG_STAT_ADDR      0x114
 115 #define  TVG_STAT_CTRL_ADDR 0x144
 116 #define  TVG_STAT_CLR_ADDR  0x164
 117 #define  TVG_STAT_FLAG_ADDR 0x184
 118
 119 #define  DPI_IRQ_EN_ADDR   0x1a0
 120 #define  DPI_IRQ_CLR_ADDR  0x1a4
 121 #define  DPI_IRQ_STAT_ADDR 0x1a4
 122 #define  DPI_CFG_ADDR      0x1ac
 123
 124
 125 //sysrst registers
 126 #define SRST_ASSERT0        0x00
 127 #define SRST_STATUS0            0x04
 128 /* Definition controller bit for syd rst registers */
 129 #define BIT_RST_DSI_DPI_PIX             17
 130
 131 struct sf_dphy {
 132         struct device *dev;
 133         void __iomem *topsys;
 134
 135         struct clk_bulk_data *clks;
 136
 137         struct clk * txesc_clk;
 138     struct reset_control *sys_rst;
 139         struct reset_control *txbytehs_rst;
 140
 141         void __iomem *aonsys;//7110 aonsys con
 142
 143         struct phy_configure_opts_mipi_dphy config;
 144
 145         u8 hsfreq;
 146
 147         struct regulator *mipitx_1p8;
 148         struct regulator *mipitx_0p9;
 149
 150         struct phy *phy;
 151 };
 152
 153 static int sf_dphy_clkrst_get(struct device *dev, struct sf_dphy *dphy)
 154 {
 155         dphy->txesc_clk = devm_clk_get(dev, "dphy_txesc");
 156         if (IS_ERR(dphy->txesc_clk)){
 157                 dev_err(dev, "===txesc_clk get error\n");
 158                 return PTR_ERR(dphy->txesc_clk);
 159         }
 160         dphy->sys_rst = reset_control_get_exclusive(dev, "dphy_sys");
 161         if (IS_ERR(dphy->sys_rst)){
 162                 dev_err(dev, "===sys_rst get error\n");
 163                 return PTR_ERR(dphy->sys_rst);
 164         }
 165
 166         return 0;
 167 }
 168 static int sf_dphy_clkrst_ena_deas(struct device *dev, struct sf_dphy *dphy)
 169 {
 170         int ret;
 171
 172         ret = clk_prepare_enable(dphy->txesc_clk);
 173         if (ret) {
 174         dev_err(dev, "failed to prepare/enable txesc_clk\n");
 175         return ret;
 176     }
 177         ret = reset_control_deassert(dphy->sys_rst);
 178         if (ret < 0) {
 179         dev_err(dev, "failed to deassert sys_rst\n");
 180         return ret;
 181     }
 182
 183         return ret;
 184 }
 185
 186 static int sf_dphy_clkrst_disa_assert(struct device *dev, struct sf_dphy *dphy)
 187 {
 188         int ret;
 189         ret = reset_control_assert(dphy->sys_rst);
 190         if (ret < 0) {
 191         dev_err(dev, "failed to assert sys_rst\n");
 192         return ret;
 193     }
 194
 195         clk_disable_unprepare(dphy->txesc_clk);
 196
 197         return ret;
 198 }
 199
 200 /*
 201 *static int sf_dphy_remove(struct platform_device *pdev)
 202 *{
 203 *       struct sf_dphy *dphy = dev_get_drvdata(&pdev->dev);
 204 *       reset_control_assert(dphy->sys_rst);
 205 *       //reset_control_assert(dphy->txbytehs_rst);
 206 *       clk_disable_unprepare(dphy->txesc_clk);
 207 *       return 0;
 208 *}
 209 */
 210
 211 #if 0
 212 static u32 top_sys_read32(struct sf_dphy *priv, u32 reg)
 213 {
 214         return ioread32(priv->topsys + reg);
 215 }
 216
 217
 218 static inline void top_sys_write32(struct sf_dphy *priv, u32 reg, u32 val)
 219 {
 220         iowrite32(val, priv->topsys + reg);
 221 }
 222
 223 static void dsi_csi2tx_sel(struct sf_dphy *priv, int sel)
 224 {
 225   u32 temp = 0;
 226   temp = top_sys_read32(priv, SCFG_DSI_CSI_SEL);
 227   temp &= ~(0x1);
 228   temp |= (sel & 0x1);
 229   top_sys_write32(priv, SCFG_DSI_CSI_SEL, temp);
 230 }
 231
 232 static void dphy_clane_hs_txready_sel(struct sf_dphy *priv, u32 ready_sel)
 233 {
 234         top_sys_write32(priv, SCFG_TXREADY_SRC_SEL_D, ready_sel);
 235         top_sys_write32(priv, SCFG_TXREADY_SRC_SEL_C, ready_sel);
 236         top_sys_write32(priv, SCFG_HS_PRE_ZERO_T_D, 0x30);
 237         top_sys_write32(priv, SCFG_HS_PRE_ZERO_T_C, 0x30);
 238 }
 239
 240 static void mipi_tx_lxn_set(struct sf_dphy *priv, u32 reg, u32 n_hstx, u32 p_hstx)
 241 {
 242         u32 temp = 0;
 243
 244         temp = n_hstx;
 245         temp |= p_hstx << 5;
 246         top_sys_write32(priv, reg, temp);
 247 }
 248
 249 static void dphy_config(struct sf_dphy *priv, int bit_rate)
 250 {
 251         int pre_div,      fbk_int,       extd_cycle_sel;
 252         int dhs_pre_time, dhs_zero_time, dhs_trial_time;
 253         int chs_pre_time, chs_zero_time, chs_trial_time;
 254         int chs_clk_pre_time, chs_clk_post_time;
 255         u32 set_val = 0;
 256
 257         mipi_tx_lxn_set(priv, SCFG_L0N_L0P_HSTX, 0x10, 0x10);
 258         mipi_tx_lxn_set(priv, SCFG_L1N_L1P_HSTX, 0x10, 0x10);
 259         mipi_tx_lxn_set(priv, SCFG_L2N_L2P_HSTX, 0x10, 0x10);
 260         mipi_tx_lxn_set(priv, SCFG_L3N_L3P_HSTX, 0x10, 0x10);
 261         mipi_tx_lxn_set(priv, SCFG_L4N_L4P_HSTX, 0x10, 0x10);
 262
 263         if(bit_rate == 80) {
 264                 pre_div=0x1,            fbk_int=2*0x33,         extd_cycle_sel=0x4,
 265                 dhs_pre_time=0xe,       dhs_zero_time=0x1d,     dhs_trial_time=0x15,
 266                 chs_pre_time=0x5,       chs_zero_time=0x2b,     chs_trial_time=0xd,
 267                 chs_clk_pre_time=0xf,
 268                 chs_clk_post_time=0x71;
 269         } else if (bit_rate == 100) {
 270                 pre_div=0x1,            fbk_int=2*0x40,         extd_cycle_sel=0x4,
 271                 dhs_pre_time=0x10,      dhs_zero_time=0x21,     dhs_trial_time=0x17,
 272                 chs_pre_time=0x7,       chs_zero_time=0x35,     chs_trial_time=0xf,
 273                 chs_clk_pre_time=0xf,
 274                 chs_clk_post_time=0x73;
 275         } else if (bit_rate == 200) {
 276                 pre_div=0x1,            fbk_int=2*0x40,         extd_cycle_sel=0x3;
 277                 dhs_pre_time=0xc,       dhs_zero_time=0x1b,     dhs_trial_time=0x13;
 278                 chs_pre_time=0x7,       chs_zero_time=0x35,     chs_trial_time=0xf,
 279                 chs_clk_pre_time=0x7,
 280                 chs_clk_post_time=0x3f;
 281         } else if(bit_rate == 300) {
 282                 pre_div=0x1,            fbk_int=2*0x60,         extd_cycle_sel=0x3,
 283                 dhs_pre_time=0x11,      dhs_zero_time=0x25, dhs_trial_time=0x19,
 284                 chs_pre_time=0xa,       chs_zero_time=0x50, chs_trial_time=0x15,
 285                 chs_clk_pre_time=0x7,
 286                 chs_clk_post_time=0x45;
 287     } else if(bit_rate == 400) {
 288                 pre_div=0x1,            fbk_int=2*0x40,         extd_cycle_sel=0x2,
 289                 dhs_pre_time=0xa,       dhs_zero_time=0x18,     dhs_trial_time=0x11,
 290                 chs_pre_time=0x7,       chs_zero_time=0x35, chs_trial_time=0xf,
 291                 chs_clk_pre_time=0x3,
 292                 chs_clk_post_time=0x25;
 293     } else if(bit_rate == 500 ) {
 294                 pre_div=0x1,      fbk_int=2*0x50,       extd_cycle_sel=0x2,
 295                 dhs_pre_time=0xc, dhs_zero_time=0x1d,   dhs_trial_time=0x14,
 296                 chs_pre_time=0x9, chs_zero_time=0x42,   chs_trial_time=0x12,
 297                 chs_clk_pre_time=0x3,
 298                 chs_clk_post_time=0x28;
 299     } else if(bit_rate == 600 ) {
 300                 pre_div=0x1,      fbk_int=2*0x60,       extd_cycle_sel=0x2,
 301                 dhs_pre_time=0xe, dhs_zero_time=0x23,   dhs_trial_time=0x17,
 302                 chs_pre_time=0xa, chs_zero_time=0x50,   chs_trial_time=0x15,
 303                 chs_clk_pre_time=0x3,
 304                 chs_clk_post_time=0x2b;
 305     } else if(bit_rate == 700) {
 306                 pre_div=0x1,      fbk_int=2*0x38,       extd_cycle_sel=0x1,
 307                 dhs_pre_time=0x8, dhs_zero_time=0x14,   dhs_trial_time=0xf,
 308                 chs_pre_time=0x6, chs_zero_time=0x2f,   chs_trial_time=0xe,
 309                 chs_clk_pre_time=0x1,
 310                 chs_clk_post_time=0x16;
 311     } else if(bit_rate == 800 ) {
 312                 pre_div=0x1,      fbk_int=2*0x40,       extd_cycle_sel=0x1,
 313                 dhs_pre_time=0x9, dhs_zero_time=0x17,   dhs_trial_time=0x10,
 314                 chs_pre_time=0x7, chs_zero_time=0x35,   chs_trial_time=0xf,
 315                 chs_clk_pre_time=0x1,
 316                 chs_clk_post_time=0x18;
 317     } else if(bit_rate == 900 ) {
 318                 pre_div=0x1,      fbk_int=2*0x48,       extd_cycle_sel=0x1,
 319                 dhs_pre_time=0xa, dhs_zero_time=0x19,   dhs_trial_time=0x12,
 320                 chs_pre_time=0x8, chs_zero_time=0x3c,   chs_trial_time=0x10,
 321                 chs_clk_pre_time=0x1,
 322                 chs_clk_post_time=0x19;
 323     } else if(bit_rate == 1000) {
 324                 pre_div=0x1,      fbk_int=2*0x50,       extd_cycle_sel=0x1,
 325                 dhs_pre_time=0xb, dhs_zero_time=0x1c,   dhs_trial_time=0x13,
 326                 chs_pre_time=0x9, chs_zero_time=0x42,   chs_trial_time=0x12,
 327                 chs_clk_pre_time=0x1,
 328                 chs_clk_post_time=0x1b;
 329     } else if(bit_rate == 1100) {
 330                 pre_div=0x1,      fbk_int=2*0x58,       extd_cycle_sel=0x1,
 331                 dhs_pre_time=0xc, dhs_zero_time=0x1e,   dhs_trial_time=0x15,
 332                 chs_pre_time=0x9, chs_zero_time=0x4a,   chs_trial_time=0x14,
 333                 chs_clk_pre_time=0x1,
 334                 chs_clk_post_time=0x1d;
 335     } else if(bit_rate == 1200) {
 336                 pre_div=0x1,      fbk_int=2*0x60,       extd_cycle_sel=0x1,
 337                 dhs_pre_time=0xe, dhs_zero_time=0x20,   dhs_trial_time=0x16,
 338                 chs_pre_time=0xa, chs_zero_time=0x50,   chs_trial_time=0x15,
 339                 chs_clk_pre_time=0x1,
 340                 chs_clk_post_time=0x1e;
 341     } else if(bit_rate == 1300) {
 342                 pre_div=0x1,      fbk_int=2*0x34,       extd_cycle_sel=0x0,
 343                 dhs_pre_time=0x7, dhs_zero_time=0x12,   dhs_trial_time=0xd,
 344                 chs_pre_time=0x5, chs_zero_time=0x2c,   chs_trial_time=0xd,
 345                 chs_clk_pre_time=0x0,
 346                 chs_clk_post_time=0xf;
 347     } else if(bit_rate == 1400) {
 348                 pre_div=0x1,      fbk_int=2*0x38,       extd_cycle_sel=0x0,
 349                 dhs_pre_time=0x7, dhs_zero_time=0x14,   dhs_trial_time=0xe,
 350                 chs_pre_time=0x6, chs_zero_time=0x2f,   chs_trial_time=0xe,
 351                 chs_clk_pre_time=0x0,
 352                 chs_clk_post_time=0x10;
 353     } else if(bit_rate == 1500) {
 354                 pre_div=0x1,      fbk_int=2*0x3c,       extd_cycle_sel=0x0,
 355                 dhs_pre_time=0x8, dhs_zero_time=0x14,   dhs_trial_time=0xf,
 356                 chs_pre_time=0x6, chs_zero_time=0x32,   chs_trial_time=0xe,
 357                 chs_clk_pre_time=0x0,
 358                 chs_clk_post_time=0x11;
 359     } else if(bit_rate == 1600) {
 360                 pre_div=0x1,      fbk_int=2*0x40,       extd_cycle_sel=0x0,
 361                 dhs_pre_time=0x9, dhs_zero_time=0x15,   dhs_trial_time=0x10,
 362                 chs_pre_time=0x7, chs_zero_time=0x35,   chs_trial_time=0xf,
 363                 chs_clk_pre_time=0x0,
 364                 chs_clk_post_time=0x12;
 365     } else if(bit_rate == 1700) {
 366                 pre_div=0x1,      fbk_int=2*0x44,       extd_cycle_sel=0x0,
 367                 dhs_pre_time=0x9, dhs_zero_time=0x17,   dhs_trial_time=0x10,
 368                 chs_pre_time=0x7, chs_zero_time=0x39,   chs_trial_time=0x10,
 369                 chs_clk_pre_time=0x0,
 370                 chs_clk_post_time=0x12;
 371     } else if(bit_rate == 1800) {
 372                 pre_div=0x1,      fbk_int=2*0x48,       extd_cycle_sel=0x0,
 373                 dhs_pre_time=0xa, dhs_zero_time=0x18,   dhs_trial_time=0x11,
 374                 chs_pre_time=0x8, chs_zero_time=0x3c,   chs_trial_time=0x10,
 375                 chs_clk_pre_time=0x0,
 376                 chs_clk_post_time=0x13;
 377     } else if(bit_rate == 1900) {
 378                 pre_div=0x1,      fbk_int=2*0x4c,       extd_cycle_sel=0x0,
 379                 dhs_pre_time=0xa, dhs_zero_time=0x1a,   dhs_trial_time=0x12,
 380                 chs_pre_time=0x8, chs_zero_time=0x3f,   chs_trial_time=0x11,
 381                 chs_clk_pre_time=0x0,
 382                 chs_clk_post_time=0x14;
 383     } else if(bit_rate == 2000) {
 384                 pre_div=0x1,      fbk_int=2*0x50,       extd_cycle_sel=0x0,
 385                 dhs_pre_time=0xb, dhs_zero_time=0x1b,   dhs_trial_time=0x13,
 386                 chs_pre_time=0x9, chs_zero_time=0x42,   chs_trial_time=0x12,
 387                 chs_clk_pre_time=0x0,
 388                 chs_clk_post_time=0x15;
 389     } else if(bit_rate == 2100) {
 390                 pre_div=0x1,      fbk_int=2*0x54,       extd_cycle_sel=0x0,
 391                 dhs_pre_time=0xb, dhs_zero_time=0x1c,   dhs_trial_time=0x13,
 392                 chs_pre_time=0x9, chs_zero_time=0x46,   chs_trial_time=0x13,
 393                 chs_clk_pre_time=0x0,
 394                 chs_clk_post_time=0x15;
 395     } else if(bit_rate == 2200) {
 396                 pre_div=0x1,      fbk_int=2*0x5b,       extd_cycle_sel=0x0,
 397                 dhs_pre_time=0xc, dhs_zero_time=0x1d,   dhs_trial_time=0x14,
 398                 chs_pre_time=0x9, chs_zero_time=0x4a,   chs_trial_time=0x14,
 399                 chs_clk_pre_time=0x0,
 400                 chs_clk_post_time=0x16;
 401     } else if(bit_rate == 2300) {
 402                 pre_div=0x1,      fbk_int=2*0x5c,       extd_cycle_sel=0x0,
 403                 dhs_pre_time=0xc, dhs_zero_time=0x1f,   dhs_trial_time=0x15,
 404                 chs_pre_time=0xa, chs_zero_time=0x4c,   chs_trial_time=0x14,
 405                 chs_clk_pre_time=0x0,
 406                 chs_clk_post_time=0x17;
 407     } else if(bit_rate == 2400) {
 408                 pre_div=0x1,      fbk_int=2*0x60,       extd_cycle_sel=0x0,
 409                 dhs_pre_time=0xd, dhs_zero_time=0x20,   dhs_trial_time=0x16,
 410                 chs_pre_time=0xa, chs_zero_time=0x50,   chs_trial_time=0x15,
 411                 chs_clk_pre_time=0x0,
 412                 chs_clk_post_time=0x18;
 413     } else if(bit_rate == 2500) {
 414                 pre_div=0x1,      fbk_int=2*0x64,       extd_cycle_sel=0x0,
 415                 dhs_pre_time=0xe, dhs_zero_time=0x21,   dhs_trial_time=0x16,
 416                 chs_pre_time=0xb, chs_zero_time=0x53,   chs_trial_time=0x16,
 417                 chs_clk_pre_time=0x0,
 418                 chs_clk_post_time=0x18;
 419     } else {
 420                 //default bit_rate == 700
 421                 pre_div=0x1,      fbk_int=2*0x38,       extd_cycle_sel=0x1,
 422                 dhs_pre_time=0x8, dhs_zero_time=0x14,   dhs_trial_time=0xf,
 423                 chs_pre_time=0x6, chs_zero_time=0x2f,   chs_trial_time=0xe,
 424                 chs_clk_pre_time=0x1,
 425                 chs_clk_post_time=0x16;
 426     }
 427         top_sys_write32(priv, SCFG_REFCLK_SEL, 0x3);
 428
 429         set_val = 0
 430                         | (1 << OFFSET_CFG_L1_SWAP_SEL)
 431                         | (4 << OFFSET_CFG_L2_SWAP_SEL)
 432                         | (2 << OFFSET_CFG_L3_SWAP_SEL)
 433                         | (3 << OFFSET_CFG_L4_SWAP_SEL);
 434         top_sys_write32(priv, SCFG_LX_SWAP_SEL, set_val);
 435
 436         set_val = 0
 437                         | (0 << OFFSET_SCFG_PWRON_READY_N)
 438                         | (1 << OFFSET_RG_CDTX_PLL_FM_EN)
 439                         | (0 << OFFSET_SCFG_PLLSSC_EN)
 440                         | (1 << OFFSET_RG_CDTX_PLL_LDO_STB_X2_EN);
 441         top_sys_write32(priv, SCFG_DBUS_PW_PLL_SSC_LD0, set_val);
 442
 443         set_val = fbk_int
 444                         | (pre_div << 9);
 445         top_sys_write32(priv, SCFG_RG_CDTX_PLL_FBK_PRE, set_val);
 446
 447         top_sys_write32(priv, SCFG_RG_EXTD_CYCLE_SEL, extd_cycle_sel);
 448
 449         set_val = chs_zero_time
 450                         | (dhs_pre_time << OFFSET_DHS_PRE_TIME)
 451                         | (dhs_trial_time << OFFSET_DHS_TRIAL_TIME)
 452                         | (dhs_zero_time << OFFSET_DHS_ZERO_TIME);
 453         top_sys_write32(priv, SCFG_RG_CLANE_DLANE_TIME, set_val);
 454
 455         set_val = chs_clk_post_time
 456                         | (chs_clk_pre_time << OFFSET_CHS_PRE_TIME)
 457                         | (chs_pre_time << OFFSET_CHS_TRIAL_TIME)
 458                         | (chs_trial_time << OFFSET_CHS_ZERO_TIME);
 459         top_sys_write32(priv, SCFG_RG_CLANE_HS_TIME, set_val);
 460
 461 }
 462
 463 static void reset_dphy(struct sf_dphy *priv, int resetb)
 464 {
 465         u32 cfg_dsc_enable = 0x01;//bit0
 466
 467         u32 precfg = top_sys_read32(priv, SCFG_PHY_RESETB);
 468         precfg &= ~(cfg_dsc_enable);
 469         precfg |= (resetb&cfg_dsc_enable);
 470         top_sys_write32(priv, SCFG_PHY_RESETB, precfg);
 471 }
 472
 473 static void polling_dphy_lock(struct sf_dphy *priv)
 474 {
 475         int pll_unlock;
 476
 477         udelay(10);
 478
 479         do {
 480                 pll_unlock = top_sys_read32(priv, SCFG_GRS_CDTX_PLL) >> 3;
 481                 pll_unlock &= 0x1;
 482         } while(pll_unlock == 0x1);
 483 }
 484
 485 static int sf_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
 486 {       //dev_info(dphy->dev,"--->sf_dphy_configure\n");
 487         struct sf_dphy *dphy = phy_get_drvdata(phy);
 488         uint32_t bit_rate = 800000000/1000000UL;//new mipi panel clock setting
 489         //uint32_t bit_rate = 500000000/1000000UL;//7110 mipi panel clock setting
 490
 491
 492         dphy_config(dphy, bit_rate);
 493         reset_dphy(dphy, 1);
 494         mdelay(10);
 495         polling_dphy_lock(dphy);
 496
 497         //dev_info(dphy->dev,"--->sf_dphy_configure\n");
 498         return 0;
 499 }
 500 #endif
 501
 502 static int is_pll_locked(struct sf_dphy *dphy)
 503 {
 504         int tmp = sf_dphy_get_reg(dphy->topsys + 0x8,
 505                                                                 RGS_CDTX_PLL_UNLOCK_SHIFT, RGS_CDTX_PLL_UNLOCK_MASK);
 506     return !tmp;
 507 }
 508 static void reset(int assert, struct sf_dphy *dphy)
 509 {
 510         dev_info(dphy->dev, "1 SET_U0_MIPITX_DPHY_RESETB\n");
 511         sf_dphy_set_reg(dphy->topsys + 0x64, (!assert), RESETB_SHIFT, RESETB_MASK);
 512         dev_info(dphy->dev, "2 SET_U0_MIPITX_DPHY_RESETB\n");
 513
 514     if (!assert) {
 515                 while(!is_pll_locked(dphy));
 516                 dev_info(dphy->dev, "MIPI dphy-tx # PLL Locked\n");
 517     }
 518 }
 519
 520 static int sys_m31_dphy_tx_configure(struct phy *phy, union phy_configure_opts *opts)
 521 {
 522         struct sf_dphy *dphy;
 523         uint32_t bitrate;
 524         unsigned long alignment;
 525         int i;
 526         const struct m31_dphy_config *p;
 527         const uint32_t AON_POWER_READY_N_active = 0;
 528         dphy = phy_get_drvdata(phy);
 529         bitrate = 500000000;
 530
 531         sf_dphy_set_reg(dphy->topsys + 0x8, 0x10,
 532                                         RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
 533         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 534                                         RG_CDTX_L0N_HSTX_RES_SHIFT, RG_CDTX_L0N_HSTX_RES_MASK);
 535         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 536                                         RG_CDTX_L2N_HSTX_RES_SHIFT, RG_CDTX_L2N_HSTX_RES_MASK);
 537         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 538                                         RG_CDTX_L3N_HSTX_RES_SHIFT, RG_CDTX_L3N_HSTX_RES_MASK);
 539         sf_dphy_set_reg(dphy->topsys + 0x10, 0x10,
 540                                         RG_CDTX_L4N_HSTX_RES_SHIFT, RG_CDTX_L4N_HSTX_RES_MASK);
 541         sf_dphy_set_reg(dphy->topsys + 0x8, 0x10,
 542                                         RG_CDTX_L0P_HSTX_RES_SHIFT, RG_CDTX_L0P_HSTX_RES_MASK);
 543         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 544                                         RG_CDTX_L1P_HSTX_RES_SHIFT, RG_CDTX_L1P_HSTX_RES_MASK);
 545         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 546                                         RG_CDTX_L2P_HSTX_RES_SHIFT, RG_CDTX_L2P_HSTX_RES_MASK);
 547         sf_dphy_set_reg(dphy->topsys + 0xC, 0x10,
 548                                         RG_CDTX_L3P_HSTX_RES_SHIFT, RG_CDTX_L3P_HSTX_RES_MASK);
 549         sf_dphy_set_reg(dphy->topsys + 0x10, 0x10,
 550                                         RG_CDTX_L4P_HSTX_RES_SHIFT, RG_CDTX_L4P_HSTX_RES_MASK);
 551
 552         dev_info(dphy->dev,"request dphy hs_rate %dMbps\n", bitrate/1000000);
 553         if (is_pll_locked(dphy))
 554                 dev_info(dphy->dev, "Error: MIPI dphy-tx # PLL is not supposed to be LOCKED\n");
 555         else
 556                 dev_info(dphy->dev, "MIPI dphy-tx # PLL is not LOCKED\n");
 557
 558     alignment = M31_DPHY_BITRATE_ALIGN;
 559     if (bitrate % alignment) {
 560         bitrate += alignment - (bitrate % alignment);
 561     }
 562
 563     dev_info(dphy->dev, "want dphy hs_rate %dMbps\n", bitrate/1000000);
 564
 565     p = m31_dphy_configs;
 566     for (i = 0; i < ARRAY_SIZE(m31_dphy_configs); i++, p++) {
 567         if (p->bitrate == bitrate) {
 568             dev_info(dphy->dev, "config dphy hs_rate %dMbps\n", bitrate/1000000);
 569
 570                         sf_dphy_set_reg(dphy->topsys + 0x64, M31_DPHY_REFCLK, REFCLK_IN_SEL_SHIFT, REFCLK_IN_SEL_MASK);
 571
 572             dev_info(dphy->dev, "MIPI dphy-tx # AON_POWER_READY_N active(%d)\n", AON_POWER_READY_N_active);
 573
 574
 575                         sf_dphy_set_reg(dphy->topsys, AON_POWER_READY_N_active,
 576                                                         AON_POWER_READY_N_SHIFT, AON_POWER_READY_N_MASK);
 577
 578                         sf_dphy_set_reg(dphy->topsys, 0x0,
 579                                                         CFG_L0_SWAP_SEL_SHIFT, CFG_L0_SWAP_SEL_MASK);//Lane setting
 580                         sf_dphy_set_reg(dphy->topsys, 0x1,
 581                                                         CFG_L1_SWAP_SEL_SHIFT, CFG_L1_SWAP_SEL_MASK);
 582                         sf_dphy_set_reg(dphy->topsys, 0x4,
 583                                                         CFG_L2_SWAP_SEL_SHIFT, CFG_L2_SWAP_SEL_MASK);
 584                         sf_dphy_set_reg(dphy->topsys, 0x2,
 585                                                         CFG_L3_SWAP_SEL_SHIFT, CFG_L3_SWAP_SEL_MASK);
 586                         sf_dphy_set_reg(dphy->topsys, 0x3,
 587                                                         CFG_L4_SWAP_SEL_SHIFT, CFG_L4_SWAP_SEL_MASK);
 588                         //PLL setting
 589                         sf_dphy_set_reg(dphy->topsys + 0x1c, 0x0,
 590                                                         RG_CDTX_PLL_SSC_EN_SHIFT, RG_CDTX_PLL_SSC_EN_MASK);
 591                         sf_dphy_set_reg(dphy->topsys + 0x18, 0x1,
 592                                                         RG_CDTX_PLL_LDO_STB_X2_EN_SHIFT, RG_CDTX_PLL_LDO_STB_X2_EN_MASK);
 593                         sf_dphy_set_reg(dphy->topsys + 0x18, 0x1,
 594                                                         RG_CDTX_PLL_FM_EN_SHIFT, RG_CDTX_PLL_FM_EN_MASK);
 595
 596                         sf_dphy_set_reg(dphy->topsys + 0x18, p->pll_prev_div,
 597                                                         RG_CDTX_PLL_PRE_DIV_SHIFT, RG_CDTX_PLL_PRE_DIV_MASK);
 598                         sf_dphy_set_reg(dphy->topsys + 0x18, p->pll_fbk_int,
 599                                                         RG_CDTX_PLL_FBK_INT_SHIFT, RG_CDTX_PLL_FBK_INT_MASK);
 600                         sf_dphy_set_reg(dphy->topsys + 0x14, p->pll_fbk_fra,
 601                                                         RG_CDTX_PLL_FBK_FRA_SHIFT, RG_CDTX_PLL_FBK_FRA_MASK);
 602                         sf_dphy_set_reg(dphy->topsys + 0x28, p->extd_cycle_sel,
 603                                                         RG_EXTD_CYCLE_SEL_SHIFT, RG_EXTD_CYCLE_SEL_MASK);
 604                         sf_dphy_set_reg(dphy->topsys + 0x24, p->dlane_hs_pre_time,
 605                                                         RG_DLANE_HS_PRE_TIME_SHIFT, RG_DLANE_HS_PRE_TIME_MASK);
 606                         sf_dphy_set_reg(dphy->topsys + 0x24, p->dlane_hs_pre_time,
 607                                                         RG_DLANE_HS_PRE_TIME_SHIFT, RG_DLANE_HS_PRE_TIME_MASK);
 608                         sf_dphy_set_reg(dphy->topsys + 0x24, p->dlane_hs_zero_time,
 609                                                         RG_DLANE_HS_ZERO_TIME_SHIFT, RG_DLANE_HS_ZERO_TIME_MASK);
 610                         sf_dphy_set_reg(dphy->topsys + 0x24, p->dlane_hs_trail_time,
 611                                                         RG_DLANE_HS_TRAIL_TIME_SHIFT, RG_DLANE_HS_TRAIL_TIME_MASK);
 612                         sf_dphy_set_reg(dphy->topsys + 0x20, p->clane_hs_pre_time,
 613                                                         RG_CLANE_HS_PRE_TIME_SHIFT, RG_CLANE_HS_PRE_TIME_MASK);
 614                         sf_dphy_set_reg(dphy->topsys + 0x24, p->clane_hs_zero_time,
 615                                                         RG_CLANE_HS_ZERO_TIME_SHIFT, RG_CLANE_HS_ZERO_TIME_MASK);
 616                         sf_dphy_set_reg(dphy->topsys + 0x20, p->clane_hs_trail_time,
 617                                                         RG_CLANE_HS_TRAIL_TIME_SHIFT, RG_CLANE_HS_TRAIL_TIME_MASK);
 618                         sf_dphy_set_reg(dphy->topsys + 0x20, p->clane_hs_clk_pre_time,
 619                                                         RG_CLANE_HS_CLK_PRE_TIME_SHIFT, RG_CLANE_HS_CLK_PRE_TIME_MASK);
 620                         sf_dphy_set_reg(dphy->topsys + 0x20, p->clane_hs_clk_post_time,
 621                                                         RG_CLANE_HS_CLK_POST_TIME_SHIFT, RG_CLANE_HS_CLK_POST_TIME_MASK);
 622
 623                         break;
 624                 }
 625         }
 626
 627         return -ENOTSUPP;
 628 }
 629
 630 static int sf_dphy_power_on(struct phy *phy)
 631 {
 632
 633         struct sf_dphy *dphy = phy_get_drvdata(phy);
 634         int ret;
 635
 636         reset(0, dphy);
 637         sf_dphy_set_reg(dphy->topsys + 0x30, 0,
 638                                         SCFG_PPI_C_READY_SEL_SHIFT, SCFG_PPI_C_READY_SEL_MASK);
 639         sf_dphy_set_reg(dphy->topsys + 0x30, 0,
 640                                         SCFG_DSI_TXREADY_ESC_SEL_SHIFT, SCFG_DSI_TXREADY_ESC_SEL_MASK);
 641         sf_dphy_set_reg(dphy->topsys + 0x2c, 0x30,
 642                                         SCFG_C_HS_PRE_ZERO_TIME_SHIFT, SCFG_C_HS_PRE_ZERO_TIME_MASK);
 643
 644         ret = sf_dphy_clkrst_ena_deas(dphy->dev, dphy);//clk rst interface enable and deassert
 645
 646         return 0;
 647 }
 648
 649 static int sf_dphy_power_off(struct phy *phy)
 650 {
 651         struct sf_dphy *dphy = phy_get_drvdata(phy);
 652
 653         sf_dphy_clkrst_disa_assert(dphy->dev, dphy);
 654         reset(1, dphy);
 655         return 0;
 656 }
 657
 658 static int sf_dphy_init(struct phy *phy)
 659 {
 660         return 0;
 661 }
 662
 663 static int sf_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
 664                         union phy_configure_opts *opts)
 665 {
 666         return 0;
 667 }
 668
 669 static int sf_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
 670 {
 671         return 0;
 672 }
 673
 674
 675 static int sf_dphy_exit(struct phy *phy)
 676 {
 677         return 0;
 678 }
 679
 680 static const struct phy_ops sf_dphy_ops = {
 681         .power_on       = sf_dphy_power_on,
 682         .power_off      = sf_dphy_power_off,
 683         .init           = sf_dphy_init,
 684         .exit           = sf_dphy_exit,
 685         //.configure    = sf_dphy_configure,
 686         .configure      = sys_m31_dphy_tx_configure,
 687         .validate  = sf_dphy_validate,
 688         .set_mode  = sf_dphy_set_mode,
 689         .owner          = THIS_MODULE,
 690 };
 691
 692 static const struct of_device_id sf_dphy_dt_ids[] = {
 693         {
 694                 .compatible = "starfive,jh7100-mipi-dphy-tx",
 695         },
 696         {}
 697 };
 698 MODULE_DEVICE_TABLE(of, sf_dphy_dt_ids);
 699
 700 static int sf_dphy_probe(struct platform_device *pdev)
 701 {
 702         struct phy_provider *phy_provider;
 703         struct sf_dphy *dphy;
 704         struct resource *res;
 705         int ret;
 706         uint32_t temp;
 707
 708         dev_info(&pdev->dev, "sf_dphy_probe begin\n");
 709         dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
 710         if (!dphy)
 711                 return -ENOMEM;
 712         dev_set_drvdata(&pdev->dev, dphy);
 713
 714         dev_info(&pdev->dev, "===> %s enter, %d \n", __func__, __LINE__);
 715
 716         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 717         dphy->topsys = devm_ioremap_resource(&pdev->dev, res);
 718         if (IS_ERR(dphy->topsys))
 719                 return PTR_ERR(dphy->topsys);
 720
 721
 722         dphy->phy = devm_phy_create(&pdev->dev, NULL, &sf_dphy_ops);
 723         if (IS_ERR(dphy->phy)) {
 724                 dev_err(&pdev->dev, "failed to create phy\n");
 725                 return PTR_ERR(dphy->phy);
 726         }
 727         phy_set_drvdata(dphy->phy, dphy);
 728
 729         dphy->dev = &pdev->dev;
 730         // this power switch control bit was added in ECO, check ECO item "aon psw_en" for detail
 731         dev_info(dphy->dev, "control ECO\n");
 732         dphy->aonsys = ioremap(0x17010000, 0x10000);
 733         temp = 0;
 734         temp = sf_dphy_get_reg(dphy->aonsys, AON_GP_REG_SHIFT,AON_GP_REG_MASK);
 735         dev_info(dphy->dev, "GET_AON_GP_REG\n");
 736
 737         if (!(temp & DPHY_TX_PSW_EN_MASK)) {
 738                 temp |= DPHY_TX_PSW_EN_MASK;
 739                 sf_dphy_set_reg(dphy->aonsys, temp,AON_GP_REG_SHIFT,AON_GP_REG_MASK);
 740         }
 741         dev_info(dphy->dev, "control ECO\n");
 742
 743         //mipi_pmic setting
 744         dphy->mipitx_1p8 = devm_regulator_get(&pdev->dev, "mipitx_1p8");
 745         if (IS_ERR(dphy->mipitx_1p8))
 746                 return PTR_ERR(dphy->mipitx_1p8);
 747
 748         dphy->mipitx_0p9 = devm_regulator_get(&pdev->dev, "mipitx_0p9");
 749         if (IS_ERR(dphy->mipitx_0p9))
 750                 return PTR_ERR(dphy->mipitx_0p9);
 751
 752         //pmic turn on
 753         ret = regulator_enable(dphy->mipitx_0p9);
 754         if (ret) {
 755                 dev_err(&pdev->dev, "Cannot enable mipitx_0p9 regulator\n");
 756                 //goto err_reg_0p9;
 757         }
 758         udelay(100);
 759         ret = regulator_enable(dphy->mipitx_1p8);
 760         if (ret) {
 761                 dev_err(&pdev->dev, "Cannot enable mipitx_1p8 regulator\n");
 762                 //goto err_reg_1p8;
 763         }
 764         udelay(100);
 765         //mipi_pmic setting
 766
 767         ret = sf_dphy_clkrst_get(&pdev->dev, dphy);
 768
 769         phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
 770
 771         dev_info(&pdev->dev, "sf_dphy_probe end\n");
 772
 773         return PTR_ERR_OR_ZERO(phy_provider);
 774 }
 775
 776 static struct platform_driver sf_dphy_driver = {
 777         .probe = sf_dphy_probe,
 778         .driver = {
 779                 .name   = "sf-mipi-dphy-tx",
 780                 .of_match_table = sf_dphy_dt_ids,
 781         },
 782 };
 783 module_platform_driver(sf_dphy_driver);
 784
 785 MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
 786 MODULE_DESCRIPTION("sf MIPI  DPHY TX0 driver");
 787 MODULE_LICENSE("Dual MIT/GPL");