drivers/phy/cadence/phy-cadence-torrent.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cadence Torrent SD0801 PHY driver.
   4  *
   5  * Based on the linux driver provided by Cadence
   6  *
   7  * Copyright (c) 2018 Cadence Design Systems
   8  *
   9  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  10  *
  11  */
  12
  13 #include <common.h>
  14 #include <clk.h>
  15 #include <generic-phy.h>
  16 #include <reset.h>
  17 #include <dm/device.h>
  18 #include <dm/device_compat.h>
  19 #include <dm/device-internal.h>
  20 #include <dm/lists.h>
  21 #include <dm/read.h>
  22 #include <dm/uclass.h>
  23 #include <linux/io.h>
  24 #include <dt-bindings/phy/phy.h>
  25 #include <regmap.h>
  26 #include <linux/delay.h>
  27 #include <linux/string.h>
  28
  29 #define REF_CLK_19_2MHz         19200000
  30 #define REF_CLK_25MHz           25000000
  31
  32 #define MAX_NUM_LANES           4
  33 #define DEFAULT_MAX_BIT_RATE    8100 /* in Mbps*/
  34
  35 #define NUM_SSC_MODE            3
  36 #define NUM_PHY_TYPE            6
  37
  38 #define POLL_TIMEOUT_US         5000
  39 #define PLL_LOCK_TIMEOUT        100000
  40
  41 #define TORRENT_COMMON_CDB_OFFSET       0x0
  42
  43 #define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)        \
  44                                 ((0x4000 << (block_offset)) +           \
  45                                 (((ln) << 9) << (reg_offset)))
  46 #define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)        \
  47                                 ((0x8000 << (block_offset)) +           \
  48                                 (((ln) << 9) << (reg_offset)))
  49
  50 #define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)     \
  51                                 (0xC000 << (block_offset))
  52
  53 #define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)     \
  54                                 (0xE000 << (block_offset))
  55
  56 /*
  57  * register offsets from SD0801 PHY register block base (i.e MHDP
  58  * register base + 0x500000)
  59  */
  60 #define CMN_SSM_BANDGAP_TMR             0x0021U
  61 #define CMN_SSM_BIAS_TMR                0x0022U
  62 #define CMN_PLLSM0_PLLPRE_TMR           0x002AU
  63 #define CMN_PLLSM0_PLLLOCK_TMR          0x002CU
  64 #define CMN_PLLSM1_PLLPRE_TMR           0x0032U
  65 #define CMN_PLLSM1_PLLLOCK_TMR          0x0034U
  66 #define CMN_CDIAG_CDB_PWRI_OVRD         0x0041U
  67 #define CMN_CDIAG_XCVRC_PWRI_OVRD       0x0047U
  68 #define CMN_BGCAL_INIT_TMR              0x0064U
  69 #define CMN_BGCAL_ITER_TMR              0x0065U
  70 #define CMN_IBCAL_INIT_TMR              0x0074U
  71 #define CMN_PLL0_VCOCAL_TCTRL           0x0082U
  72 #define CMN_PLL0_VCOCAL_INIT_TMR        0x0084U
  73 #define CMN_PLL0_VCOCAL_ITER_TMR        0x0085U
  74 #define CMN_PLL0_VCOCAL_REFTIM_START    0x0086U
  75 #define CMN_PLL0_VCOCAL_PLLCNT_START    0x0088U
  76 #define CMN_PLL0_INTDIV_M0              0x0090U
  77 #define CMN_PLL0_FRACDIVL_M0            0x0091U
  78 #define CMN_PLL0_FRACDIVH_M0            0x0092U
  79 #define CMN_PLL0_HIGH_THR_M0            0x0093U
  80 #define CMN_PLL0_DSM_DIAG_M0            0x0094U
  81 #define CMN_PLL0_SS_CTRL1_M0            0x0098U
  82 #define CMN_PLL0_SS_CTRL2_M0            0x0099U
  83 #define CMN_PLL0_SS_CTRL3_M0            0x009AU
  84 #define CMN_PLL0_SS_CTRL4_M0            0x009BU
  85 #define CMN_PLL0_LOCK_REFCNT_START      0x009CU
  86 #define CMN_PLL0_LOCK_PLLCNT_START      0x009EU
  87 #define CMN_PLL0_LOCK_PLLCNT_THR        0x009FU
  88 #define CMN_PLL0_INTDIV_M1              0x00A0U
  89 #define CMN_PLL0_FRACDIVH_M1            0x00A2U
  90 #define CMN_PLL0_HIGH_THR_M1            0x00A3U
  91 #define CMN_PLL0_DSM_DIAG_M1            0x00A4U
  92 #define CMN_PLL0_SS_CTRL1_M1            0x00A8U
  93 #define CMN_PLL0_SS_CTRL2_M1            0x00A9U
  94 #define CMN_PLL0_SS_CTRL3_M1            0x00AAU
  95 #define CMN_PLL0_SS_CTRL4_M1            0x00ABU
  96 #define CMN_PLL1_VCOCAL_TCTRL           0x00C2U
  97 #define CMN_PLL1_VCOCAL_INIT_TMR        0x00C4U
  98 #define CMN_PLL1_VCOCAL_ITER_TMR        0x00C5U
  99 #define CMN_PLL1_VCOCAL_REFTIM_START    0x00C6U
 100 #define CMN_PLL1_VCOCAL_PLLCNT_START    0x00C8U
 101 #define CMN_PLL1_INTDIV_M0              0x00D0U
 102 #define CMN_PLL1_FRACDIVL_M0            0x00D1U
 103 #define CMN_PLL1_FRACDIVH_M0            0x00D2U
 104 #define CMN_PLL1_HIGH_THR_M0            0x00D3U
 105 #define CMN_PLL1_DSM_DIAG_M0            0x00D4U
 106 #define CMN_PLL1_DSM_FBH_OVRD_M0        0x00D5U
 107 #define CMN_PLL1_DSM_FBL_OVRD_M0        0x00D6U
 108 #define CMN_PLL1_SS_CTRL1_M0            0x00D8U
 109 #define CMN_PLL1_SS_CTRL2_M0            0x00D9U
 110 #define CMN_PLL1_SS_CTRL3_M0            0x00DAU
 111 #define CMN_PLL1_SS_CTRL4_M0            0x00DBU
 112 #define CMN_PLL1_LOCK_REFCNT_START      0x00DCU
 113 #define CMN_PLL1_LOCK_PLLCNT_START      0x00DEU
 114 #define CMN_PLL1_LOCK_PLLCNT_THR        0x00DFU
 115 #define CMN_TXPUCAL_TUNE                0x0103U
 116 #define CMN_TXPUCAL_INIT_TMR            0x0104U
 117 #define CMN_TXPUCAL_ITER_TMR            0x0105U
 118 #define CMN_CMN_TXPDCAL_OVRD            0x0109U
 119 #define CMN_TXPDCAL_TUNE                0x010BU
 120 #define CMN_TXPDCAL_INIT_TMR            0x010CU
 121 #define CMN_TXPDCAL_ITER_TMR            0x010DU
 122 #define CMN_RXCAL_INIT_TMR              0x0114U
 123 #define CMN_RXCAL_ITER_TMR              0x0115U
 124 #define CMN_SD_CAL_INIT_TMR             0x0124U
 125 #define CMN_SD_CAL_ITER_TMR             0x0125U
 126 #define CMN_SD_CAL_REFTIM_START         0x0126U
 127 #define CMN_SD_CAL_PLLCNT_START         0x0128U
 128 #define CMN_PDIAG_PLL0_CTRL_M0          0x01A0U
 129 #define CMN_PDIAG_PLL0_CLK_SEL_M0       0x01A1U
 130 #define CMN_PDIAG_PLL0_CP_PADJ_M0       0x01A4U
 131 #define CMN_PDIAG_PLL0_CP_IADJ_M0       0x01A5U
 132 #define CMN_PDIAG_PLL0_FILT_PADJ_M0     0x01A6U
 133 #define CMN_PDIAG_PLL0_CTRL_M1          0x01B0U
 134 #define CMN_PDIAG_PLL0_CLK_SEL_M1       0x01B1U
 135 #define CMN_PDIAG_PLL0_CP_PADJ_M1       0x01B4U
 136 #define CMN_PDIAG_PLL0_CP_IADJ_M1       0x01B5U
 137 #define CMN_PDIAG_PLL0_FILT_PADJ_M1     0x01B6U
 138 #define CMN_PDIAG_PLL1_CTRL_M0          0x01C0U
 139 #define CMN_PDIAG_PLL1_CLK_SEL_M0       0x01C1U
 140 #define CMN_PDIAG_PLL1_CP_PADJ_M0       0x01C4U
 141 #define CMN_PDIAG_PLL1_CP_IADJ_M0       0x01C5U
 142 #define CMN_PDIAG_PLL1_FILT_PADJ_M0     0x01C6U
 143 #define CMN_DIAG_BIAS_OVRD1             0x01E1U
 144
 145 /* PMA TX Lane registers */
 146 #define TX_TXCC_CTRL                    0x0040U
 147 #define TX_TXCC_CPOST_MULT_00           0x004CU
 148 #define TX_TXCC_CPOST_MULT_01           0x004DU
 149 #define TX_TXCC_MGNFS_MULT_000          0x0050U
 150 #define TX_TXCC_MGNFS_MULT_100          0x0054U
 151 #define DRV_DIAG_TX_DRV                 0x00C6U
 152 #define XCVR_DIAG_PLLDRC_CTRL           0x00E5U
 153 #define XCVR_DIAG_HSCLK_SEL             0x00E6U
 154 #define XCVR_DIAG_HSCLK_DIV             0x00E7U
 155 #define XCVR_DIAG_RXCLK_CTRL            0x00E9U
 156 #define XCVR_DIAG_BIDI_CTRL             0x00EAU
 157 #define XCVR_DIAG_PSC_OVRD              0x00EBU
 158 #define TX_PSC_A0                       0x0100U
 159 #define TX_PSC_A1                       0x0101U
 160 #define TX_PSC_A2                       0x0102U
 161 #define TX_PSC_A3                       0x0103U
 162 #define TX_RCVDET_ST_TMR                0x0123U
 163 #define TX_DIAG_ACYA                    0x01E7U
 164 #define TX_DIAG_ACYA_HBDC_MASK          0x0001U
 165
 166 /* PMA RX Lane registers */
 167 #define RX_PSC_A0                       0x0000U
 168 #define RX_PSC_A1                       0x0001U
 169 #define RX_PSC_A2                       0x0002U
 170 #define RX_PSC_A3                       0x0003U
 171 #define RX_PSC_CAL                      0x0006U
 172 #define RX_CDRLF_CNFG                   0x0080U
 173 #define RX_CDRLF_CNFG3                  0x0082U
 174 #define RX_SIGDET_HL_FILT_TMR           0x0090U
 175 #define RX_REE_GCSM1_CTRL               0x0108U
 176 #define RX_REE_GCSM1_EQENM_PH1          0x0109U
 177 #define RX_REE_GCSM1_EQENM_PH2          0x010AU
 178 #define RX_REE_GCSM2_CTRL               0x0110U
 179 #define RX_REE_PERGCSM_CTRL             0x0118U
 180 #define RX_REE_ATTEN_THR                0x0149U
 181 #define RX_REE_TAP1_CLIP                0x0171U
 182 #define RX_REE_TAP2TON_CLIP             0x0172U
 183 #define RX_REE_SMGM_CTRL1               0x0177U
 184 #define RX_REE_SMGM_CTRL2               0x0178U
 185 #define RX_DIAG_DFE_CTRL                0x01E0U
 186 #define RX_DIAG_DFE_AMP_TUNE_2          0x01E2U
 187 #define RX_DIAG_DFE_AMP_TUNE_3          0x01E3U
 188 #define RX_DIAG_NQST_CTRL               0x01E5U
 189 #define RX_DIAG_SIGDET_TUNE             0x01E8U
 190 #define RX_DIAG_PI_RATE                 0x01F4U
 191 #define RX_DIAG_PI_CAP                  0x01F5U
 192 #define RX_DIAG_ACYA                    0x01FFU
 193
 194 /* PHY PCS common registers */
 195 #define PHY_PLL_CFG                     0x000EU
 196 #define PHY_PIPE_USB3_GEN2_PRE_CFG0     0x0020U
 197 #define PHY_PIPE_USB3_GEN2_POST_CFG0    0x0022U
 198 #define PHY_PIPE_USB3_GEN2_POST_CFG1    0x0023U
 199
 200 /* PHY PMA common registers */
 201 #define PHY_PMA_CMN_CTRL1               0x0000U
 202 #define PHY_PMA_CMN_CTRL2               0x0001U
 203 #define PHY_PMA_PLL_RAW_CTRL            0x0003U
 204
 205 static const struct reg_field phy_pll_cfg =  REG_FIELD(PHY_PLL_CFG, 0, 1);
 206 static const struct reg_field phy_pma_cmn_ctrl_1 =
 207                                         REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);
 208 static const struct reg_field phy_pma_cmn_ctrl_2 =
 209                                         REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);
 210 static const struct reg_field phy_pma_pll_raw_ctrl =
 211                                         REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);
 212
 213 #define reset_control_assert reset_assert
 214 #define reset_control_deassert reset_deassert
 215 #define reset_control reset_ctl
 216 #define reset_control_put reset_free
 217
 218 enum cdns_torrent_phy_type {
 219         TYPE_NONE,
 220         TYPE_DP,
 221         TYPE_PCIE,
 222         TYPE_SGMII,
 223         TYPE_QSGMII,
 224         TYPE_USB,
 225 };
 226
 227 enum cdns_torrent_ssc_mode {
 228         NO_SSC,
 229         EXTERNAL_SSC,
 230         INTERNAL_SSC
 231 };
 232
 233 struct cdns_torrent_inst {
 234         struct phy *phy;
 235         u32 mlane;
 236         enum cdns_torrent_phy_type phy_type;
 237         u32 num_lanes;
 238         struct reset_ctl_bulk *lnk_rst;
 239         enum cdns_torrent_ssc_mode ssc_mode;
 240 };
 241
 242 struct cdns_torrent_phy {
 243         void __iomem *sd_base;  /* SD0801 register base  */
 244         size_t size;
 245         struct reset_control *phy_rst;
 246         struct udevice *dev;
 247         struct cdns_torrent_inst phys[MAX_NUM_LANES];
 248         int nsubnodes;
 249         const struct cdns_torrent_data *init_data;
 250         struct regmap *regmap;
 251         struct regmap *regmap_common_cdb;
 252         struct regmap *regmap_phy_pcs_common_cdb;
 253         struct regmap *regmap_phy_pma_common_cdb;
 254         struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];
 255         struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];
 256         struct regmap_field *phy_pll_cfg;
 257         struct regmap_field *phy_pma_cmn_ctrl_1;
 258         struct regmap_field *phy_pma_cmn_ctrl_2;
 259         struct regmap_field *phy_pma_pll_raw_ctrl;
 260 };
 261
 262 struct cdns_reg_pairs {
 263         u32 val;
 264         u32 off;
 265 };
 266
 267 struct cdns_torrent_vals {
 268         struct cdns_reg_pairs *reg_pairs;
 269         u32 num_regs;
 270 };
 271
 272 struct cdns_torrent_data {
 273         u8 block_offset_shift;
 274         u8 reg_offset_shift;
 275         struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 276                                                [NUM_SSC_MODE];
 277         struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 278                                                 [NUM_SSC_MODE];
 279         struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 280                                                [NUM_SSC_MODE];
 281         struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 282                                           [NUM_SSC_MODE];
 283         struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 284                                           [NUM_SSC_MODE];
 285         struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 286                                             [NUM_SSC_MODE];
 287 };
 288
 289 static inline struct cdns_torrent_inst *phy_get_drvdata(struct phy *phy)
 290 {
 291         struct cdns_torrent_phy *sp = dev_get_priv(phy->dev);
 292         int index;
 293
 294         if (phy->id >= MAX_NUM_LANES)
 295                 return NULL;
 296
 297         for (index = 0; index < sp->nsubnodes; index++) {
 298                 if (phy->id == sp->phys[index].mlane)
 299                         return &sp->phys[index];
 300         }
 301
 302         return NULL;
 303 }
 304
 305 static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base,
 306                                        u32 block_offset,
 307                                        u8 reg_offset_shift)
 308 {
 309         struct cdns_torrent_phy *sp = dev_get_priv(dev);
 310         struct regmap_config config;
 311
 312         config.r_start = (ulong)(base + block_offset);
 313         config.r_size = sp->size - block_offset;
 314         config.reg_offset_shift = reg_offset_shift;
 315         config.width = REGMAP_SIZE_16;
 316
 317         return devm_regmap_init(dev, NULL, NULL, &config);
 318 }
 319
 320 static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)
 321 {
 322         struct udevice *dev = cdns_phy->dev;
 323         struct regmap_field *field;
 324         struct regmap *regmap;
 325
 326         regmap = cdns_phy->regmap_phy_pcs_common_cdb;
 327         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);
 328         if (IS_ERR(field)) {
 329                 dev_err(dev, "PHY_PLL_CFG reg field init failed\n");
 330                 return PTR_ERR(field);
 331         }
 332         cdns_phy->phy_pll_cfg = field;
 333
 334         regmap = cdns_phy->regmap_phy_pma_common_cdb;
 335         field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);
 336         if (IS_ERR(field)) {
 337                 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");
 338                 return PTR_ERR(field);
 339         }
 340         cdns_phy->phy_pma_cmn_ctrl_1 = field;
 341
 342         regmap = cdns_phy->regmap_phy_pma_common_cdb;
 343         field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);
 344         if (IS_ERR(field)) {
 345                 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");
 346                 return PTR_ERR(field);
 347         }
 348         cdns_phy->phy_pma_cmn_ctrl_2 = field;
 349
 350         regmap = cdns_phy->regmap_phy_pma_common_cdb;
 351         field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);
 352         if (IS_ERR(field)) {
 353                 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");
 354                 return PTR_ERR(field);
 355         }
 356         cdns_phy->phy_pma_pll_raw_ctrl = field;
 357
 358         return 0;
 359 }
 360
 361 static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)
 362 {
 363         void __iomem *sd_base = cdns_phy->sd_base;
 364         u8 block_offset_shift, reg_offset_shift;
 365         struct udevice *dev = cdns_phy->dev;
 366         struct regmap *regmap;
 367         u32 block_offset;
 368         int i;
 369
 370         block_offset_shift = cdns_phy->init_data->block_offset_shift;
 371         reg_offset_shift = cdns_phy->init_data->reg_offset_shift;
 372
 373         for (i = 0; i < MAX_NUM_LANES; i++) {
 374                 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,
 375                                                           reg_offset_shift);
 376
 377                 regmap = cdns_regmap_init(dev, sd_base, block_offset,
 378                                           reg_offset_shift);
 379                 if (IS_ERR(regmap)) {
 380                         dev_err(dev, "Failed to init tx lane CDB regmap\n");
 381                         return PTR_ERR(regmap);
 382                 }
 383                 cdns_phy->regmap_tx_lane_cdb[i] = regmap;
 384                 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,
 385                                                           reg_offset_shift);
 386                 regmap = cdns_regmap_init(dev, sd_base, block_offset,
 387                                           reg_offset_shift);
 388                 if (IS_ERR(regmap)) {
 389                         dev_err(dev, "Failed to init rx lane CDB regmap");
 390                         return PTR_ERR(regmap);
 391                 }
 392                 cdns_phy->regmap_rx_lane_cdb[i] = regmap;
 393         }
 394
 395         block_offset = TORRENT_COMMON_CDB_OFFSET;
 396         regmap = cdns_regmap_init(dev, sd_base, block_offset,
 397                                   reg_offset_shift);
 398         if (IS_ERR(regmap)) {
 399                 dev_err(dev, "Failed to init common CDB regmap\n");
 400                 return PTR_ERR(regmap);
 401         }
 402         cdns_phy->regmap_common_cdb = regmap;
 403
 404         block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);
 405         regmap = cdns_regmap_init(dev, sd_base, block_offset,
 406                                   reg_offset_shift);
 407         if (IS_ERR(regmap)) {
 408                 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
 409                 return PTR_ERR(regmap);
 410         }
 411         cdns_phy->regmap_phy_pcs_common_cdb = regmap;
 412
 413         block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);
 414         regmap = cdns_regmap_init(dev, sd_base, block_offset,
 415                                   reg_offset_shift);
 416         if (IS_ERR(regmap)) {
 417                 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
 418                 return PTR_ERR(regmap);
 419         }
 420         cdns_phy->regmap_phy_pma_common_cdb = regmap;
 421
 422         return 0;
 423 }
 424
 425 static int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)
 426 {
 427         const struct cdns_torrent_data *init_data = cdns_phy->init_data;
 428         struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
 429         struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
 430         enum cdns_torrent_phy_type phy_t1, phy_t2, tmp_phy_type;
 431         struct cdns_torrent_vals *pcs_cmn_vals;
 432         int i, j, node, mlane, num_lanes, ret;
 433         struct cdns_reg_pairs *reg_pairs;
 434         enum cdns_torrent_ssc_mode ssc;
 435         struct regmap *regmap;
 436         u32 num_regs;
 437
 438         /* Maximum 2 links (subnodes) are supported */
 439         if (cdns_phy->nsubnodes != 2)
 440                 return -EINVAL;
 441
 442         phy_t1 = cdns_phy->phys[0].phy_type;
 443         phy_t2 = cdns_phy->phys[1].phy_type;
 444
 445         /*
 446          * First configure the PHY for first link with phy_t1. Geth the array
 447          * values are [phy_t1][phy_t2][ssc].
 448          */
 449         for (node = 0; node < cdns_phy->nsubnodes; node++) {
 450                 if (node == 1) {
 451                         /*
 452                          * If fist link with phy_t1 is configured, then
 453                          * configure the PHY for second link with phy_t2.
 454                          * Get the array values as [phy_t2][phy_t1][ssc]
 455                          */
 456                         tmp_phy_type = phy_t1;
 457                         phy_t1 = phy_t2;
 458                         phy_t2 = tmp_phy_type;
 459                 }
 460
 461                 mlane = cdns_phy->phys[node].mlane;
 462                 ssc = cdns_phy->phys[node].ssc_mode;
 463                 num_lanes = cdns_phy->phys[node].num_lanes;
 464
 465                 /**
 466                  * PHY configuration specific registers:
 467                  * link_cmn_vals depend on combination of PHY types being
 468                  * configured and are common for both PHY types, so array
 469                  * values should be same for [phy_t1][phy_t2][ssc] and
 470                  * [phy_t2][phy_t1][ssc].
 471                  * xcvr_diag_vals also depend on combination of PHY types
 472                  * being configured, but these can be different for particular
 473                  * PHY type and are per lane.
 474                  */
 475                 link_cmn_vals = init_data->link_cmn_vals[phy_t1][phy_t2][ssc];
 476                 if (link_cmn_vals) {
 477                         reg_pairs = link_cmn_vals->reg_pairs;
 478                         num_regs = link_cmn_vals->num_regs;
 479                         regmap = cdns_phy->regmap_common_cdb;
 480
 481                         /**
 482                          * First array value in link_cmn_vals must be of
 483                          * PHY_PLL_CFG register
 484                          */
 485                         regmap_field_write(cdns_phy->phy_pll_cfg,
 486                                            reg_pairs[0].val);
 487
 488                         for (i = 1; i < num_regs; i++)
 489                                 regmap_write(regmap, reg_pairs[i].off,
 490                                              reg_pairs[i].val);
 491                 }
 492
 493                 xcvr_diag_vals = init_data->xcvr_diag_vals[phy_t1][phy_t2][ssc];
 494                 if (xcvr_diag_vals) {
 495                         reg_pairs = xcvr_diag_vals->reg_pairs;
 496                         num_regs = xcvr_diag_vals->num_regs;
 497                         for (i = 0; i < num_lanes; i++) {
 498                                 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
 499                                 for (j = 0; j < num_regs; j++)
 500                                         regmap_write(regmap, reg_pairs[j].off,
 501                                                      reg_pairs[j].val);
 502                         }
 503                 }
 504
 505                 /* PHY PCS common registers configurations */
 506                 pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];
 507                 if (pcs_cmn_vals) {
 508                         reg_pairs = pcs_cmn_vals->reg_pairs;
 509                         num_regs = pcs_cmn_vals->num_regs;
 510                         regmap = cdns_phy->regmap_phy_pcs_common_cdb;
 511                         for (i = 0; i < num_regs; i++)
 512                                 regmap_write(regmap, reg_pairs[i].off,
 513                                              reg_pairs[i].val);
 514                 }
 515
 516                 /* PMA common registers configurations */
 517                 cmn_vals = init_data->cmn_vals[phy_t1][phy_t2][ssc];
 518                 if (cmn_vals) {
 519                         reg_pairs = cmn_vals->reg_pairs;
 520                         num_regs = cmn_vals->num_regs;
 521                         regmap = cdns_phy->regmap_common_cdb;
 522                         for (i = 0; i < num_regs; i++)
 523                                 regmap_write(regmap, reg_pairs[i].off,
 524                                              reg_pairs[i].val);
 525                 }
 526
 527                 /* PMA TX lane registers configurations */
 528                 tx_ln_vals = init_data->tx_ln_vals[phy_t1][phy_t2][ssc];
 529                 if (tx_ln_vals) {
 530                         reg_pairs = tx_ln_vals->reg_pairs;
 531                         num_regs = tx_ln_vals->num_regs;
 532                         for (i = 0; i < num_lanes; i++) {
 533                                 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];
 534                                 for (j = 0; j < num_regs; j++)
 535                                         regmap_write(regmap, reg_pairs[j].off,
 536                                                      reg_pairs[j].val);
 537                         }
 538                 }
 539
 540                 /* PMA RX lane registers configurations */
 541                 rx_ln_vals = init_data->rx_ln_vals[phy_t1][phy_t2][ssc];
 542                 if (rx_ln_vals) {
 543                         reg_pairs = rx_ln_vals->reg_pairs;
 544                         num_regs = rx_ln_vals->num_regs;
 545                         for (i = 0; i < num_lanes; i++) {
 546                                 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];
 547                                 for (j = 0; j < num_regs; j++)
 548                                         regmap_write(regmap, reg_pairs[j].off,
 549                                                      reg_pairs[j].val);
 550                         }
 551                 }
 552
 553                 reset_deassert_bulk(cdns_phy->phys[node].lnk_rst);
 554         }
 555
 556         /* Take the PHY out of reset */
 557         ret = reset_control_deassert(cdns_phy->phy_rst);
 558         if (ret)
 559                 return ret;
 560
 561         return 0;
 562 }
 563
 564 static int cdns_torrent_phy_probe(struct udevice *dev)
 565 {
 566         struct cdns_torrent_phy *cdns_phy = dev_get_priv(dev);
 567         int ret, subnodes = 0, node = 0, i;
 568         struct cdns_torrent_data *data;
 569         u32 total_num_lanes = 0;
 570         struct clk *clk;
 571         ofnode child;
 572         u32 phy_type;
 573
 574         cdns_phy->dev = dev;
 575
 576         /* Get init data for this phy  */
 577         data = (struct cdns_torrent_data *)dev_get_driver_data(dev);
 578         cdns_phy->init_data = data;
 579
 580         cdns_phy->phy_rst = devm_reset_control_get_by_index(dev, 0);
 581         if (IS_ERR(cdns_phy->phy_rst)) {
 582                 dev_err(dev, "failed to get reset\n");
 583                 return PTR_ERR(cdns_phy->phy_rst);
 584         }
 585
 586         clk = devm_clk_get(dev, "refclk");
 587         if (IS_ERR(clk)) {
 588                 dev_err(dev, "phy ref clock not found\n");
 589                 return PTR_ERR(clk);
 590         }
 591
 592         ret = clk_prepare_enable(clk);
 593         if (ret) {
 594                 dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
 595                 return ret;
 596         }
 597
 598         cdns_phy->sd_base = devfdt_remap_addr_index(dev, 0);
 599         if (IS_ERR(cdns_phy->sd_base))
 600                 return PTR_ERR(cdns_phy->sd_base);
 601         devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&cdns_phy->size);
 602
 603         dev_for_each_subnode(child, dev)
 604                 subnodes++;
 605         if (subnodes == 0) {
 606                 dev_err(dev, "No available link subnodes found\n");
 607                 return -EINVAL;
 608         }
 609         ret = cdns_torrent_regmap_init(cdns_phy);
 610         if (ret)
 611                 return ret;
 612
 613         ret = cdns_torrent_regfield_init(cdns_phy);
 614         if (ret)
 615                 return ret;
 616
 617         /* Going through all the available subnodes or children*/
 618         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
 619                 /* PHY subnode name must be a 'link' */
 620                 if (!ofnode_name_eq(child, "link"))
 621                         continue;
 622                 cdns_phy->phys[node].lnk_rst =
 623                                 devm_reset_bulk_get_by_node(dev, child);
 624                 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {
 625                         dev_err(dev, "%s: failed to get reset\n",
 626                                 ofnode_get_name(child));
 627                         ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);
 628                         goto put_lnk_rst;
 629                 }
 630
 631                 if (ofnode_read_u32(child, "reg",
 632                                     &cdns_phy->phys[node].mlane)) {
 633                         dev_err(dev, "%s: No \"reg \" - property.\n",
 634                                 ofnode_get_name(child));
 635                         ret = -EINVAL;
 636                         goto put_child;
 637                 }
 638
 639                 if (ofnode_read_u32(child, "cdns,phy-type", &phy_type)) {
 640                         dev_err(dev, "%s: No \"cdns,phy-type \" - property.\n",
 641                                 ofnode_get_name(child));
 642                         ret = -EINVAL;
 643                         goto put_child;
 644                 }
 645
 646                 switch (phy_type) {
 647                 case PHY_TYPE_PCIE:
 648                         cdns_phy->phys[node].phy_type = TYPE_PCIE;
 649                         break;
 650                 case PHY_TYPE_DP:
 651                         cdns_phy->phys[node].phy_type = TYPE_DP;
 652                         break;
 653                 case PHY_TYPE_SGMII:
 654                         cdns_phy->phys[node].phy_type = TYPE_SGMII;
 655                         break;
 656                 case PHY_TYPE_QSGMII:
 657                         cdns_phy->phys[node].phy_type = TYPE_QSGMII;
 658                         break;
 659                 case PHY_TYPE_USB3:
 660                         cdns_phy->phys[node].phy_type = TYPE_USB;
 661                         break;
 662                 default:
 663                         dev_err(dev, "Unsupported protocol\n");
 664                         ret = -EINVAL;
 665                         goto put_child;
 666                 }
 667
 668                 if (ofnode_read_u32(child, "cdns,num-lanes",
 669                                     &cdns_phy->phys[node].num_lanes)) {
 670                         dev_err(dev, "%s: No \"cdns,num-lanes \" - property.\n",
 671                                 ofnode_get_name(child));
 672                         ret = -EINVAL;
 673                         goto put_child;
 674                 }
 675
 676                 total_num_lanes += cdns_phy->phys[node].num_lanes;
 677
 678                 /* Get SSC mode */
 679                 ofnode_read_u32(child, "cdns,ssc-mode",
 680                                 &cdns_phy->phys[node].ssc_mode);
 681                 node++;
 682         }
 683
 684         cdns_phy->nsubnodes = node;
 685
 686         if (total_num_lanes > MAX_NUM_LANES) {
 687                 dev_err(dev, "Invalid lane configuration\n");
 688                 goto put_lnk_rst;
 689         }
 690
 691         if (cdns_phy->nsubnodes > 1) {
 692                 ret = cdns_torrent_phy_configure_multilink(cdns_phy);
 693                 if (ret)
 694                         goto put_lnk_rst;
 695         }
 696
 697         reset_control_deassert(cdns_phy->phy_rst);
 698         return 0;
 699
 700 put_child:
 701         node++;
 702 put_lnk_rst:
 703         for (i = 0; i < node; i++)
 704                 reset_release_bulk(cdns_phy->phys[i].lnk_rst);
 705         return ret;
 706 }
 707
 708 static int cdns_torrent_phy_on(struct phy *gphy)
 709 {
 710         struct cdns_torrent_inst *inst = phy_get_drvdata(gphy);
 711         struct cdns_torrent_phy *cdns_phy = dev_get_priv(gphy->dev);
 712         u32 read_val;
 713         int ret;
 714
 715         if (cdns_phy->nsubnodes == 1) {
 716                 /* Take the PHY lane group out of reset */
 717                 reset_deassert_bulk(inst->lnk_rst);
 718
 719                 /* Take the PHY out of reset */
 720                 ret = reset_control_deassert(cdns_phy->phy_rst);
 721                 if (ret)
 722                         return ret;
 723         }
 724
 725         /*
 726          * Wait for cmn_ready assertion
 727          * PHY_PMA_CMN_CTRL1[0] == 1
 728          */
 729         ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,
 730                                              read_val, read_val, 1000,
 731                                              PLL_LOCK_TIMEOUT);
 732         if (ret) {
 733                 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");
 734                 return ret;
 735         }
 736         mdelay(10);
 737
 738         return 0;
 739 }
 740
 741 static int cdns_torrent_phy_init(struct phy *phy)
 742 {
 743         struct cdns_torrent_phy *cdns_phy = dev_get_priv(phy->dev);
 744         const struct cdns_torrent_data *init_data = cdns_phy->init_data;
 745         struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;
 746         struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;
 747         struct cdns_torrent_inst *inst = phy_get_drvdata(phy);
 748         enum cdns_torrent_phy_type phy_type = inst->phy_type;
 749         enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;
 750         struct cdns_torrent_vals *pcs_cmn_vals;
 751         struct cdns_reg_pairs *reg_pairs;
 752         struct regmap *regmap;
 753         u32 num_regs;
 754         int i, j;
 755
 756         if (cdns_phy->nsubnodes > 1)
 757                 return 0;
 758
 759         /**
 760          * Spread spectrum generation is not required or supported
 761          * for SGMII/QSGMII
 762          */
 763         if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII)
 764                 ssc = NO_SSC;
 765
 766         /* PHY configuration specific registers for single link */
 767         link_cmn_vals = init_data->link_cmn_vals[phy_type][TYPE_NONE][ssc];
 768         if (link_cmn_vals) {
 769                 reg_pairs = link_cmn_vals->reg_pairs;
 770                 num_regs = link_cmn_vals->num_regs;
 771                 regmap = cdns_phy->regmap_common_cdb;
 772
 773                 /**
 774                  * First array value in link_cmn_vals must be of
 775                  * PHY_PLL_CFG register
 776                  */
 777                 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);
 778
 779                 for (i = 1; i < num_regs; i++)
 780                         regmap_write(regmap, reg_pairs[i].off,
 781                                      reg_pairs[i].val);
 782         }
 783
 784         xcvr_diag_vals = init_data->xcvr_diag_vals[phy_type][TYPE_NONE][ssc];
 785         if (xcvr_diag_vals) {
 786                 reg_pairs = xcvr_diag_vals->reg_pairs;
 787                 num_regs = xcvr_diag_vals->num_regs;
 788                 for (i = 0; i < inst->num_lanes; i++) {
 789                         regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
 790                         for (j = 0; j < num_regs; j++)
 791                                 regmap_write(regmap, reg_pairs[j].off,
 792                                              reg_pairs[j].val);
 793                 }
 794         }
 795
 796         /* PHY PCS common registers configurations */
 797         pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
 798         if (pcs_cmn_vals) {
 799                 reg_pairs = pcs_cmn_vals->reg_pairs;
 800                 num_regs = pcs_cmn_vals->num_regs;
 801                 regmap = cdns_phy->regmap_phy_pcs_common_cdb;
 802                 for (i = 0; i < num_regs; i++)
 803                         regmap_write(regmap, reg_pairs[i].off,
 804                                      reg_pairs[i].val);
 805         }
 806
 807         /* PMA common registers configurations */
 808         cmn_vals = init_data->cmn_vals[phy_type][TYPE_NONE][ssc];
 809         if (cmn_vals) {
 810                 reg_pairs = cmn_vals->reg_pairs;
 811                 num_regs = cmn_vals->num_regs;
 812                 regmap = cdns_phy->regmap_common_cdb;
 813                 for (i = 0; i < num_regs; i++)
 814                         regmap_write(regmap, reg_pairs[i].off,
 815                                      reg_pairs[i].val);
 816         }
 817
 818         /* PMA TX lane registers configurations */
 819         tx_ln_vals = init_data->tx_ln_vals[phy_type][TYPE_NONE][ssc];
 820         if (tx_ln_vals) {
 821                 reg_pairs = tx_ln_vals->reg_pairs;
 822                 num_regs = tx_ln_vals->num_regs;
 823                 for (i = 0; i < inst->num_lanes; i++) {
 824                         regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];
 825                         for (j = 0; j < num_regs; j++)
 826                                 regmap_write(regmap, reg_pairs[j].off,
 827                                              reg_pairs[j].val);
 828                 }
 829         }
 830
 831         /* PMA RX lane registers configurations */
 832         rx_ln_vals = init_data->rx_ln_vals[phy_type][TYPE_NONE][ssc];
 833         if (rx_ln_vals) {
 834                 reg_pairs = rx_ln_vals->reg_pairs;
 835                 num_regs = rx_ln_vals->num_regs;
 836                 for (i = 0; i < inst->num_lanes; i++) {
 837                         regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];
 838                         for (j = 0; j < num_regs; j++)
 839                                 regmap_write(regmap, reg_pairs[j].off,
 840                                              reg_pairs[j].val);
 841                 }
 842         }
 843
 844         return 0;
 845 }
 846
 847 static int cdns_torrent_phy_off(struct phy *gphy)
 848 {
 849         struct cdns_torrent_inst *inst = phy_get_drvdata(gphy);
 850         struct cdns_torrent_phy *cdns_phy = dev_get_priv(gphy->dev);
 851         int ret;
 852
 853         if (cdns_phy->nsubnodes != 1)
 854                 return 0;
 855
 856         ret = reset_control_assert(cdns_phy->phy_rst);
 857         if (ret)
 858                 return ret;
 859
 860         return reset_assert_bulk(inst->lnk_rst);
 861 }
 862
 863 static int cdns_torrent_phy_remove(struct udevice *dev)
 864 {
 865         struct cdns_torrent_phy *cdns_phy = dev_get_priv(dev);
 866         int i;
 867
 868         reset_control_assert(cdns_phy->phy_rst);
 869         for (i = 0; i < cdns_phy->nsubnodes; i++)
 870                 reset_release_bulk(cdns_phy->phys[i].lnk_rst);
 871
 872         return 0;
 873 }
 874
 875 /* USB and SGMII/QSGMII link configuration */
 876 static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {
 877         {0x0002, PHY_PLL_CFG},
 878         {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},
 879         {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
 880 };
 881
 882 static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {
 883         {0x0000, XCVR_DIAG_HSCLK_SEL},
 884         {0x0001, XCVR_DIAG_HSCLK_DIV},
 885         {0x0041, XCVR_DIAG_PLLDRC_CTRL}
 886 };
 887
 888 static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {
 889         {0x0011, XCVR_DIAG_HSCLK_SEL},
 890         {0x0003, XCVR_DIAG_HSCLK_DIV},
 891         {0x009B, XCVR_DIAG_PLLDRC_CTRL}
 892 };
 893
 894 static struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {
 895         .reg_pairs = usb_sgmii_link_cmn_regs,
 896         .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),
 897 };
 898
 899 static struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {
 900         .reg_pairs = usb_sgmii_xcvr_diag_ln_regs,
 901         .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),
 902 };
 903
 904 static struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {
 905         .reg_pairs = sgmii_usb_xcvr_diag_ln_regs,
 906         .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),
 907 };
 908
 909 /* PCIe and USB Unique SSC link configuration */
 910 static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {
 911         {0x0003, PHY_PLL_CFG},
 912         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
 913         {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
 914         {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}
 915 };
 916
 917 static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {
 918         {0x0000, XCVR_DIAG_HSCLK_SEL},
 919         {0x0001, XCVR_DIAG_HSCLK_DIV},
 920         {0x0012, XCVR_DIAG_PLLDRC_CTRL}
 921 };
 922
 923 static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {
 924         {0x0011, XCVR_DIAG_HSCLK_SEL},
 925         {0x0001, XCVR_DIAG_HSCLK_DIV},
 926         {0x00C9, XCVR_DIAG_PLLDRC_CTRL}
 927 };
 928
 929 static struct cdns_torrent_vals pcie_usb_link_cmn_vals = {
 930         .reg_pairs = pcie_usb_link_cmn_regs,
 931         .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),
 932 };
 933
 934 static struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {
 935         .reg_pairs = pcie_usb_xcvr_diag_ln_regs,
 936         .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),
 937 };
 938
 939 static struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {
 940         .reg_pairs = usb_pcie_xcvr_diag_ln_regs,
 941         .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),
 942 };
 943
 944 /* USB 100 MHz Ref clk, internal SSC */
 945 static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {
 946         {0x0004, CMN_PLL0_DSM_DIAG_M0},
 947         {0x0004, CMN_PLL0_DSM_DIAG_M1},
 948         {0x0004, CMN_PLL1_DSM_DIAG_M0},
 949         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
 950         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
 951         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
 952         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
 953         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
 954         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
 955         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
 956         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
 957         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
 958         {0x0064, CMN_PLL0_INTDIV_M0},
 959         {0x0050, CMN_PLL0_INTDIV_M1},
 960         {0x0064, CMN_PLL1_INTDIV_M0},
 961         {0x0002, CMN_PLL0_FRACDIVH_M0},
 962         {0x0002, CMN_PLL0_FRACDIVH_M1},
 963         {0x0002, CMN_PLL1_FRACDIVH_M0},
 964         {0x0044, CMN_PLL0_HIGH_THR_M0},
 965         {0x0036, CMN_PLL0_HIGH_THR_M1},
 966         {0x0044, CMN_PLL1_HIGH_THR_M0},
 967         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
 968         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
 969         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
 970         {0x0001, CMN_PLL0_SS_CTRL1_M0},
 971         {0x0001, CMN_PLL0_SS_CTRL1_M1},
 972         {0x0001, CMN_PLL1_SS_CTRL1_M0},
 973         {0x011B, CMN_PLL0_SS_CTRL2_M0},
 974         {0x011B, CMN_PLL0_SS_CTRL2_M1},
 975         {0x011B, CMN_PLL1_SS_CTRL2_M0},
 976         {0x006E, CMN_PLL0_SS_CTRL3_M0},
 977         {0x0058, CMN_PLL0_SS_CTRL3_M1},
 978         {0x006E, CMN_PLL1_SS_CTRL3_M0},
 979         {0x000E, CMN_PLL0_SS_CTRL4_M0},
 980         {0x0012, CMN_PLL0_SS_CTRL4_M1},
 981         {0x000E, CMN_PLL1_SS_CTRL4_M0},
 982         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
 983         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
 984         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
 985         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
 986         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
 987         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
 988         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
 989         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
 990         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
 991         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
 992         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
 993         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
 994         {0x007F, CMN_TXPUCAL_TUNE},
 995         {0x007F, CMN_TXPDCAL_TUNE}
 996 };
 997
 998 static struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {
 999         .reg_pairs = usb_100_int_ssc_cmn_regs,
1000         .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),
1001 };
1002
1003 /* Single USB link configuration */
1004 static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {
1005         {0x0000, PHY_PLL_CFG},
1006         {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}
1007 };
1008
1009 static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {
1010         {0x0000, XCVR_DIAG_HSCLK_SEL},
1011         {0x0001, XCVR_DIAG_HSCLK_DIV},
1012         {0x0041, XCVR_DIAG_PLLDRC_CTRL}
1013 };
1014
1015 static struct cdns_torrent_vals sl_usb_link_cmn_vals = {
1016         .reg_pairs = sl_usb_link_cmn_regs,
1017         .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),
1018 };
1019
1020 static struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {
1021         .reg_pairs = sl_usb_xcvr_diag_ln_regs,
1022         .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),
1023 };
1024
1025 /* USB PHY PCS common configuration */
1026 static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {
1027         {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},
1028         {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},
1029         {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}
1030 };
1031
1032 static struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {
1033         .reg_pairs = usb_phy_pcs_cmn_regs,
1034         .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),
1035 };
1036
1037 /* USB 100 MHz Ref clk, no SSC */
1038 static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {
1039         {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1040         {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1041         {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1042         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1043         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
1044         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1045         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
1046 };
1047
1048 static struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {
1049         .reg_pairs = sl_usb_100_no_ssc_cmn_regs,
1050         .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),
1051 };
1052
1053 static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {
1054         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1055         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},
1056         {0x007F, CMN_TXPUCAL_TUNE},
1057         {0x007F, CMN_TXPDCAL_TUNE}
1058 };
1059
1060 static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {
1061         {0x02FF, TX_PSC_A0},
1062         {0x06AF, TX_PSC_A1},
1063         {0x06AE, TX_PSC_A2},
1064         {0x06AE, TX_PSC_A3},
1065         {0x2A82, TX_TXCC_CTRL},
1066         {0x0014, TX_TXCC_CPOST_MULT_01},
1067         {0x0003, XCVR_DIAG_PSC_OVRD}
1068 };
1069
1070 static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {
1071         {0x0D1D, RX_PSC_A0},
1072         {0x0D1D, RX_PSC_A1},
1073         {0x0D00, RX_PSC_A2},
1074         {0x0500, RX_PSC_A3},
1075         {0x0013, RX_SIGDET_HL_FILT_TMR},
1076         {0x0000, RX_REE_GCSM1_CTRL},
1077         {0x0C02, RX_REE_ATTEN_THR},
1078         {0x0330, RX_REE_SMGM_CTRL1},
1079         {0x0300, RX_REE_SMGM_CTRL2},
1080         {0x0019, RX_REE_TAP1_CLIP},
1081         {0x0019, RX_REE_TAP2TON_CLIP},
1082         {0x1004, RX_DIAG_SIGDET_TUNE},
1083         {0x00F9, RX_DIAG_NQST_CTRL},
1084         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1085         {0x0002, RX_DIAG_DFE_AMP_TUNE_3},
1086         {0x0000, RX_DIAG_PI_CAP},
1087         {0x0031, RX_DIAG_PI_RATE},
1088         {0x0001, RX_DIAG_ACYA},
1089         {0x018C, RX_CDRLF_CNFG},
1090         {0x0003, RX_CDRLF_CNFG3}
1091 };
1092
1093 static struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {
1094         .reg_pairs = usb_100_no_ssc_cmn_regs,
1095         .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),
1096 };
1097
1098 static struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {
1099         .reg_pairs = usb_100_no_ssc_tx_ln_regs,
1100         .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),
1101 };
1102
1103 static struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {
1104         .reg_pairs = usb_100_no_ssc_rx_ln_regs,
1105         .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),
1106 };
1107
1108 /* Single link USB, 100 MHz Ref clk, internal SSC */
1109 static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {
1110         {0x0004, CMN_PLL0_DSM_DIAG_M0},
1111         {0x0004, CMN_PLL1_DSM_DIAG_M0},
1112         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1113         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1114         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1115         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1116         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1117         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1118         {0x0064, CMN_PLL0_INTDIV_M0},
1119         {0x0064, CMN_PLL1_INTDIV_M0},
1120         {0x0002, CMN_PLL0_FRACDIVH_M0},
1121         {0x0002, CMN_PLL1_FRACDIVH_M0},
1122         {0x0044, CMN_PLL0_HIGH_THR_M0},
1123         {0x0044, CMN_PLL1_HIGH_THR_M0},
1124         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1125         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1126         {0x0001, CMN_PLL0_SS_CTRL1_M0},
1127         {0x0001, CMN_PLL1_SS_CTRL1_M0},
1128         {0x011B, CMN_PLL0_SS_CTRL2_M0},
1129         {0x011B, CMN_PLL1_SS_CTRL2_M0},
1130         {0x006E, CMN_PLL0_SS_CTRL3_M0},
1131         {0x006E, CMN_PLL1_SS_CTRL3_M0},
1132         {0x000E, CMN_PLL0_SS_CTRL4_M0},
1133         {0x000E, CMN_PLL1_SS_CTRL4_M0},
1134         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1135         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1136         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1137         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1138         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1139         {0x0003, CMN_PLL1_VCOCAL_TCTRL},
1140         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1141         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1142         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1143         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1144         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1145         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1146         {0x8200, CMN_CDIAG_CDB_PWRI_OVRD},
1147         {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}
1148 };
1149
1150 static struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {
1151         .reg_pairs = sl_usb_100_int_ssc_cmn_regs,
1152         .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),
1153 };
1154
1155 /* PCIe and SGMII/QSGMII Unique SSC link configuration */
1156 static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {
1157         {0x0003, PHY_PLL_CFG},
1158         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},
1159         {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},
1160         {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}
1161 };
1162
1163 static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {
1164         {0x0000, XCVR_DIAG_HSCLK_SEL},
1165         {0x0001, XCVR_DIAG_HSCLK_DIV},
1166         {0x0012, XCVR_DIAG_PLLDRC_CTRL}
1167 };
1168
1169 static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {
1170         {0x0011, XCVR_DIAG_HSCLK_SEL},
1171         {0x0003, XCVR_DIAG_HSCLK_DIV},
1172         {0x009B, XCVR_DIAG_PLLDRC_CTRL}
1173 };
1174
1175 static struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {
1176         .reg_pairs = pcie_sgmii_link_cmn_regs,
1177         .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),
1178 };
1179
1180 static struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {
1181         .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,
1182         .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),
1183 };
1184
1185 static struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {
1186         .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,
1187         .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),
1188 };
1189
1190 /* SGMII 100 MHz Ref clk, no SSC */
1191 static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {
1192         {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1193         {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1194         {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1195         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1196         {0x0003, CMN_PLL1_VCOCAL_TCTRL}
1197 };
1198
1199 static struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {
1200         .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,
1201         .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),
1202 };
1203
1204 static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {
1205         {0x007F, CMN_TXPUCAL_TUNE},
1206         {0x007F, CMN_TXPDCAL_TUNE}
1207 };
1208
1209 static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {
1210         {0x00F3, TX_PSC_A0},
1211         {0x04A2, TX_PSC_A2},
1212         {0x04A2, TX_PSC_A3},
1213         {0x0000, TX_TXCC_CPOST_MULT_00},
1214         {0x00B3, DRV_DIAG_TX_DRV}
1215 };
1216
1217 static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {
1218         {0x00F3, TX_PSC_A0},
1219         {0x04A2, TX_PSC_A2},
1220         {0x04A2, TX_PSC_A3},
1221         {0x0000, TX_TXCC_CPOST_MULT_00},
1222         {0x00B3, DRV_DIAG_TX_DRV},
1223         {0x4000, XCVR_DIAG_RXCLK_CTRL},
1224 };
1225
1226 static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {
1227         {0x091D, RX_PSC_A0},
1228         {0x0900, RX_PSC_A2},
1229         {0x0100, RX_PSC_A3},
1230         {0x03C7, RX_REE_GCSM1_EQENM_PH1},
1231         {0x01C7, RX_REE_GCSM1_EQENM_PH2},
1232         {0x0000, RX_DIAG_DFE_CTRL},
1233         {0x0019, RX_REE_TAP1_CLIP},
1234         {0x0019, RX_REE_TAP2TON_CLIP},
1235         {0x0098, RX_DIAG_NQST_CTRL},
1236         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1237         {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
1238         {0x0000, RX_DIAG_PI_CAP},
1239         {0x0010, RX_DIAG_PI_RATE},
1240         {0x0001, RX_DIAG_ACYA},
1241         {0x018C, RX_CDRLF_CNFG},
1242 };
1243
1244 static struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {
1245         .reg_pairs = sgmii_100_no_ssc_cmn_regs,
1246         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),
1247 };
1248
1249 static struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {
1250         .reg_pairs = sgmii_100_no_ssc_tx_ln_regs,
1251         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),
1252 };
1253
1254 static struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {
1255         .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,
1256         .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),
1257 };
1258
1259 static struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {
1260         .reg_pairs = sgmii_100_no_ssc_rx_ln_regs,
1261         .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),
1262 };
1263
1264 /* SGMII 100 MHz Ref clk, internal SSC */
1265 static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {
1266         {0x0004, CMN_PLL0_DSM_DIAG_M0},
1267         {0x0004, CMN_PLL0_DSM_DIAG_M1},
1268         {0x0004, CMN_PLL1_DSM_DIAG_M0},
1269         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1270         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1271         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1272         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1273         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1274         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1275         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1276         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1277         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1278         {0x0064, CMN_PLL0_INTDIV_M0},
1279         {0x0050, CMN_PLL0_INTDIV_M1},
1280         {0x0064, CMN_PLL1_INTDIV_M0},
1281         {0x0002, CMN_PLL0_FRACDIVH_M0},
1282         {0x0002, CMN_PLL0_FRACDIVH_M1},
1283         {0x0002, CMN_PLL1_FRACDIVH_M0},
1284         {0x0044, CMN_PLL0_HIGH_THR_M0},
1285         {0x0036, CMN_PLL0_HIGH_THR_M1},
1286         {0x0044, CMN_PLL1_HIGH_THR_M0},
1287         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1288         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1289         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1290         {0x0001, CMN_PLL0_SS_CTRL1_M0},
1291         {0x0001, CMN_PLL0_SS_CTRL1_M1},
1292         {0x0001, CMN_PLL1_SS_CTRL1_M0},
1293         {0x011B, CMN_PLL0_SS_CTRL2_M0},
1294         {0x011B, CMN_PLL0_SS_CTRL2_M1},
1295         {0x011B, CMN_PLL1_SS_CTRL2_M0},
1296         {0x006E, CMN_PLL0_SS_CTRL3_M0},
1297         {0x0058, CMN_PLL0_SS_CTRL3_M1},
1298         {0x006E, CMN_PLL1_SS_CTRL3_M0},
1299         {0x000E, CMN_PLL0_SS_CTRL4_M0},
1300         {0x0012, CMN_PLL0_SS_CTRL4_M1},
1301         {0x000E, CMN_PLL1_SS_CTRL4_M0},
1302         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1303         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1304         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1305         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1306         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1307         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1308         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1309         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1310         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1311         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1312         {0x007F, CMN_TXPUCAL_TUNE},
1313         {0x007F, CMN_TXPDCAL_TUNE}
1314 };
1315
1316 static struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {
1317         .reg_pairs = sgmii_100_int_ssc_cmn_regs,
1318         .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),
1319 };
1320
1321 /* QSGMII 100 MHz Ref clk, no SSC */
1322 static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {
1323         {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1324         {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1325         {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},
1326         {0x0003, CMN_PLL0_VCOCAL_TCTRL},
1327         {0x0003, CMN_PLL1_VCOCAL_TCTRL}
1328 };
1329
1330 static struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {
1331         .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,
1332         .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),
1333 };
1334
1335 static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {
1336         {0x007F, CMN_TXPUCAL_TUNE},
1337         {0x007F, CMN_TXPDCAL_TUNE}
1338 };
1339
1340 static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {
1341         {0x00F3, TX_PSC_A0},
1342         {0x04A2, TX_PSC_A2},
1343         {0x04A2, TX_PSC_A3},
1344         {0x0000, TX_TXCC_CPOST_MULT_00},
1345         {0x0011, TX_TXCC_MGNFS_MULT_100},
1346         {0x0003, DRV_DIAG_TX_DRV}
1347 };
1348
1349 static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {
1350         {0x00F3, TX_PSC_A0},
1351         {0x04A2, TX_PSC_A2},
1352         {0x04A2, TX_PSC_A3},
1353         {0x0000, TX_TXCC_CPOST_MULT_00},
1354         {0x0011, TX_TXCC_MGNFS_MULT_100},
1355         {0x0003, DRV_DIAG_TX_DRV},
1356         {0x4000, XCVR_DIAG_RXCLK_CTRL},
1357 };
1358
1359 static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {
1360         {0x091D, RX_PSC_A0},
1361         {0x0900, RX_PSC_A2},
1362         {0x0100, RX_PSC_A3},
1363         {0x03C7, RX_REE_GCSM1_EQENM_PH1},
1364         {0x01C7, RX_REE_GCSM1_EQENM_PH2},
1365         {0x0000, RX_DIAG_DFE_CTRL},
1366         {0x0019, RX_REE_TAP1_CLIP},
1367         {0x0019, RX_REE_TAP2TON_CLIP},
1368         {0x0098, RX_DIAG_NQST_CTRL},
1369         {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
1370         {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
1371         {0x0000, RX_DIAG_PI_CAP},
1372         {0x0010, RX_DIAG_PI_RATE},
1373         {0x0001, RX_DIAG_ACYA},
1374         {0x018C, RX_CDRLF_CNFG},
1375 };
1376
1377 static struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {
1378         .reg_pairs = qsgmii_100_no_ssc_cmn_regs,
1379         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),
1380 };
1381
1382 static struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {
1383         .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,
1384         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),
1385 };
1386
1387 static struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {
1388         .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,
1389         .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),
1390 };
1391
1392 static struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {
1393         .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,
1394         .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),
1395 };
1396
1397 /* QSGMII 100 MHz Ref clk, internal SSC */
1398 static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {
1399         {0x0004, CMN_PLL0_DSM_DIAG_M0},
1400         {0x0004, CMN_PLL0_DSM_DIAG_M1},
1401         {0x0004, CMN_PLL1_DSM_DIAG_M0},
1402         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1403         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1404         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1405         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1406         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1407         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1408         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1409         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1410         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1411         {0x0064, CMN_PLL0_INTDIV_M0},
1412         {0x0050, CMN_PLL0_INTDIV_M1},
1413         {0x0064, CMN_PLL1_INTDIV_M0},
1414         {0x0002, CMN_PLL0_FRACDIVH_M0},
1415         {0x0002, CMN_PLL0_FRACDIVH_M1},
1416         {0x0002, CMN_PLL1_FRACDIVH_M0},
1417         {0x0044, CMN_PLL0_HIGH_THR_M0},
1418         {0x0036, CMN_PLL0_HIGH_THR_M1},
1419         {0x0044, CMN_PLL1_HIGH_THR_M0},
1420         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1421         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1422         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1423         {0x0001, CMN_PLL0_SS_CTRL1_M0},
1424         {0x0001, CMN_PLL0_SS_CTRL1_M1},
1425         {0x0001, CMN_PLL1_SS_CTRL1_M0},
1426         {0x011B, CMN_PLL0_SS_CTRL2_M0},
1427         {0x011B, CMN_PLL0_SS_CTRL2_M1},
1428         {0x011B, CMN_PLL1_SS_CTRL2_M0},
1429         {0x006E, CMN_PLL0_SS_CTRL3_M0},
1430         {0x0058, CMN_PLL0_SS_CTRL3_M1},
1431         {0x006E, CMN_PLL1_SS_CTRL3_M0},
1432         {0x000E, CMN_PLL0_SS_CTRL4_M0},
1433         {0x0012, CMN_PLL0_SS_CTRL4_M1},
1434         {0x000E, CMN_PLL1_SS_CTRL4_M0},
1435         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1436         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1437         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1438         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1439         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1440         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1441         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1442         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1443         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1444         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR},
1445         {0x007F, CMN_TXPUCAL_TUNE},
1446         {0x007F, CMN_TXPDCAL_TUNE}
1447 };
1448
1449 static struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {
1450         .reg_pairs = qsgmii_100_int_ssc_cmn_regs,
1451         .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),
1452 };
1453
1454 /* Single SGMII/QSGMII link configuration */
1455 static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {
1456         {0x0000, PHY_PLL_CFG},
1457         {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
1458 };
1459
1460 static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {
1461         {0x0000, XCVR_DIAG_HSCLK_SEL},
1462         {0x0003, XCVR_DIAG_HSCLK_DIV},
1463         {0x0013, XCVR_DIAG_PLLDRC_CTRL}
1464 };
1465
1466 static struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {
1467         .reg_pairs = sl_sgmii_link_cmn_regs,
1468         .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),
1469 };
1470
1471 static struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {
1472         .reg_pairs = sl_sgmii_xcvr_diag_ln_regs,
1473         .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),
1474 };
1475
1476 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */
1477 static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {
1478         {0x0004, CMN_PLL0_DSM_DIAG_M0},
1479         {0x0004, CMN_PLL0_DSM_DIAG_M1},
1480         {0x0004, CMN_PLL1_DSM_DIAG_M0},
1481         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1482         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1483         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1484         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1485         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1486         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1487         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1488         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1489         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1490         {0x0064, CMN_PLL0_INTDIV_M0},
1491         {0x0050, CMN_PLL0_INTDIV_M1},
1492         {0x0064, CMN_PLL1_INTDIV_M0},
1493         {0x0002, CMN_PLL0_FRACDIVH_M0},
1494         {0x0002, CMN_PLL0_FRACDIVH_M1},
1495         {0x0002, CMN_PLL1_FRACDIVH_M0},
1496         {0x0044, CMN_PLL0_HIGH_THR_M0},
1497         {0x0036, CMN_PLL0_HIGH_THR_M1},
1498         {0x0044, CMN_PLL1_HIGH_THR_M0},
1499         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1500         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1501         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1502         {0x0001, CMN_PLL0_SS_CTRL1_M0},
1503         {0x0001, CMN_PLL0_SS_CTRL1_M1},
1504         {0x0001, CMN_PLL1_SS_CTRL1_M0},
1505         {0x011B, CMN_PLL0_SS_CTRL2_M0},
1506         {0x011B, CMN_PLL0_SS_CTRL2_M1},
1507         {0x011B, CMN_PLL1_SS_CTRL2_M0},
1508         {0x006E, CMN_PLL0_SS_CTRL3_M0},
1509         {0x0058, CMN_PLL0_SS_CTRL3_M1},
1510         {0x006E, CMN_PLL1_SS_CTRL3_M0},
1511         {0x000E, CMN_PLL0_SS_CTRL4_M0},
1512         {0x0012, CMN_PLL0_SS_CTRL4_M1},
1513         {0x000E, CMN_PLL1_SS_CTRL4_M0},
1514         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1515         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1516         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1517         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1518         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1519         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1520         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1521         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1522         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1523         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
1524 };
1525
1526 static struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {
1527         .reg_pairs = pcie_100_int_ssc_cmn_regs,
1528         .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),
1529 };
1530
1531 /* Single link PCIe, 100 MHz Ref clk, internal SSC */
1532 static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {
1533         {0x0004, CMN_PLL0_DSM_DIAG_M0},
1534         {0x0004, CMN_PLL0_DSM_DIAG_M1},
1535         {0x0004, CMN_PLL1_DSM_DIAG_M0},
1536         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},
1537         {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},
1538         {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},
1539         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},
1540         {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},
1541         {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},
1542         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},
1543         {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},
1544         {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},
1545         {0x0064, CMN_PLL0_INTDIV_M0},
1546         {0x0050, CMN_PLL0_INTDIV_M1},
1547         {0x0050, CMN_PLL1_INTDIV_M0},
1548         {0x0002, CMN_PLL0_FRACDIVH_M0},
1549         {0x0002, CMN_PLL0_FRACDIVH_M1},
1550         {0x0002, CMN_PLL1_FRACDIVH_M0},
1551         {0x0044, CMN_PLL0_HIGH_THR_M0},
1552         {0x0036, CMN_PLL0_HIGH_THR_M1},
1553         {0x0036, CMN_PLL1_HIGH_THR_M0},
1554         {0x0002, CMN_PDIAG_PLL0_CTRL_M0},
1555         {0x0002, CMN_PDIAG_PLL0_CTRL_M1},
1556         {0x0002, CMN_PDIAG_PLL1_CTRL_M0},
1557         {0x0001, CMN_PLL0_SS_CTRL1_M0},
1558         {0x0001, CMN_PLL0_SS_CTRL1_M1},
1559         {0x0001, CMN_PLL1_SS_CTRL1_M0},
1560         {0x011B, CMN_PLL0_SS_CTRL2_M0},
1561         {0x011B, CMN_PLL0_SS_CTRL2_M1},
1562         {0x011B, CMN_PLL1_SS_CTRL2_M0},
1563         {0x006E, CMN_PLL0_SS_CTRL3_M0},
1564         {0x0058, CMN_PLL0_SS_CTRL3_M1},
1565         {0x0058, CMN_PLL1_SS_CTRL3_M0},
1566         {0x000E, CMN_PLL0_SS_CTRL4_M0},
1567         {0x0012, CMN_PLL0_SS_CTRL4_M1},
1568         {0x0012, CMN_PLL1_SS_CTRL4_M0},
1569         {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},
1570         {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},
1571         {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},
1572         {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},
1573         {0x00C7, CMN_PLL0_LOCK_REFCNT_START},
1574         {0x00C7, CMN_PLL1_LOCK_REFCNT_START},
1575         {0x00C7, CMN_PLL0_LOCK_PLLCNT_START},
1576         {0x00C7, CMN_PLL1_LOCK_PLLCNT_START},
1577         {0x0005, CMN_PLL0_LOCK_PLLCNT_THR},
1578         {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}
1579 };
1580
1581 static struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {
1582         .reg_pairs = sl_pcie_100_int_ssc_cmn_regs,
1583         .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),
1584 };
1585
1586 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */
1587 static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {
1588         {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},
1589         {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},
1590         {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}
1591 };
1592
1593 static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {
1594         {0x0019, RX_REE_TAP1_CLIP},
1595         {0x0019, RX_REE_TAP2TON_CLIP},
1596         {0x0001, RX_DIAG_ACYA}
1597 };
1598
1599 static struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {
1600         .reg_pairs = pcie_100_ext_no_ssc_cmn_regs,
1601         .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),
1602 };
1603
1604 static struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {
1605         .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,
1606         .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),
1607 };
1608
1609 static const struct cdns_torrent_data cdns_map_torrent = {
1610         .block_offset_shift = 0x2,
1611         .reg_offset_shift = 0x2,
1612         .link_cmn_vals = {
1613                 [TYPE_PCIE] = {
1614                         [TYPE_NONE] = {
1615                                 [NO_SSC] = NULL,
1616                                 [EXTERNAL_SSC] = NULL,
1617                                 [INTERNAL_SSC] = NULL,
1618                         },
1619                         [TYPE_SGMII] = {
1620                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1621                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1622                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1623                         },
1624                         [TYPE_QSGMII] = {
1625                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1626                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1627                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1628                         },
1629                         [TYPE_USB] = {
1630                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
1631                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1632                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1633                         },
1634                 },
1635                 [TYPE_SGMII] = {
1636                         [TYPE_NONE] = {
1637                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
1638                         },
1639                         [TYPE_PCIE] = {
1640                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1641                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1642                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1643                         },
1644                         [TYPE_USB] = {
1645                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1646                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1647                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1648                         },
1649                 },
1650                 [TYPE_QSGMII] = {
1651                         [TYPE_NONE] = {
1652                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
1653                         },
1654                         [TYPE_PCIE] = {
1655                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
1656                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1657                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
1658                         },
1659                         [TYPE_USB] = {
1660                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1661                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1662                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1663                         },
1664                 },
1665                 [TYPE_USB] = {
1666                         [TYPE_NONE] = {
1667                                 [NO_SSC] = &sl_usb_link_cmn_vals,
1668                                 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
1669                                 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
1670                         },
1671                         [TYPE_PCIE] = {
1672                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
1673                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1674                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
1675                         },
1676                         [TYPE_SGMII] = {
1677                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1678                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1679                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1680                         },
1681                         [TYPE_QSGMII] = {
1682                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
1683                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1684                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
1685                         },
1686                 },
1687         },
1688         .xcvr_diag_vals = {
1689                 [TYPE_PCIE] = {
1690                         [TYPE_NONE] = {
1691                                 [NO_SSC] = NULL,
1692                                 [EXTERNAL_SSC] = NULL,
1693                                 [INTERNAL_SSC] = NULL,
1694                         },
1695                         [TYPE_SGMII] = {
1696                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1697                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1698                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1699                         },
1700                         [TYPE_QSGMII] = {
1701                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1702                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1703                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
1704                         },
1705                         [TYPE_USB] = {
1706                                 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1707                                 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1708                                 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
1709                         },
1710                 },
1711                 [TYPE_SGMII] = {
1712                         [TYPE_NONE] = {
1713                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
1714                         },
1715                         [TYPE_PCIE] = {
1716                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1717                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1718                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1719                         },
1720                         [TYPE_USB] = {
1721                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1722                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1723                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1724                         },
1725                 },
1726                 [TYPE_QSGMII] = {
1727                         [TYPE_NONE] = {
1728                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
1729                         },
1730                         [TYPE_PCIE] = {
1731                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1732                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1733                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
1734                         },
1735                         [TYPE_USB] = {
1736                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1737                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1738                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
1739                         },
1740                 },
1741                 [TYPE_USB] = {
1742                         [TYPE_NONE] = {
1743                                 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
1744                                 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
1745                                 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
1746                         },
1747                         [TYPE_PCIE] = {
1748                                 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1749                                 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1750                                 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
1751                         },
1752                         [TYPE_SGMII] = {
1753                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1754                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1755                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1756                         },
1757                         [TYPE_QSGMII] = {
1758                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1759                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1760                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
1761                         },
1762                 },
1763         },
1764         .pcs_cmn_vals = {
1765                 [TYPE_USB] = {
1766                         [TYPE_NONE] = {
1767                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1768                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1769                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1770                         },
1771                         [TYPE_PCIE] = {
1772                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1773                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1774                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1775                         },
1776                         [TYPE_SGMII] = {
1777                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1778                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1779                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1780                         },
1781                         [TYPE_QSGMII] = {
1782                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
1783                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1784                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
1785                         },
1786                 },
1787         },
1788         .cmn_vals = {
1789                 [TYPE_PCIE] = {
1790                         [TYPE_NONE] = {
1791                                 [NO_SSC] = NULL,
1792                                 [EXTERNAL_SSC] = NULL,
1793                                 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
1794                         },
1795                         [TYPE_SGMII] = {
1796                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1797                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1798                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1799                         },
1800                         [TYPE_QSGMII] = {
1801                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1802                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1803                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1804                         },
1805                         [TYPE_USB] = {
1806                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
1807                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
1808                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
1809                         },
1810                 },
1811                 [TYPE_SGMII] = {
1812                         [TYPE_NONE] = {
1813                                 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
1814                         },
1815                         [TYPE_PCIE] = {
1816                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
1817                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1818                                 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
1819                         },
1820                         [TYPE_USB] = {
1821                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
1822                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1823                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
1824                         },
1825                 },
1826                 [TYPE_QSGMII] = {
1827                         [TYPE_NONE] = {
1828                                 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
1829                         },
1830                         [TYPE_PCIE] = {
1831                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1832                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1833                                 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
1834                         },
1835                         [TYPE_USB] = {
1836                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1837                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1838                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
1839                         },
1840                 },
1841                 [TYPE_USB] = {
1842                         [TYPE_NONE] = {
1843                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1844                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1845                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1846                         },
1847                         [TYPE_PCIE] = {
1848                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
1849                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
1850                                 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
1851                         },
1852                         [TYPE_SGMII] = {
1853                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1854                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1855                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1856                         },
1857                         [TYPE_QSGMII] = {
1858                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1859                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
1860                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
1861                         },
1862                 },
1863         },
1864         .tx_ln_vals = {
1865                 [TYPE_PCIE] = {
1866                         [TYPE_NONE] = {
1867                                 [NO_SSC] = NULL,
1868                                 [EXTERNAL_SSC] = NULL,
1869                                 [INTERNAL_SSC] = NULL,
1870                         },
1871                         [TYPE_SGMII] = {
1872                                 [NO_SSC] = NULL,
1873                                 [EXTERNAL_SSC] = NULL,
1874                                 [INTERNAL_SSC] = NULL,
1875                         },
1876                         [TYPE_QSGMII] = {
1877                                 [NO_SSC] = NULL,
1878                                 [EXTERNAL_SSC] = NULL,
1879                                 [INTERNAL_SSC] = NULL,
1880                         },
1881                         [TYPE_USB] = {
1882                                 [NO_SSC] = NULL,
1883                                 [EXTERNAL_SSC] = NULL,
1884                                 [INTERNAL_SSC] = NULL,
1885                         },
1886                 },
1887                 [TYPE_SGMII] = {
1888                         [TYPE_NONE] = {
1889                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1890                         },
1891                         [TYPE_PCIE] = {
1892                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1893                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1894                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1895                         },
1896                         [TYPE_USB] = {
1897                                 [NO_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1898                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1899                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_tx_ln_vals,
1900                         },
1901                 },
1902                 [TYPE_QSGMII] = {
1903                         [TYPE_NONE] = {
1904                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1905                         },
1906                         [TYPE_PCIE] = {
1907                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1908                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1909                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1910                         },
1911                         [TYPE_USB] = {
1912                                 [NO_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1913                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1914                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_tx_ln_vals,
1915                         },
1916                 },
1917                 [TYPE_USB] = {
1918                         [TYPE_NONE] = {
1919                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1920                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1921                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1922                         },
1923                         [TYPE_PCIE] = {
1924                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1925                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1926                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1927                         },
1928                         [TYPE_SGMII] = {
1929                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1930                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1931                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1932                         },
1933                         [TYPE_QSGMII] = {
1934                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
1935                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1936                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
1937                         },
1938                 },
1939         },
1940         .rx_ln_vals = {
1941                 [TYPE_PCIE] = {
1942                         [TYPE_NONE] = {
1943                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1944                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1945                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1946                         },
1947                         [TYPE_SGMII] = {
1948                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1949                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1950                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1951                         },
1952                         [TYPE_QSGMII] = {
1953                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1954                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1955                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1956                         },
1957                         [TYPE_USB] = {
1958                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1959                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1960                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
1961                         },
1962                 },
1963                 [TYPE_SGMII] = {
1964                         [TYPE_NONE] = {
1965                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1966                         },
1967                         [TYPE_PCIE] = {
1968                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1969                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1970                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1971                         },
1972                         [TYPE_USB] = {
1973                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1974                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1975                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
1976                         },
1977                 },
1978                 [TYPE_QSGMII] = {
1979                         [TYPE_NONE] = {
1980                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1981                         },
1982                         [TYPE_PCIE] = {
1983                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1984                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1985                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1986                         },
1987                         [TYPE_USB] = {
1988                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1989                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1990                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
1991                         },
1992                 },
1993                 [TYPE_USB] = {
1994                         [TYPE_NONE] = {
1995                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
1996                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
1997                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
1998                         },
1999                         [TYPE_PCIE] = {
2000                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2001                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2002                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2003                         },
2004                         [TYPE_SGMII] = {
2005                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2006                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2007                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2008                         },
2009                         [TYPE_QSGMII] = {
2010                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2011                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2012                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2013                         },
2014                 },
2015         },
2016 };
2017
2018 static const struct cdns_torrent_data ti_j721e_map_torrent = {
2019         .block_offset_shift = 0x0,
2020         .reg_offset_shift = 0x1,
2021         .link_cmn_vals = {
2022                 [TYPE_PCIE] = {
2023                         [TYPE_NONE] = {
2024                                 [NO_SSC] = NULL,
2025                                 [EXTERNAL_SSC] = NULL,
2026                                 [INTERNAL_SSC] = NULL,
2027                         },
2028                         [TYPE_SGMII] = {
2029                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2030                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2031                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2032                         },
2033                         [TYPE_QSGMII] = {
2034                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2035                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2036                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2037                         },
2038                         [TYPE_USB] = {
2039                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
2040                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2041                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2042                         },
2043                 },
2044                 [TYPE_SGMII] = {
2045                         [TYPE_NONE] = {
2046                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
2047                         },
2048                         [TYPE_PCIE] = {
2049                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2050                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2051                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2052                         },
2053                         [TYPE_USB] = {
2054                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2055                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2056                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2057                         },
2058                 },
2059                 [TYPE_QSGMII] = {
2060                         [TYPE_NONE] = {
2061                                 [NO_SSC] = &sl_sgmii_link_cmn_vals,
2062                         },
2063                         [TYPE_PCIE] = {
2064                                 [NO_SSC] = &pcie_sgmii_link_cmn_vals,
2065                                 [EXTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2066                                 [INTERNAL_SSC] = &pcie_sgmii_link_cmn_vals,
2067                         },
2068                         [TYPE_USB] = {
2069                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2070                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2071                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2072                         },
2073                 },
2074                 [TYPE_USB] = {
2075                         [TYPE_NONE] = {
2076                                 [NO_SSC] = &sl_usb_link_cmn_vals,
2077                                 [EXTERNAL_SSC] = &sl_usb_link_cmn_vals,
2078                                 [INTERNAL_SSC] = &sl_usb_link_cmn_vals,
2079                         },
2080                         [TYPE_PCIE] = {
2081                                 [NO_SSC] = &pcie_usb_link_cmn_vals,
2082                                 [EXTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2083                                 [INTERNAL_SSC] = &pcie_usb_link_cmn_vals,
2084                         },
2085                         [TYPE_SGMII] = {
2086                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2087                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2088                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2089                         },
2090                         [TYPE_QSGMII] = {
2091                                 [NO_SSC] = &usb_sgmii_link_cmn_vals,
2092                                 [EXTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2093                                 [INTERNAL_SSC] = &usb_sgmii_link_cmn_vals,
2094                         },
2095                 },
2096         },
2097         .xcvr_diag_vals = {
2098                 [TYPE_PCIE] = {
2099                         [TYPE_NONE] = {
2100                                 [NO_SSC] = NULL,
2101                                 [EXTERNAL_SSC] = NULL,
2102                                 [INTERNAL_SSC] = NULL,
2103                         },
2104                         [TYPE_SGMII] = {
2105                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2106                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2107                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2108                         },
2109                         [TYPE_QSGMII] = {
2110                                 [NO_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2111                                 [EXTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2112                                 [INTERNAL_SSC] = &pcie_sgmii_xcvr_diag_ln_vals,
2113                         },
2114                         [TYPE_USB] = {
2115                                 [NO_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2116                                 [EXTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2117                                 [INTERNAL_SSC] = &pcie_usb_xcvr_diag_ln_vals,
2118                         },
2119                 },
2120                 [TYPE_SGMII] = {
2121                         [TYPE_NONE] = {
2122                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
2123                         },
2124                         [TYPE_PCIE] = {
2125                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2126                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2127                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2128                         },
2129                         [TYPE_USB] = {
2130                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2131                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2132                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2133                         },
2134                 },
2135                 [TYPE_QSGMII] = {
2136                         [TYPE_NONE] = {
2137                                 [NO_SSC] = &sl_sgmii_xcvr_diag_ln_vals,
2138                         },
2139                         [TYPE_PCIE] = {
2140                                 [NO_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2141                                 [EXTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2142                                 [INTERNAL_SSC] = &sgmii_pcie_xcvr_diag_ln_vals,
2143                         },
2144                         [TYPE_USB] = {
2145                                 [NO_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2146                                 [EXTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2147                                 [INTERNAL_SSC] = &sgmii_usb_xcvr_diag_ln_vals,
2148                         },
2149                 },
2150                 [TYPE_USB] = {
2151                         [TYPE_NONE] = {
2152                                 [NO_SSC] = &sl_usb_xcvr_diag_ln_vals,
2153                                 [EXTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
2154                                 [INTERNAL_SSC] = &sl_usb_xcvr_diag_ln_vals,
2155                         },
2156                         [TYPE_PCIE] = {
2157                                 [NO_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2158                                 [EXTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2159                                 [INTERNAL_SSC] = &usb_pcie_xcvr_diag_ln_vals,
2160                         },
2161                         [TYPE_SGMII] = {
2162                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2163                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2164                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2165                         },
2166                         [TYPE_QSGMII] = {
2167                                 [NO_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2168                                 [EXTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2169                                 [INTERNAL_SSC] = &usb_sgmii_xcvr_diag_ln_vals,
2170                         },
2171                 },
2172         },
2173         .pcs_cmn_vals = {
2174                 [TYPE_USB] = {
2175                         [TYPE_NONE] = {
2176                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2177                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2178                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2179                         },
2180                         [TYPE_PCIE] = {
2181                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2182                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2183                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2184                         },
2185                         [TYPE_SGMII] = {
2186                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2187                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2188                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2189                         },
2190                         [TYPE_QSGMII] = {
2191                                 [NO_SSC] = &usb_phy_pcs_cmn_vals,
2192                                 [EXTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2193                                 [INTERNAL_SSC] = &usb_phy_pcs_cmn_vals,
2194                         },
2195                 },
2196         },
2197         .cmn_vals = {
2198                 [TYPE_PCIE] = {
2199                         [TYPE_NONE] = {
2200                                 [NO_SSC] = NULL,
2201                                 [EXTERNAL_SSC] = NULL,
2202                                 [INTERNAL_SSC] = &sl_pcie_100_int_ssc_cmn_vals,
2203                         },
2204                         [TYPE_SGMII] = {
2205                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2206                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2207                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2208                         },
2209                         [TYPE_QSGMII] = {
2210                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2211                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2212                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2213                         },
2214                         [TYPE_USB] = {
2215                                 [NO_SSC] = &pcie_100_no_ssc_cmn_vals,
2216                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_cmn_vals,
2217                                 [INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,
2218                         },
2219                 },
2220                 [TYPE_SGMII] = {
2221                         [TYPE_NONE] = {
2222                                 [NO_SSC] = &sl_sgmii_100_no_ssc_cmn_vals,
2223                         },
2224                         [TYPE_PCIE] = {
2225                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
2226                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2227                                 [INTERNAL_SSC] = &sgmii_100_int_ssc_cmn_vals,
2228                         },
2229                         [TYPE_USB] = {
2230                                 [NO_SSC] = &sgmii_100_no_ssc_cmn_vals,
2231                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2232                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_cmn_vals,
2233                         },
2234                 },
2235                 [TYPE_QSGMII] = {
2236                         [TYPE_NONE] = {
2237                                 [NO_SSC] = &sl_qsgmii_100_no_ssc_cmn_vals,
2238                         },
2239                         [TYPE_PCIE] = {
2240                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2241                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2242                                 [INTERNAL_SSC] = &qsgmii_100_int_ssc_cmn_vals,
2243                         },
2244                         [TYPE_USB] = {
2245                                 [NO_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2246                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2247                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_cmn_vals,
2248                         },
2249                 },
2250                 [TYPE_USB] = {
2251                         [TYPE_NONE] = {
2252                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2253                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2254                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2255                         },
2256                         [TYPE_PCIE] = {
2257                                 [NO_SSC] = &usb_100_no_ssc_cmn_vals,
2258                                 [EXTERNAL_SSC] = &usb_100_no_ssc_cmn_vals,
2259                                 [INTERNAL_SSC] = &usb_100_int_ssc_cmn_vals,
2260                         },
2261                         [TYPE_SGMII] = {
2262                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2263                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2264                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2265                         },
2266                         [TYPE_QSGMII] = {
2267                                 [NO_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2268                                 [EXTERNAL_SSC] = &sl_usb_100_no_ssc_cmn_vals,
2269                                 [INTERNAL_SSC] = &sl_usb_100_int_ssc_cmn_vals,
2270                         },
2271                 },
2272         },
2273         .tx_ln_vals = {
2274                 [TYPE_PCIE] = {
2275                         [TYPE_NONE] = {
2276                                 [NO_SSC] = NULL,
2277                                 [EXTERNAL_SSC] = NULL,
2278                                 [INTERNAL_SSC] = NULL,
2279                         },
2280                         [TYPE_SGMII] = {
2281                                 [NO_SSC] = NULL,
2282                                 [EXTERNAL_SSC] = NULL,
2283                                 [INTERNAL_SSC] = NULL,
2284                         },
2285                         [TYPE_QSGMII] = {
2286                                 [NO_SSC] = NULL,
2287                                 [EXTERNAL_SSC] = NULL,
2288                                 [INTERNAL_SSC] = NULL,
2289                         },
2290                         [TYPE_USB] = {
2291                                 [NO_SSC] = NULL,
2292                                 [EXTERNAL_SSC] = NULL,
2293                                 [INTERNAL_SSC] = NULL,
2294                         },
2295                 },
2296                 [TYPE_SGMII] = {
2297                         [TYPE_NONE] = {
2298                                 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2299                         },
2300                         [TYPE_PCIE] = {
2301                                 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2302                                 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2303                                 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2304                         },
2305                         [TYPE_USB] = {
2306                                 [NO_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2307                                 [EXTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2308                                 [INTERNAL_SSC] = &ti_sgmii_100_no_ssc_tx_ln_vals,
2309                         },
2310                 },
2311                 [TYPE_QSGMII] = {
2312                         [TYPE_NONE] = {
2313                                 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2314                         },
2315                         [TYPE_PCIE] = {
2316                                 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2317                                 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2318                                 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2319                         },
2320                         [TYPE_USB] = {
2321                                 [NO_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2322                                 [EXTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2323                                 [INTERNAL_SSC] = &ti_qsgmii_100_no_ssc_tx_ln_vals,
2324                         },
2325                 },
2326                 [TYPE_USB] = {
2327                         [TYPE_NONE] = {
2328                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2329                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2330                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2331                         },
2332                         [TYPE_PCIE] = {
2333                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2334                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2335                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2336                         },
2337                         [TYPE_SGMII] = {
2338                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2339                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2340                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2341                         },
2342                         [TYPE_QSGMII] = {
2343                                 [NO_SSC] = &usb_100_no_ssc_tx_ln_vals,
2344                                 [EXTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2345                                 [INTERNAL_SSC] = &usb_100_no_ssc_tx_ln_vals,
2346                         },
2347                 },
2348         },
2349         .rx_ln_vals = {
2350                 [TYPE_PCIE] = {
2351                         [TYPE_NONE] = {
2352                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2353                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2354                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2355                         },
2356                         [TYPE_SGMII] = {
2357                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2358                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2359                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2360                         },
2361                         [TYPE_QSGMII] = {
2362                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2363                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2364                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2365                         },
2366                         [TYPE_USB] = {
2367                                 [NO_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2368                                 [EXTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2369                                 [INTERNAL_SSC] = &pcie_100_no_ssc_rx_ln_vals,
2370                         },
2371                 },
2372                 [TYPE_SGMII] = {
2373                         [TYPE_NONE] = {
2374                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2375                         },
2376                         [TYPE_PCIE] = {
2377                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2378                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2379                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2380                         },
2381                         [TYPE_USB] = {
2382                                 [NO_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2383                                 [EXTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2384                                 [INTERNAL_SSC] = &sgmii_100_no_ssc_rx_ln_vals,
2385                         },
2386                 },
2387                 [TYPE_QSGMII] = {
2388                         [TYPE_NONE] = {
2389                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2390                         },
2391                         [TYPE_PCIE] = {
2392                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2393                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2394                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2395                         },
2396                         [TYPE_USB] = {
2397                                 [NO_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2398                                 [EXTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2399                                 [INTERNAL_SSC] = &qsgmii_100_no_ssc_rx_ln_vals,
2400                         },
2401                 },
2402                 [TYPE_USB] = {
2403                         [TYPE_NONE] = {
2404                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2405                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2406                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2407                         },
2408                         [TYPE_PCIE] = {
2409                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2410                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2411                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2412                         },
2413                         [TYPE_SGMII] = {
2414                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2415                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2416                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2417                         },
2418                         [TYPE_QSGMII] = {
2419                                 [NO_SSC] = &usb_100_no_ssc_rx_ln_vals,
2420                                 [EXTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2421                                 [INTERNAL_SSC] = &usb_100_no_ssc_rx_ln_vals,
2422                         },
2423                 },
2424         },
2425 };
2426
2427 static int cdns_torrent_phy_reset(struct phy *gphy)
2428 {
2429         struct cdns_torrent_phy *sp = dev_get_priv(gphy->dev);
2430
2431         reset_control_assert(sp->phy_rst);
2432         reset_control_deassert(sp->phy_rst);
2433         return 0;
2434 }
2435
2436 static const struct udevice_id cdns_torrent_id_table[] = {
2437         {
2438                 .compatible = "cdns,torrent-phy",
2439                 .data = (ulong)&cdns_map_torrent,
2440         },
2441         {
2442                 .compatible = "ti,j721e-serdes-10g",
2443                 .data = (ulong)&ti_j721e_map_torrent,
2444         },
2445         {}
2446 };
2447
2448 static const struct phy_ops cdns_torrent_phy_ops = {
2449         .init           = cdns_torrent_phy_init,
2450         .power_on       = cdns_torrent_phy_on,
2451         .power_off      = cdns_torrent_phy_off,
2452         .reset          = cdns_torrent_phy_reset,
2453 };
2454
2455 U_BOOT_DRIVER(torrent_phy_provider) = {
2456         .name           = "cdns,torrent",
2457         .id             = UCLASS_PHY,
2458         .of_match       = cdns_torrent_id_table,
2459         .probe          = cdns_torrent_phy_probe,
2460         .remove         = cdns_torrent_phy_remove,
2461         .ops            = &cdns_torrent_phy_ops,
2462         .priv_auto      = sizeof(struct cdns_torrent_phy),
2463 };