drivers/phy/cadence/phy-cadence-sierra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cadence Sierra PHY Driver
   4  *
   5  * Based on the linux driver provided by Cadence
   6  *
   7  * Copyright (c) 2018 Cadence Design Systems
   8  * Author: Alan Douglas <adouglas@cadence.com>
   9  *
  10  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  11  * Jean-Jacques Hiblot <jjhiblot@ti.com>
  12  *
  13  */
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <generic-phy.h>
  18 #include <reset.h>
  19 #include <dm/device.h>
  20 #include <dm/device-internal.h>
  21 #include <dm/device_compat.h>
  22 #include <dm/lists.h>
  23 #include <dm/read.h>
  24 #include <dm/uclass.h>
  25 #include <dm/devres.h>
  26 #include <linux/io.h>
  27 #include <dt-bindings/phy/phy.h>
  28 #include <dt-bindings/phy/phy-cadence.h>
  29 #include <regmap.h>
  30
  31 #define NUM_SSC_MODE            3
  32 #define NUM_PHY_TYPE            3
  33
  34 /* PHY register offsets */
  35 #define SIERRA_COMMON_CDB_OFFSET                        0x0
  36 #define SIERRA_MACRO_ID_REG                             0x0
  37 #define SIERRA_CMN_PLLLC_GEN_PREG                       0x42
  38 #define SIERRA_CMN_PLLLC_MODE_PREG                      0x48
  39 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG            0x49
  40 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG            0x4A
  41 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG             0x4B
  42 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG               0x4F
  43 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG               0x50
  44 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG     0x62
  45 #define SIERRA_CMN_REFRCV_PREG                          0x98
  46 #define SIERRA_CMN_REFRCV1_PREG                         0xB8
  47 #define SIERRA_CMN_PLLLC1_GEN_PREG                      0xC2
  48
  49 #define SIERRA_LANE_CDB_OFFSET(ln, offset)      \
  50                                 (0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
  51
  52 #define SIERRA_DET_STANDEC_A_PREG                       0x000
  53 #define SIERRA_DET_STANDEC_B_PREG                       0x001
  54 #define SIERRA_DET_STANDEC_C_PREG                       0x002
  55 #define SIERRA_DET_STANDEC_D_PREG                       0x003
  56 #define SIERRA_DET_STANDEC_E_PREG                       0x004
  57 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG           0x008
  58 #define SIERRA_PSM_A0IN_TMR_PREG                        0x009
  59 #define SIERRA_PSM_DIAG_PREG                            0x015
  60 #define SIERRA_PSC_TX_A0_PREG                           0x028
  61 #define SIERRA_PSC_TX_A1_PREG                           0x029
  62 #define SIERRA_PSC_TX_A2_PREG                           0x02A
  63 #define SIERRA_PSC_TX_A3_PREG                           0x02B
  64 #define SIERRA_PSC_RX_A0_PREG                           0x030
  65 #define SIERRA_PSC_RX_A1_PREG                           0x031
  66 #define SIERRA_PSC_RX_A2_PREG                           0x032
  67 #define SIERRA_PSC_RX_A3_PREG                           0x033
  68 #define SIERRA_PLLCTRL_SUBRATE_PREG                     0x03A
  69 #define SIERRA_PLLCTRL_GEN_D_PREG                       0x03E
  70 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG                 0x03F
  71 #define SIERRA_PLLCTRL_STATUS_PREG                      0x044
  72 #define SIERRA_CLKPATH_BIASTRIM_PREG                    0x04B
  73 #define SIERRA_DFE_BIASTRIM_PREG                        0x04C
  74 #define SIERRA_DRVCTRL_ATTEN_PREG                       0x06A
  75 #define SIERRA_CLKPATHCTRL_TMR_PREG                     0x081
  76 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG                0x085
  77 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG                0x086
  78 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG                0x087
  79 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG                0x088
  80 #define SIERRA_CREQ_CCLKDET_MODE01_PREG                 0x08E
  81 #define SIERRA_RX_CTLE_MAINTENANCE_PREG                 0x091
  82 #define SIERRA_CREQ_FSMCLK_SEL_PREG                     0x092
  83 #define SIERRA_CREQ_EQ_CTRL_PREG                        0x093
  84 #define SIERRA_CREQ_SPARE_PREG                          0x096
  85 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG             0x097
  86 #define SIERRA_CTLELUT_CTRL_PREG                        0x098
  87 #define SIERRA_DFE_ECMP_RATESEL_PREG                    0x0C0
  88 #define SIERRA_DFE_SMP_RATESEL_PREG                     0x0C1
  89 #define SIERRA_DEQ_PHALIGN_CTRL                         0x0C4
  90 #define SIERRA_DEQ_CONCUR_CTRL1_PREG                    0x0C8
  91 #define SIERRA_DEQ_CONCUR_CTRL2_PREG                    0x0C9
  92 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG                    0x0CD
  93 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG               0x0CE
  94 #define SIERRA_DEQ_ERRCMP_CTRL_PREG                     0x0D0
  95 #define SIERRA_DEQ_OFFSET_CTRL_PREG                     0x0D8
  96 #define SIERRA_DEQ_GAIN_CTRL_PREG                       0x0E0
  97 #define SIERRA_DEQ_VGATUNE_CTRL_PREG                    0x0E1
  98 #define SIERRA_DEQ_GLUT0                                0x0E8
  99 #define SIERRA_DEQ_GLUT1                                0x0E9
 100 #define SIERRA_DEQ_GLUT2                                0x0EA
 101 #define SIERRA_DEQ_GLUT3                                0x0EB
 102 #define SIERRA_DEQ_GLUT4                                0x0EC
 103 #define SIERRA_DEQ_GLUT5                                0x0ED
 104 #define SIERRA_DEQ_GLUT6                                0x0EE
 105 #define SIERRA_DEQ_GLUT7                                0x0EF
 106 #define SIERRA_DEQ_GLUT8                                0x0F0
 107 #define SIERRA_DEQ_GLUT9                                0x0F1
 108 #define SIERRA_DEQ_GLUT10                               0x0F2
 109 #define SIERRA_DEQ_GLUT11                               0x0F3
 110 #define SIERRA_DEQ_GLUT12                               0x0F4
 111 #define SIERRA_DEQ_GLUT13                               0x0F5
 112 #define SIERRA_DEQ_GLUT14                               0x0F6
 113 #define SIERRA_DEQ_GLUT15                               0x0F7
 114 #define SIERRA_DEQ_GLUT16                               0x0F8
 115 #define SIERRA_DEQ_ALUT0                                0x108
 116 #define SIERRA_DEQ_ALUT1                                0x109
 117 #define SIERRA_DEQ_ALUT2                                0x10A
 118 #define SIERRA_DEQ_ALUT3                                0x10B
 119 #define SIERRA_DEQ_ALUT4                                0x10C
 120 #define SIERRA_DEQ_ALUT5                                0x10D
 121 #define SIERRA_DEQ_ALUT6                                0x10E
 122 #define SIERRA_DEQ_ALUT7                                0x10F
 123 #define SIERRA_DEQ_ALUT8                                0x110
 124 #define SIERRA_DEQ_ALUT9                                0x111
 125 #define SIERRA_DEQ_ALUT10                               0x112
 126 #define SIERRA_DEQ_ALUT11                               0x113
 127 #define SIERRA_DEQ_ALUT12                               0x114
 128 #define SIERRA_DEQ_ALUT13                               0x115
 129 #define SIERRA_DEQ_DFETAP_CTRL_PREG                     0x128
 130 #define SIERRA_DFE_EN_1010_IGNORE_PREG                  0x134
 131 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 132 #define SIERRA_DEQ_TAU_CTRL2_PREG                       0x151
 133 #define SIERRA_DEQ_PICTRL_PREG                          0x161
 134 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG                 0x170
 135 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG                 0x171
 136 #define SIERRA_CPICAL_PICNT_MODE1_PREG                  0x174
 137 #define SIERRA_CPI_OUTBUF_RATESEL_PREG                  0x17C
 138 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG         0x183
 139 #define SIERRA_LFPSDET_SUPPORT_PREG                     0x188
 140 #define SIERRA_LFPSFILT_NS_PREG                         0x18A
 141 #define SIERRA_LFPSFILT_RD_PREG                         0x18B
 142 #define SIERRA_LFPSFILT_MP_PREG                         0x18C
 143 #define SIERRA_SIGDET_SUPPORT_PREG                      0x190
 144 #define SIERRA_SDFILT_H2L_A_PREG                        0x191
 145 #define SIERRA_SDFILT_L2H_PREG                          0x193
 146 #define SIERRA_RXBUFFER_CTLECTRL_PREG                   0x19E
 147 #define SIERRA_RXBUFFER_RCDFECTRL_PREG                  0x19F
 148 #define SIERRA_RXBUFFER_DFECTRL_PREG                    0x1A0
 149 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG            0x14F
 150 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 151
 152 #define SIERRA_PHY_PCS_COMMON_OFFSET                    0xc000
 153 #define SIERRA_PHY_PIPE_CMN_CTRL1                       0x0
 154 #define SIERRA_PHY_PLL_CFG                              0xe
 155
 156 #define SIERRA_MACRO_ID                                 0x00007364
 157 #define SIERRA_MAX_LANES                                16
 158 #define PLL_LOCK_TIME                                   100
 159
 160 #define CDNS_SIERRA_INPUT_CLOCKS                        5
 161 enum cdns_sierra_clock_input {
 162         PHY_CLK,
 163         CMN_REFCLK_DIG_DIV,
 164         CMN_REFCLK1_DIG_DIV,
 165         PLL0_REFCLK,
 166         PLL1_REFCLK,
 167 };
 168
 169 #define SIERRA_NUM_CMN_PLLC                             2
 170 #define SIERRA_NUM_CMN_PLLC_PARENTS                     2
 171
 172 static const struct reg_field macro_id_type =
 173                                 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 174 static const struct reg_field phy_pll_cfg_1 =
 175                                 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 176 static const struct reg_field pllctrl_lock =
 177                                 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 178
 179 static const char * const clk_names[] = {
 180         [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
 181         [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
 182 };
 183
 184 enum cdns_sierra_cmn_plllc {
 185         CMN_PLLLC,
 186         CMN_PLLLC1,
 187 };
 188
 189 struct cdns_sierra_pll_mux_reg_fields {
 190         struct reg_field        pfdclk_sel_preg;
 191         struct reg_field        plllc1en_field;
 192         struct reg_field        termen_field;
 193 };
 194
 195 static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {
 196         [CMN_PLLLC] = {
 197                 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
 198                 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
 199                 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
 200         },
 201         [CMN_PLLLC1] = {
 202                 .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
 203                 .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
 204                 .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
 205         },
 206 };
 207
 208 struct cdns_sierra_pll_mux {
 209         struct cdns_sierra_phy  *sp;
 210         struct clk              *clk;
 211         struct clk              *parent_clks[2];
 212         struct regmap_field     *pfdclk_sel_preg;
 213         struct regmap_field     *plllc1en_field;
 214         struct regmap_field     *termen_field;
 215 };
 216
 217 #define reset_control_assert(rst) cdns_reset_assert(rst)
 218 #define reset_control_deassert(rst) cdns_reset_deassert(rst)
 219 #define reset_control reset_ctl
 220
 221 enum cdns_sierra_phy_type {
 222         TYPE_NONE,
 223         TYPE_PCIE,
 224         TYPE_USB
 225 };
 226
 227 enum cdns_sierra_ssc_mode {
 228         NO_SSC,
 229         EXTERNAL_SSC,
 230         INTERNAL_SSC
 231 };
 232
 233 struct cdns_sierra_inst {
 234         enum cdns_sierra_phy_type phy_type;
 235         u32 num_lanes;
 236         u32 mlane;
 237         struct reset_ctl_bulk *lnk_rst;
 238         enum cdns_sierra_ssc_mode ssc_mode;
 239 };
 240
 241 struct cdns_reg_pairs {
 242         u16 val;
 243         u32 off;
 244 };
 245
 246 struct cdns_sierra_vals {
 247         const struct cdns_reg_pairs *reg_pairs;
 248         u32 num_regs;
 249 };
 250
 251 struct cdns_sierra_data {
 252                 u32 id_value;
 253                 u8 block_offset_shift;
 254                 u8 reg_offset_shift;
 255                 struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 256                                                      [NUM_SSC_MODE];
 257                 struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 258                                                      [NUM_SSC_MODE];
 259                 struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
 260                                                     [NUM_SSC_MODE];
 261 };
 262
 263 struct cdns_sierra_phy {
 264         struct udevice *dev;
 265         void *base;
 266         size_t size;
 267         struct regmap *regmap;
 268         struct cdns_sierra_data *init_data;
 269         struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
 270         struct reset_control *phy_rst;
 271         struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 272         struct regmap *regmap_phy_pcs_common_cdb;
 273         struct regmap *regmap_common_cdb;
 274         struct regmap_field *macro_id_type;
 275         struct regmap_field *phy_pll_cfg_1;
 276         struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 277         struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
 278         struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
 279         struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
 280         struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
 281         int nsubnodes;
 282         u32 num_lanes;
 283         bool autoconf;
 284 };
 285
 286 static inline int cdns_reset_assert(struct reset_control *rst)
 287 {
 288         if (rst)
 289                 return reset_assert(rst);
 290         else
 291                 return 0;
 292 }
 293
 294 static inline int cdns_reset_deassert(struct reset_control *rst)
 295 {
 296         if (rst)
 297                 return reset_deassert(rst);
 298         else
 299                 return 0;
 300 }
 301
 302 static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
 303 {
 304         struct cdns_sierra_phy *sp = dev_get_priv(phy->dev);
 305         int index;
 306
 307         if (phy->id >= SIERRA_MAX_LANES)
 308                 return NULL;
 309
 310         for (index = 0; index < sp->nsubnodes; index++) {
 311                 if (phy->id == sp->phys[index]->mlane)
 312                         return sp->phys[index];
 313         }
 314
 315         return NULL;
 316 }
 317
 318 static int cdns_sierra_phy_init(struct phy *gphy)
 319 {
 320         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 321         struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
 322         struct cdns_sierra_data *init_data = phy->init_data;
 323         struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
 324         enum cdns_sierra_phy_type phy_type = ins->phy_type;
 325         enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
 326         const struct cdns_reg_pairs *reg_pairs;
 327         struct cdns_sierra_vals *pcs_cmn_vals;
 328         struct regmap *regmap = phy->regmap;
 329         u32 num_regs;
 330         int i, j;
 331
 332         /* Initialise the PHY registers, unless auto configured */
 333         if (phy->autoconf)
 334                 return 0;
 335
 336         clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);
 337         clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);
 338
 339         /* PHY PCS common registers configurations */
 340         pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
 341         if (pcs_cmn_vals) {
 342                 reg_pairs = pcs_cmn_vals->reg_pairs;
 343                 num_regs = pcs_cmn_vals->num_regs;
 344                 regmap = phy->regmap_phy_pcs_common_cdb;
 345                 for (i = 0; i < num_regs; i++)
 346                         regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 347         }
 348
 349         /* PMA common registers configurations */
 350         pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
 351         if (pma_cmn_vals) {
 352                 reg_pairs = pma_cmn_vals->reg_pairs;
 353                 num_regs = pma_cmn_vals->num_regs;
 354                 regmap = phy->regmap_common_cdb;
 355                 for (i = 0; i < num_regs; i++)
 356                         regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);
 357         }
 358
 359         /* PMA TX lane registers configurations */
 360         pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
 361         if (pma_ln_vals) {
 362                 reg_pairs = pma_ln_vals->reg_pairs;
 363                 num_regs = pma_ln_vals->num_regs;
 364                 for (i = 0; i < ins->num_lanes; i++) {
 365                         regmap = phy->regmap_lane_cdb[i + ins->mlane];
 366                         for (j = 0; j < num_regs; j++)
 367                                 regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);
 368                 }
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int cdns_sierra_phy_on(struct phy *gphy)
 375 {
 376         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 377         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 378         struct udevice *dev = gphy->dev;
 379         u32 val;
 380         int ret;
 381
 382         ret = reset_control_deassert(sp->phy_rst);
 383         if (ret) {
 384                 dev_err(dev, "Failed to take the PHY out of reset\n");
 385                 return ret;
 386         }
 387
 388         /* Take the PHY lane group out of reset */
 389         ret = reset_deassert_bulk(ins->lnk_rst);
 390         if (ret) {
 391                 dev_err(dev, "Failed to take the PHY lane out of reset\n");
 392                 return ret;
 393         }
 394
 395         ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 396                                              val, val, 1000, PLL_LOCK_TIME);
 397         if (ret < 0)
 398                 dev_err(dev, "PLL lock of lane failed\n");
 399
 400         reset_control_assert(sp->phy_rst);
 401         reset_control_deassert(sp->phy_rst);
 402
 403         return ret;
 404 }
 405
 406 static int cdns_sierra_phy_off(struct phy *gphy)
 407 {
 408         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 409
 410         return reset_assert_bulk(ins->lnk_rst);
 411 }
 412
 413 static int cdns_sierra_phy_reset(struct phy *gphy)
 414 {
 415         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 416
 417         reset_control_assert(sp->phy_rst);
 418         reset_control_deassert(sp->phy_rst);
 419         return 0;
 420 };
 421
 422 static const struct phy_ops ops = {
 423         .init           = cdns_sierra_phy_init,
 424         .power_on       = cdns_sierra_phy_on,
 425         .power_off      = cdns_sierra_phy_off,
 426         .reset          = cdns_sierra_phy_reset,
 427 };
 428
 429 struct cdns_sierra_pll_mux_sel {
 430         enum cdns_sierra_cmn_plllc      mux_sel;
 431         u32                             table[2];
 432         const char                      *node_name;
 433         u32                             num_parents;
 434         u32                             parents[2];
 435 };
 436
 437 static struct cdns_sierra_pll_mux_sel pll_clk_mux_sel[] = {
 438         {
 439                 .num_parents = 2,
 440                 .parents = { PLL0_REFCLK, PLL1_REFCLK },
 441                 .mux_sel = CMN_PLLLC,
 442                 .table = { 0, 1 },
 443                 .node_name = "pll_cmnlc",
 444         },
 445         {
 446                 .num_parents = 2,
 447                 .parents = { PLL1_REFCLK, PLL0_REFCLK },
 448                 .mux_sel = CMN_PLLLC1,
 449                 .table = { 1, 0 },
 450                 .node_name = "pll_cmnlc1",
 451         },
 452 };
 453
 454 static int cdns_sierra_pll_mux_set_parent(struct clk *clk, struct clk *parent)
 455 {
 456         struct udevice *dev = clk->dev;
 457         struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
 458         struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
 459         struct cdns_sierra_phy *sp = priv->sp;
 460         int ret;
 461         int i;
 462
 463         for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
 464                 if (parent->dev == priv->parent_clks[i]->dev)
 465                         break;
 466         }
 467
 468         if (i == ARRAY_SIZE(priv->parent_clks))
 469                 return -EINVAL;
 470
 471         ret = regmap_field_write(sp->cmn_refrcv_refclk_plllc1en_preg[data[clk->id].mux_sel], i);
 472         ret |= regmap_field_write(sp->cmn_refrcv_refclk_termen_preg[data[clk->id].mux_sel], i);
 473         ret |= regmap_field_write(sp->cmn_plllc_pfdclk1_sel_preg[data[clk->id].mux_sel],
 474                                   data[clk->id].table[i]);
 475
 476         return ret;
 477 }
 478
 479 static const struct clk_ops cdns_sierra_pll_mux_ops = {
 480         .set_parent = cdns_sierra_pll_mux_set_parent,
 481 };
 482
 483 int cdns_sierra_pll_mux_probe(struct udevice *dev)
 484 {
 485         struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
 486         struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
 487         struct cdns_sierra_pll_mux_sel *data = dev_get_plat(dev);
 488         struct clk *clk;
 489         int i, j;
 490
 491         for (j = 0; j < SIERRA_NUM_CMN_PLLC; j++) {
 492                 for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
 493                         clk = sp->input_clks[data[j].parents[i]];
 494                         if (IS_ERR_OR_NULL(clk)) {
 495                                 dev_err(dev, "No parent clock for PLL mux clocks\n");
 496                                 return IS_ERR(clk) ? PTR_ERR(clk) : -ENOENT;
 497                         }
 498                         priv->parent_clks[i] = clk;
 499                 }
 500         }
 501
 502         priv->sp = dev_get_priv(dev->parent);
 503
 504         return 0;
 505 }
 506
 507 U_BOOT_DRIVER(cdns_sierra_pll_mux_clk) = {
 508         .name                   = "cdns_sierra_mux_clk",
 509         .id                     = UCLASS_CLK,
 510         .priv_auto              = sizeof(struct cdns_sierra_pll_mux),
 511         .ops                    = &cdns_sierra_pll_mux_ops,
 512         .probe                  = cdns_sierra_pll_mux_probe,
 513         .plat_auto              = sizeof(struct cdns_sierra_pll_mux_sel) * SIERRA_NUM_CMN_PLLC,
 514 };
 515
 516 static int cdns_sierra_pll_bind_of_clocks(struct cdns_sierra_phy *sp)
 517 {
 518         struct udevice *dev = sp->dev;
 519         struct driver *cdns_sierra_clk_drv;
 520         struct cdns_sierra_pll_mux_sel *data = pll_clk_mux_sel;
 521         int i, rc;
 522
 523         cdns_sierra_clk_drv = lists_driver_lookup_name("cdns_sierra_mux_clk");
 524         if (!cdns_sierra_clk_drv) {
 525                 dev_err(dev, "Can not find driver 'cdns_sierra_mux_clk'\n");
 526                 return -ENOENT;
 527         }
 528
 529         rc = device_bind(dev, cdns_sierra_clk_drv, "pll_mux_clk",
 530                          data, dev_ofnode(dev), NULL);
 531         if (rc) {
 532                 dev_err(dev, "cannot bind driver for clock %s\n",
 533                         clk_names[i]);
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 540                                     ofnode child)
 541 {
 542         u32 phy_type;
 543
 544         if (ofnode_read_u32(child, "reg", &inst->mlane))
 545                 return -EINVAL;
 546
 547         if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 548                 return -EINVAL;
 549
 550         if (ofnode_read_u32(child, "cdns,phy-type", &phy_type))
 551                 return -EINVAL;
 552
 553         switch (phy_type) {
 554         case PHY_TYPE_PCIE:
 555                 inst->phy_type = TYPE_PCIE;
 556                 break;
 557         case PHY_TYPE_USB3:
 558                 inst->phy_type = TYPE_USB;
 559                 break;
 560         default:
 561                 return -EINVAL;
 562         }
 563
 564         inst->ssc_mode = EXTERNAL_SSC;
 565         ofnode_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);
 566
 567         return 0;
 568 }
 569
 570 static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base,
 571                                        u32 block_offset, u8 block_offset_shift,
 572                                        u8 reg_offset_shift)
 573 {
 574         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 575         struct regmap_config config;
 576
 577         config.r_start = (ulong)(base + (block_offset << block_offset_shift));
 578         config.r_size = sp->size - (block_offset << block_offset_shift);
 579         config.reg_offset_shift = reg_offset_shift;
 580         config.width = REGMAP_SIZE_16;
 581
 582         return devm_regmap_init(dev, NULL, NULL, &config);
 583 }
 584
 585 static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 586 {
 587         struct udevice *dev = sp->dev;
 588         struct regmap_field *field;
 589         struct reg_field reg_field;
 590         struct regmap *regmap;
 591         int i;
 592
 593         regmap = sp->regmap_common_cdb;
 594         field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 595         if (IS_ERR(field)) {
 596                 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 597                 return PTR_ERR(field);
 598         }
 599         sp->macro_id_type = field;
 600
 601         for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {
 602                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;
 603                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 604                 if (IS_ERR(field)) {
 605                         dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);
 606                         return PTR_ERR(field);
 607                 }
 608                 sp->cmn_plllc_pfdclk1_sel_preg[i] = field;
 609
 610                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;
 611                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 612                 if (IS_ERR(field)) {
 613                         dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);
 614                         return PTR_ERR(field);
 615                 }
 616                 sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;
 617
 618                 reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;
 619                 field = devm_regmap_field_alloc(dev, regmap, reg_field);
 620                 if (IS_ERR(field)) {
 621                         dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);
 622                         return PTR_ERR(field);
 623                 }
 624                 sp->cmn_refrcv_refclk_termen_preg[i] = field;
 625         }
 626
 627         regmap = sp->regmap_phy_pcs_common_cdb;
 628         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
 629         if (IS_ERR(field)) {
 630                 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
 631                 return PTR_ERR(field);
 632         }
 633         sp->phy_pll_cfg_1 = field;
 634
 635         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 636                 regmap = sp->regmap_lane_cdb[i];
 637                 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
 638                 if (IS_ERR(field)) {
 639                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 640                         return PTR_ERR(field);
 641                 }
 642                 sp->pllctrl_lock[i] =  field;
 643         }
 644
 645         return 0;
 646 }
 647
 648 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
 649                                    void __iomem *base, u8 block_offset_shift,
 650                                    u8 reg_offset_shift)
 651 {
 652         struct udevice *dev = sp->dev;
 653         struct regmap *regmap;
 654         u32 block_offset;
 655         int i;
 656
 657         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 658                 block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift);
 659                 regmap = cdns_regmap_init(dev, base, block_offset,
 660                                           block_offset_shift, reg_offset_shift);
 661                 if (IS_ERR(regmap)) {
 662                         dev_err(dev, "Failed to init lane CDB regmap\n");
 663                         return PTR_ERR(regmap);
 664                 }
 665                 sp->regmap_lane_cdb[i] = regmap;
 666         }
 667
 668         regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
 669                                   block_offset_shift, reg_offset_shift);
 670         if (IS_ERR(regmap)) {
 671                 dev_err(dev, "Failed to init common CDB regmap\n");
 672                 return PTR_ERR(regmap);
 673         }
 674         sp->regmap_common_cdb = regmap;
 675
 676         regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET,
 677                                   block_offset_shift, reg_offset_shift);
 678         if (IS_ERR(regmap)) {
 679                 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
 680                 return PTR_ERR(regmap);
 681         }
 682         sp->regmap_phy_pcs_common_cdb = regmap;
 683
 684         return 0;
 685 }
 686
 687 static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
 688                                       struct udevice *dev)
 689 {
 690         struct clk *clk;
 691         int ret;
 692
 693         clk = devm_clk_get_optional(dev, "phy_clk");
 694         if (IS_ERR(clk)) {
 695                 dev_err(dev, "failed to get clock phy_clk\n");
 696                 return PTR_ERR(clk);
 697         }
 698         sp->input_clks[PHY_CLK] = clk;
 699
 700         clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
 701         if (IS_ERR(clk)) {
 702                 dev_err(dev, "cmn_refclk_dig_div clock not found\n");
 703                 ret = PTR_ERR(clk);
 704                 return ret;
 705         }
 706         sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
 707
 708         clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
 709         if (IS_ERR(clk)) {
 710                 dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
 711                 ret = PTR_ERR(clk);
 712                 return ret;
 713         }
 714         sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
 715
 716         clk = devm_clk_get_optional(dev, "pll0_refclk");
 717         if (IS_ERR(clk)) {
 718                 dev_err(dev, "pll0_refclk clock not found\n");
 719                 ret = PTR_ERR(clk);
 720                 return ret;
 721         }
 722         sp->input_clks[PLL0_REFCLK] = clk;
 723
 724         clk = devm_clk_get_optional(dev, "pll1_refclk");
 725         if (IS_ERR(clk)) {
 726                 dev_err(dev, "pll1_refclk clock not found\n");
 727                 ret = PTR_ERR(clk);
 728                 return ret;
 729         }
 730         sp->input_clks[PLL1_REFCLK] = clk;
 731
 732         return 0;
 733 }
 734
 735 static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
 736                                       struct udevice *dev)
 737 {
 738         struct reset_control *rst;
 739
 740         rst = devm_reset_control_get(dev, "sierra_reset");
 741         if (IS_ERR(rst)) {
 742                 dev_err(dev, "failed to get reset\n");
 743                 return PTR_ERR(rst);
 744         }
 745         sp->phy_rst = rst;
 746
 747         return 0;
 748 }
 749
 750 static int cdns_sierra_bind_link_nodes(struct  cdns_sierra_phy *sp)
 751 {
 752         struct udevice *dev = sp->dev;
 753         struct driver *link_drv;
 754         ofnode child;
 755         int rc;
 756
 757         link_drv = lists_driver_lookup_name("sierra_phy_link");
 758         if (!link_drv) {
 759                 dev_err(dev, "Cannot find driver 'sierra_phy_link'\n");
 760                 return -ENOENT;
 761         }
 762
 763         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
 764                 if (!(ofnode_name_eq(child, "phy") ||
 765                       ofnode_name_eq(child, "link")))
 766                         continue;
 767
 768                 rc = device_bind(dev, link_drv, "link", NULL, child, NULL);
 769                 if (rc) {
 770                         dev_err(dev, "cannot bind driver for link\n");
 771                         return rc;
 772                 }
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int cdns_sierra_link_probe(struct udevice *dev)
 779 {
 780         struct cdns_sierra_inst *inst = dev_get_priv(dev);
 781         struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
 782         struct reset_ctl_bulk *rst;
 783         int ret, node;
 784
 785         rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
 786         if (IS_ERR(rst)) {
 787                 ret = PTR_ERR(rst);
 788                 dev_err(dev, "failed to get reset\n");
 789                 return ret;
 790         }
 791         inst->lnk_rst = rst;
 792
 793         ret = cdns_sierra_get_optional(inst, dev_ofnode(dev));
 794         if (ret) {
 795                 dev_err(dev, "missing property in node\n");
 796                 return ret;
 797         }
 798         node = sp->nsubnodes;
 799         sp->phys[node] = inst;
 800         sp->nsubnodes += 1;
 801         sp->num_lanes += inst->num_lanes;
 802
 803         /* If more than one subnode, configure the PHY as multilink */
 804         if (!sp->autoconf && sp->nsubnodes > 1)
 805                 regmap_field_write(sp->phy_pll_cfg_1, 0x1);
 806
 807         return 0;
 808 }
 809
 810 U_BOOT_DRIVER(sierra_phy_link) = {
 811         .name           = "sierra_phy_link",
 812         .id             = UCLASS_PHY,
 813         .probe          = cdns_sierra_link_probe,
 814         .priv_auto      = sizeof(struct cdns_sierra_inst),
 815 };
 816
 817 static int cdns_sierra_phy_probe(struct udevice *dev)
 818 {
 819         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 820         struct cdns_sierra_data *data;
 821         unsigned int id_value;
 822         int ret;
 823
 824         sp->dev = dev;
 825
 826         sp->base =  devfdt_remap_addr_index(dev, 0);
 827         if (!sp->base) {
 828                 dev_err(dev, "unable to map regs\n");
 829                 return -ENOMEM;
 830         }
 831         devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size);
 832
 833         /* Get init data for this PHY */
 834         data = (struct cdns_sierra_data *)dev_get_driver_data(dev);
 835         sp->init_data = data;
 836
 837         ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift,
 838                                       data->reg_offset_shift);
 839         if (ret)
 840                 return ret;
 841
 842         ret = cdns_regfield_init(sp);
 843         if (ret)
 844                 return ret;
 845
 846         ret = cdns_sierra_phy_get_clocks(sp, dev);
 847         if (ret)
 848                 return ret;
 849
 850         ret = cdns_sierra_pll_bind_of_clocks(sp);
 851         if (ret)
 852                 return ret;
 853
 854         ret = cdns_sierra_phy_get_resets(sp, dev);
 855         if (ret)
 856                 return ret;
 857
 858         ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
 859         if (ret)
 860                 return ret;
 861
 862         /* Check that PHY is present */
 863         regmap_field_read(sp->macro_id_type, &id_value);
 864         if  (sp->init_data->id_value != id_value) {
 865                 dev_err(dev, "PHY not found 0x%x vs 0x%x\n",
 866                         sp->init_data->id_value, id_value);
 867                 ret = -EINVAL;
 868                 goto clk_disable;
 869         }
 870
 871         sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
 872         /* Binding link nodes as children to serdes */
 873         ret = cdns_sierra_bind_link_nodes(sp);
 874         if (ret)
 875                 goto clk_disable;
 876
 877         dev_info(dev, "sierra probed\n");
 878         return 0;
 879
 880 clk_disable:
 881         clk_disable_unprepare(sp->input_clks[PHY_CLK]);
 882         return ret;
 883 }
 884
 885 static int cdns_sierra_phy_remove(struct udevice *dev)
 886 {
 887         struct cdns_sierra_phy *phy = dev_get_priv(dev);
 888         int i;
 889
 890         reset_control_assert(phy->phy_rst);
 891
 892         /*
 893          * The device level resets will be put automatically.
 894          * Need to put the subnode resets here though.
 895          */
 896         for (i = 0; i < phy->nsubnodes; i++)
 897                 reset_assert_bulk(phy->phys[i]->lnk_rst);
 898
 899         clk_disable_unprepare(phy->input_clks[PHY_CLK]);
 900
 901         return 0;
 902 }
 903
 904 /* PCIE PHY PCS common configuration */
 905 static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
 906         {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
 907 };
 908
 909 static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
 910         .reg_pairs = pcie_phy_pcs_cmn_regs,
 911         .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
 912 };
 913
 914 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
 915 static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
 916         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 917         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 918         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
 919         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 920         {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 921 };
 922
 923 /* refclk100MHz_32b_PCIe_ln_ext_ssc */
 924 static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
 925         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
 926         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
 927         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
 928         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 929         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 930         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 931         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
 932 };
 933
 934 static struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {
 935         .reg_pairs = cdns_pcie_cmn_regs_ext_ssc,
 936         .num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
 937 };
 938
 939 static struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {
 940         .reg_pairs = cdns_pcie_ln_regs_ext_ssc,
 941         .num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
 942 };
 943
 944 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
 945 static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
 946         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 947         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 948         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 949         {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 950 };
 951
 952 /* refclk100MHz_20b_USB_ln_ext_ssc */
 953 static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
 954         {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
 955         {0x000F, SIERRA_DET_STANDEC_B_PREG},
 956         {0x55A5, SIERRA_DET_STANDEC_C_PREG},
 957         {0x69ad, SIERRA_DET_STANDEC_D_PREG},
 958         {0x0241, SIERRA_DET_STANDEC_E_PREG},
 959         {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
 960         {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
 961         {0xCF00, SIERRA_PSM_DIAG_PREG},
 962         {0x001F, SIERRA_PSC_TX_A0_PREG},
 963         {0x0007, SIERRA_PSC_TX_A1_PREG},
 964         {0x0003, SIERRA_PSC_TX_A2_PREG},
 965         {0x0003, SIERRA_PSC_TX_A3_PREG},
 966         {0x0FFF, SIERRA_PSC_RX_A0_PREG},
 967         {0x0003, SIERRA_PSC_RX_A1_PREG},
 968         {0x0003, SIERRA_PSC_RX_A2_PREG},
 969         {0x0001, SIERRA_PSC_RX_A3_PREG},
 970         {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
 971         {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
 972         {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
 973         {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
 974         {0x2512, SIERRA_DFE_BIASTRIM_PREG},
 975         {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
 976         {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
 977         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 978         {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 979         {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
 980         {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 981         {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
 982         {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
 983         {0x0000, SIERRA_CREQ_SPARE_PREG},
 984         {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
 985         {0x8452, SIERRA_CTLELUT_CTRL_PREG},
 986         {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
 987         {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
 988         {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
 989         {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
 990         {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
 991         {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
 992         {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
 993         {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
 994         {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
 995         {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
 996         {0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},
 997         {0x0014, SIERRA_DEQ_GLUT0},
 998         {0x0014, SIERRA_DEQ_GLUT1},
 999         {0x0014, SIERRA_DEQ_GLUT2},
1000         {0x0014, SIERRA_DEQ_GLUT3},
1001         {0x0014, SIERRA_DEQ_GLUT4},
1002         {0x0014, SIERRA_DEQ_GLUT5},
1003         {0x0014, SIERRA_DEQ_GLUT6},
1004         {0x0014, SIERRA_DEQ_GLUT7},
1005         {0x0014, SIERRA_DEQ_GLUT8},
1006         {0x0014, SIERRA_DEQ_GLUT9},
1007         {0x0014, SIERRA_DEQ_GLUT10},
1008         {0x0014, SIERRA_DEQ_GLUT11},
1009         {0x0014, SIERRA_DEQ_GLUT12},
1010         {0x0014, SIERRA_DEQ_GLUT13},
1011         {0x0014, SIERRA_DEQ_GLUT14},
1012         {0x0014, SIERRA_DEQ_GLUT15},
1013         {0x0014, SIERRA_DEQ_GLUT16},
1014         {0x0BAE, SIERRA_DEQ_ALUT0},
1015         {0x0AEB, SIERRA_DEQ_ALUT1},
1016         {0x0A28, SIERRA_DEQ_ALUT2},
1017         {0x0965, SIERRA_DEQ_ALUT3},
1018         {0x08A2, SIERRA_DEQ_ALUT4},
1019         {0x07DF, SIERRA_DEQ_ALUT5},
1020         {0x071C, SIERRA_DEQ_ALUT6},
1021         {0x0659, SIERRA_DEQ_ALUT7},
1022         {0x0596, SIERRA_DEQ_ALUT8},
1023         {0x0514, SIERRA_DEQ_ALUT9},
1024         {0x0492, SIERRA_DEQ_ALUT10},
1025         {0x0410, SIERRA_DEQ_ALUT11},
1026         {0x038E, SIERRA_DEQ_ALUT12},
1027         {0x030C, SIERRA_DEQ_ALUT13},
1028         {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
1029         {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
1030         {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
1031         {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
1032         {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
1033         {0x0033, SIERRA_DEQ_PICTRL_PREG},
1034         {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
1035         {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
1036         {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
1037         {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
1038         {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
1039         {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
1040         {0x000F, SIERRA_LFPSFILT_NS_PREG},
1041         {0x0009, SIERRA_LFPSFILT_RD_PREG},
1042         {0x0001, SIERRA_LFPSFILT_MP_PREG},
1043         {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
1044         {0x8013, SIERRA_SDFILT_H2L_A_PREG},
1045         {0x8009, SIERRA_SDFILT_L2H_PREG},
1046         {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
1047         {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
1048         {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
1049 };
1050
1051 static struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {
1052         .reg_pairs = cdns_usb_cmn_regs_ext_ssc,
1053         .num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
1054 };
1055
1056 static struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {
1057         .reg_pairs = cdns_usb_ln_regs_ext_ssc,
1058         .num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
1059 };
1060
1061 static const struct cdns_sierra_data cdns_map_sierra = {
1062         .id_value = SIERRA_MACRO_ID,
1063         .block_offset_shift = 0x2,
1064         .reg_offset_shift = 0x2,
1065         .pcs_cmn_vals = {
1066                 [TYPE_PCIE] = {
1067                         [TYPE_NONE] = {
1068                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
1069                         },
1070                 },
1071         },
1072         .pma_cmn_vals = {
1073                 [TYPE_PCIE] = {
1074                         [TYPE_NONE] = {
1075                                         [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
1076                                 },
1077                         },
1078                 [TYPE_USB] = {
1079                         [TYPE_NONE] = {
1080                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
1081                         },
1082                 },
1083         },
1084         .pma_ln_vals = {
1085                 [TYPE_PCIE] = {
1086                         [TYPE_NONE] = {
1087                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
1088                         },
1089                 },
1090                 [TYPE_USB] = {
1091                         [TYPE_NONE] = {
1092                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
1093                         },
1094                 },
1095         },
1096 };
1097
1098 static const struct cdns_sierra_data cdns_ti_map_sierra = {
1099         .id_value = SIERRA_MACRO_ID,
1100         .block_offset_shift = 0x0,
1101         .reg_offset_shift = 0x1,
1102         .pcs_cmn_vals = {
1103                 [TYPE_PCIE] = {
1104                         [TYPE_NONE] = {
1105                                 [EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,
1106                         },
1107                 },
1108         },
1109         .pma_cmn_vals = {
1110                 [TYPE_PCIE] = {
1111                         [TYPE_NONE] = {
1112                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,
1113                         },
1114                 },
1115                 [TYPE_USB] = {
1116                         [TYPE_NONE] = {
1117                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,
1118                         },
1119                 },
1120         },
1121         .pma_ln_vals = {
1122                 [TYPE_PCIE] = {
1123                         [TYPE_NONE] = {
1124                                 [EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,
1125                         },
1126                 },
1127                 [TYPE_USB] = {
1128                         [TYPE_NONE] = {
1129                                 [EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,
1130                         },
1131                 },
1132         },
1133 };
1134
1135 static const struct udevice_id cdns_sierra_id_table[] = {
1136         {
1137                 .compatible = "cdns,sierra-phy-t0",
1138                 .data = (ulong)&cdns_map_sierra,
1139         },
1140         {
1141                 .compatible = "ti,sierra-phy-t0",
1142                 .data = (ulong)&cdns_ti_map_sierra,
1143         },
1144         {}
1145 };
1146
1147 U_BOOT_DRIVER(sierra_phy_provider) = {
1148         .name           = "cdns,sierra",
1149         .id             = UCLASS_PHY,
1150         .of_match       = cdns_sierra_id_table,
1151         .probe          = cdns_sierra_phy_probe,
1152         .remove         = cdns_sierra_phy_remove,
1153         .ops            = &ops,
1154         .priv_auto      = sizeof(struct cdns_sierra_phy),
1155 };