drivers/phy/cadence/phy-cadence-sierra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Cadence Sierra PHY Driver
   4  *
   5  * Based on the linux driver provided by Cadence
   6  *
   7  * Copyright (c) 2018 Cadence Design Systems
   8  * Author: Alan Douglas <adouglas@cadence.com>
   9  *
  10  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
  11  * Jean-Jacques Hiblot <jjhiblot@ti.com>
  12  *
  13  */
  14 #include <common.h>
  15 #include <clk.h>
  16 #include <generic-phy.h>
  17 #include <reset.h>
  18 #include <dm/device.h>
  19 #include <dm/device-internal.h>
  20 #include <dm/device_compat.h>
  21 #include <dm/lists.h>
  22 #include <dm/read.h>
  23 #include <dm/uclass.h>
  24 #include <dm/devres.h>
  25 #include <linux/io.h>
  26 #include <dt-bindings/phy/phy.h>
  27 #include <regmap.h>
  28
  29 /* PHY register offsets */
  30 #define SIERRA_COMMON_CDB_OFFSET                        0x0
  31 #define SIERRA_MACRO_ID_REG                             0x0
  32 #define SIERRA_CMN_PLLLC_MODE_PREG                      0x48
  33 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG            0x49
  34 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG            0x4A
  35 #define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG             0x4B
  36 #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG               0x4F
  37 #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG               0x50
  38 #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG     0x62
  39
  40 #define SIERRA_LANE_CDB_OFFSET(ln, offset)      \
  41                                 (0x4000 + ((ln) * (0x800 >> (2 - (offset)))))
  42
  43 #define SIERRA_DET_STANDEC_A_PREG                       0x000
  44 #define SIERRA_DET_STANDEC_B_PREG                       0x001
  45 #define SIERRA_DET_STANDEC_C_PREG                       0x002
  46 #define SIERRA_DET_STANDEC_D_PREG                       0x003
  47 #define SIERRA_DET_STANDEC_E_PREG                       0x004
  48 #define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG           0x008
  49 #define SIERRA_PSM_A0IN_TMR_PREG                        0x009
  50 #define SIERRA_PSM_DIAG_PREG                            0x015
  51 #define SIERRA_PSC_TX_A0_PREG                           0x028
  52 #define SIERRA_PSC_TX_A1_PREG                           0x029
  53 #define SIERRA_PSC_TX_A2_PREG                           0x02A
  54 #define SIERRA_PSC_TX_A3_PREG                           0x02B
  55 #define SIERRA_PSC_RX_A0_PREG                           0x030
  56 #define SIERRA_PSC_RX_A1_PREG                           0x031
  57 #define SIERRA_PSC_RX_A2_PREG                           0x032
  58 #define SIERRA_PSC_RX_A3_PREG                           0x033
  59 #define SIERRA_PLLCTRL_SUBRATE_PREG                     0x03A
  60 #define SIERRA_PLLCTRL_GEN_D_PREG                       0x03E
  61 #define SIERRA_PLLCTRL_CPGAIN_MODE_PREG                 0x03F
  62 #define SIERRA_PLLCTRL_STATUS_PREG                      0x044
  63 #define SIERRA_CLKPATH_BIASTRIM_PREG                    0x04B
  64 #define SIERRA_DFE_BIASTRIM_PREG                        0x04C
  65 #define SIERRA_DRVCTRL_ATTEN_PREG                       0x06A
  66 #define SIERRA_CLKPATHCTRL_TMR_PREG                     0x081
  67 #define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG                0x085
  68 #define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG                0x086
  69 #define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG                0x087
  70 #define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG                0x088
  71 #define SIERRA_CREQ_CCLKDET_MODE01_PREG                 0x08E
  72 #define SIERRA_RX_CTLE_MAINTENANCE_PREG                 0x091
  73 #define SIERRA_CREQ_FSMCLK_SEL_PREG                     0x092
  74 #define SIERRA_CREQ_EQ_CTRL_PREG                        0x093
  75 #define SIERRA_CREQ_SPARE_PREG                          0x096
  76 #define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG             0x097
  77 #define SIERRA_CTLELUT_CTRL_PREG                        0x098
  78 #define SIERRA_DFE_ECMP_RATESEL_PREG                    0x0C0
  79 #define SIERRA_DFE_SMP_RATESEL_PREG                     0x0C1
  80 #define SIERRA_DEQ_PHALIGN_CTRL                         0x0C4
  81 #define SIERRA_DEQ_CONCUR_CTRL1_PREG                    0x0C8
  82 #define SIERRA_DEQ_CONCUR_CTRL2_PREG                    0x0C9
  83 #define SIERRA_DEQ_EPIPWR_CTRL2_PREG                    0x0CD
  84 #define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG               0x0CE
  85 #define SIERRA_DEQ_ERRCMP_CTRL_PREG                     0x0D0
  86 #define SIERRA_DEQ_OFFSET_CTRL_PREG                     0x0D8
  87 #define SIERRA_DEQ_GAIN_CTRL_PREG                       0x0E0
  88 #define SIERRA_DEQ_VGATUNE_CTRL_PREG                    0x0E1
  89 #define SIERRA_DEQ_GLUT0                                0x0E8
  90 #define SIERRA_DEQ_GLUT1                                0x0E9
  91 #define SIERRA_DEQ_GLUT2                                0x0EA
  92 #define SIERRA_DEQ_GLUT3                                0x0EB
  93 #define SIERRA_DEQ_GLUT4                                0x0EC
  94 #define SIERRA_DEQ_GLUT5                                0x0ED
  95 #define SIERRA_DEQ_GLUT6                                0x0EE
  96 #define SIERRA_DEQ_GLUT7                                0x0EF
  97 #define SIERRA_DEQ_GLUT8                                0x0F0
  98 #define SIERRA_DEQ_GLUT9                                0x0F1
  99 #define SIERRA_DEQ_GLUT10                               0x0F2
 100 #define SIERRA_DEQ_GLUT11                               0x0F3
 101 #define SIERRA_DEQ_GLUT12                               0x0F4
 102 #define SIERRA_DEQ_GLUT13                               0x0F5
 103 #define SIERRA_DEQ_GLUT14                               0x0F6
 104 #define SIERRA_DEQ_GLUT15                               0x0F7
 105 #define SIERRA_DEQ_GLUT16                               0x0F8
 106 #define SIERRA_DEQ_ALUT0                                0x108
 107 #define SIERRA_DEQ_ALUT1                                0x109
 108 #define SIERRA_DEQ_ALUT2                                0x10A
 109 #define SIERRA_DEQ_ALUT3                                0x10B
 110 #define SIERRA_DEQ_ALUT4                                0x10C
 111 #define SIERRA_DEQ_ALUT5                                0x10D
 112 #define SIERRA_DEQ_ALUT6                                0x10E
 113 #define SIERRA_DEQ_ALUT7                                0x10F
 114 #define SIERRA_DEQ_ALUT8                                0x110
 115 #define SIERRA_DEQ_ALUT9                                0x111
 116 #define SIERRA_DEQ_ALUT10                               0x112
 117 #define SIERRA_DEQ_ALUT11                               0x113
 118 #define SIERRA_DEQ_ALUT12                               0x114
 119 #define SIERRA_DEQ_ALUT13                               0x115
 120 #define SIERRA_DEQ_DFETAP_CTRL_PREG                     0x128
 121 #define SIERRA_DFE_EN_1010_IGNORE_PREG                  0x134
 122 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 123 #define SIERRA_DEQ_TAU_CTRL2_PREG                       0x151
 124 #define SIERRA_DEQ_PICTRL_PREG                          0x161
 125 #define SIERRA_CPICAL_TMRVAL_MODE1_PREG                 0x170
 126 #define SIERRA_CPICAL_TMRVAL_MODE0_PREG                 0x171
 127 #define SIERRA_CPICAL_PICNT_MODE1_PREG                  0x174
 128 #define SIERRA_CPI_OUTBUF_RATESEL_PREG                  0x17C
 129 #define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG         0x183
 130 #define SIERRA_LFPSDET_SUPPORT_PREG                     0x188
 131 #define SIERRA_LFPSFILT_NS_PREG                         0x18A
 132 #define SIERRA_LFPSFILT_RD_PREG                         0x18B
 133 #define SIERRA_LFPSFILT_MP_PREG                         0x18C
 134 #define SIERRA_SIGDET_SUPPORT_PREG                      0x190
 135 #define SIERRA_SDFILT_H2L_A_PREG                        0x191
 136 #define SIERRA_SDFILT_L2H_PREG                          0x193
 137 #define SIERRA_RXBUFFER_CTLECTRL_PREG                   0x19E
 138 #define SIERRA_RXBUFFER_RCDFECTRL_PREG                  0x19F
 139 #define SIERRA_RXBUFFER_DFECTRL_PREG                    0x1A0
 140 #define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG            0x14F
 141 #define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG            0x150
 142
 143 #define SIERRA_PHY_CONFIG_CTRL_OFFSET                   0xc000
 144 #define SIERRA_PHY_PLL_CFG                              0xe
 145
 146 #define SIERRA_MACRO_ID                                 0x00007364
 147 #define SIERRA_MAX_LANES                                16
 148 #define PLL_LOCK_TIME                                   100
 149
 150 static const struct reg_field macro_id_type =
 151                                 REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
 152 static const struct reg_field phy_pll_cfg_1 =
 153                                 REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
 154 static const struct reg_field pllctrl_lock =
 155                                 REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
 156
 157 #define reset_control_assert(rst) cdns_reset_assert(rst)
 158 #define reset_control_deassert(rst) cdns_reset_deassert(rst)
 159 #define reset_control reset_ctl
 160
 161 struct cdns_sierra_inst {
 162         u32 phy_type;
 163         u32 num_lanes;
 164         u32 mlane;
 165         struct reset_ctl_bulk *lnk_rst;
 166 };
 167
 168 struct cdns_reg_pairs {
 169         u16 val;
 170         u32 off;
 171 };
 172
 173 struct cdns_sierra_data {
 174                 u32 id_value;
 175                 u8 block_offset_shift;
 176                 u8 reg_offset_shift;
 177                 u32 pcie_cmn_regs;
 178                 u32 pcie_ln_regs;
 179                 u32 usb_cmn_regs;
 180                 u32 usb_ln_regs;
 181                 struct cdns_reg_pairs *pcie_cmn_vals;
 182                 struct cdns_reg_pairs *pcie_ln_vals;
 183                 struct cdns_reg_pairs *usb_cmn_vals;
 184                 struct cdns_reg_pairs *usb_ln_vals;
 185 };
 186
 187 struct cdns_regmap_cdb_context {
 188         struct udevice *dev;
 189         void __iomem *base;
 190         u8 reg_offset_shift;
 191 };
 192
 193 struct cdns_sierra_phy {
 194         struct udevice *dev;
 195         void *base;
 196         size_t size;
 197         struct regmap *regmap;
 198         struct cdns_sierra_data *init_data;
 199         struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
 200         struct reset_control *phy_rst;
 201         struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
 202         struct regmap *regmap_phy_config_ctrl;
 203         struct regmap *regmap_common_cdb;
 204         struct regmap_field *macro_id_type;
 205         struct regmap_field *phy_pll_cfg_1;
 206         struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
 207         struct clk *clk;
 208         struct clk *cmn_refclk;
 209         struct clk *cmn_refclk1;
 210         int nsubnodes;
 211         u32 num_lanes;
 212         bool autoconf;
 213 };
 214
 215 static inline int cdns_reset_assert(struct reset_control *rst)
 216 {
 217         if (rst)
 218                 return reset_assert(rst);
 219         else
 220                 return 0;
 221 }
 222
 223 static inline int cdns_reset_deassert(struct reset_control *rst)
 224 {
 225         if (rst)
 226                 return reset_deassert(rst);
 227         else
 228                 return 0;
 229 }
 230
 231 static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
 232 {
 233         struct cdns_sierra_phy *sp = dev_get_priv(phy->dev);
 234         int index;
 235
 236         if (phy->id >= SIERRA_MAX_LANES)
 237                 return NULL;
 238
 239         for (index = 0; index < sp->nsubnodes; index++) {
 240                 if (phy->id == sp->phys[index].mlane)
 241                         return &sp->phys[index];
 242         }
 243
 244         return NULL;
 245 }
 246
 247 static int cdns_sierra_phy_init(struct phy *gphy)
 248 {
 249         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 250         struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
 251         struct regmap *regmap = phy->regmap;
 252         int i, j;
 253         struct cdns_reg_pairs *cmn_vals, *ln_vals;
 254         u32 num_cmn_regs, num_ln_regs;
 255
 256         /* Initialise the PHY registers, unless auto configured */
 257         if (phy->autoconf)
 258                 return 0;
 259
 260         clk_set_rate(phy->cmn_refclk, 25000000);
 261         clk_set_rate(phy->cmn_refclk1, 25000000);
 262
 263         if (ins->phy_type == PHY_TYPE_PCIE) {
 264                 num_cmn_regs = phy->init_data->pcie_cmn_regs;
 265                 num_ln_regs = phy->init_data->pcie_ln_regs;
 266                 cmn_vals = phy->init_data->pcie_cmn_vals;
 267                 ln_vals = phy->init_data->pcie_ln_vals;
 268         } else if (ins->phy_type == PHY_TYPE_USB3) {
 269                 num_cmn_regs = phy->init_data->usb_cmn_regs;
 270                 num_ln_regs = phy->init_data->usb_ln_regs;
 271                 cmn_vals = phy->init_data->usb_cmn_vals;
 272                 ln_vals = phy->init_data->usb_ln_vals;
 273         } else {
 274                 return -EINVAL;
 275         }
 276
 277         regmap = phy->regmap_common_cdb;
 278         for (j = 0; j < num_cmn_regs ; j++)
 279                 regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
 280
 281         for (i = 0; i < ins->num_lanes; i++) {
 282                 for (j = 0; j < num_ln_regs ; j++) {
 283                         regmap = phy->regmap_lane_cdb[i + ins->mlane];
 284                         regmap_write(regmap, ln_vals[j].off, ln_vals[j].val);
 285                 }
 286         }
 287
 288         return 0;
 289 }
 290
 291 static int cdns_sierra_phy_on(struct phy *gphy)
 292 {
 293         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 294         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 295         struct udevice *dev = gphy->dev;
 296         u32 val;
 297         int ret;
 298
 299         /* Take the PHY lane group out of reset */
 300         ret = reset_deassert_bulk(ins->lnk_rst);
 301         if (ret) {
 302                 dev_err(dev, "Failed to take the PHY lane out of reset\n");
 303                 return ret;
 304         }
 305
 306         ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
 307                                              val, val, 1000, PLL_LOCK_TIME);
 308         if (ret < 0)
 309                 dev_err(dev, "PLL lock of lane failed\n");
 310
 311         reset_control_assert(sp->phy_rst);
 312         reset_control_deassert(sp->phy_rst);
 313
 314         return ret;
 315 }
 316
 317 static int cdns_sierra_phy_off(struct phy *gphy)
 318 {
 319         struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
 320
 321         return reset_assert_bulk(ins->lnk_rst);
 322 }
 323
 324 static int cdns_sierra_phy_reset(struct phy *gphy)
 325 {
 326         struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
 327
 328         reset_control_assert(sp->phy_rst);
 329         reset_control_deassert(sp->phy_rst);
 330         return 0;
 331 };
 332
 333 static const struct phy_ops ops = {
 334         .init           = cdns_sierra_phy_init,
 335         .power_on       = cdns_sierra_phy_on,
 336         .power_off      = cdns_sierra_phy_off,
 337         .reset          = cdns_sierra_phy_reset,
 338 };
 339
 340 static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,
 341                                     ofnode child)
 342 {
 343         if (ofnode_read_u32(child, "reg", &inst->mlane))
 344                 return -EINVAL;
 345
 346         if (ofnode_read_u32(child, "cdns,num-lanes", &inst->num_lanes))
 347                 return -EINVAL;
 348
 349         if (ofnode_read_u32(child, "cdns,phy-type", &inst->phy_type))
 350                 return -EINVAL;
 351
 352         return 0;
 353 }
 354
 355 static struct regmap *cdns_regmap_init(struct udevice *dev, void __iomem *base,
 356                                        u32 block_offset, u8 block_offset_shift,
 357                                        u8 reg_offset_shift)
 358 {
 359         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 360         struct regmap_config config;
 361
 362         config.r_start = (ulong)(base + (block_offset << block_offset_shift));
 363         config.r_size = sp->size - (block_offset << block_offset_shift);
 364         config.reg_offset_shift = reg_offset_shift;
 365         config.width = REGMAP_SIZE_16;
 366
 367         return devm_regmap_init(dev, NULL, NULL, &config);
 368 }
 369
 370 static int cdns_regfield_init(struct cdns_sierra_phy *sp)
 371 {
 372         struct udevice *dev = sp->dev;
 373         struct regmap_field *field;
 374         struct regmap *regmap;
 375         int i;
 376
 377         regmap = sp->regmap_common_cdb;
 378         field = devm_regmap_field_alloc(dev, regmap, macro_id_type);
 379         if (IS_ERR(field)) {
 380                 dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");
 381                 return PTR_ERR(field);
 382         }
 383         sp->macro_id_type = field;
 384
 385         regmap = sp->regmap_phy_config_ctrl;
 386         field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
 387         if (IS_ERR(field)) {
 388                 dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
 389                 return PTR_ERR(field);
 390         }
 391         sp->phy_pll_cfg_1 = field;
 392
 393         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 394                 regmap = sp->regmap_lane_cdb[i];
 395                 field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
 396                 if (IS_ERR(field)) {
 397                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 398                         return PTR_ERR(field);
 399                 }
 400                 sp->pllctrl_lock[i] =  field;
 401         }
 402
 403         return 0;
 404 }
 405
 406 static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,
 407                                    void __iomem *base, u8 block_offset_shift,
 408                                    u8 reg_offset_shift)
 409 {
 410         struct udevice *dev = sp->dev;
 411         struct regmap *regmap;
 412         u32 block_offset;
 413         int i;
 414
 415         for (i = 0; i < SIERRA_MAX_LANES; i++) {
 416                 block_offset = SIERRA_LANE_CDB_OFFSET(i, reg_offset_shift);
 417                 regmap = cdns_regmap_init(dev, base, block_offset,
 418                                           block_offset_shift, reg_offset_shift);
 419                 if (IS_ERR(regmap)) {
 420                         dev_err(dev, "Failed to init lane CDB regmap\n");
 421                         return PTR_ERR(regmap);
 422                 }
 423                 sp->regmap_lane_cdb[i] = regmap;
 424         }
 425
 426         regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,
 427                                   block_offset_shift, reg_offset_shift);
 428         if (IS_ERR(regmap)) {
 429                 dev_err(dev, "Failed to init common CDB regmap\n");
 430                 return PTR_ERR(regmap);
 431         }
 432         sp->regmap_common_cdb = regmap;
 433
 434         regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
 435                                   block_offset_shift, reg_offset_shift);
 436         if (IS_ERR(regmap)) {
 437                 dev_err(dev, "Failed to init PHY config and control regmap\n");
 438                 return PTR_ERR(regmap);
 439         }
 440         sp->regmap_phy_config_ctrl = regmap;
 441
 442         return 0;
 443 }
 444
 445 static int cdns_sierra_phy_probe(struct udevice *dev)
 446 {
 447         struct cdns_sierra_phy *sp = dev_get_priv(dev);
 448         struct cdns_sierra_data *data;
 449         unsigned int id_value;
 450         int ret, node = 0;
 451         struct clk *clk;
 452         ofnode child;
 453
 454         sp->dev = dev;
 455
 456         sp->base =  devfdt_remap_addr_index(dev, 0);
 457         if (!sp->base) {
 458                 dev_err(dev, "unable to map regs\n");
 459                 return -ENOMEM;
 460         }
 461         devfdt_get_addr_size_index(dev, 0, (fdt_size_t *)&sp->size);
 462
 463         /* Get init data for this PHY */
 464         data = (struct cdns_sierra_data *)dev_get_driver_data(dev);
 465         sp->init_data = data;
 466
 467         ret = cdns_regmap_init_blocks(sp, sp->base, data->block_offset_shift,
 468                                       data->reg_offset_shift);
 469         if (ret)
 470                 return ret;
 471
 472         ret = cdns_regfield_init(sp);
 473         if (ret)
 474                 return ret;
 475
 476         sp->clk = devm_clk_get_optional(dev, "phy_clk");
 477         if (IS_ERR(sp->clk)) {
 478                 dev_err(dev, "failed to get clock phy_clk\n");
 479                 return PTR_ERR(sp->clk);
 480         }
 481
 482         sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
 483         if (IS_ERR(sp->phy_rst)) {
 484                 dev_err(dev, "failed to get reset\n");
 485                 return PTR_ERR(sp->phy_rst);
 486         }
 487
 488         clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
 489         if (IS_ERR(clk)) {
 490                 dev_err(dev, "cmn_refclk clock not found\n");
 491                 ret = PTR_ERR(clk);
 492                 return ret;
 493         }
 494         sp->cmn_refclk = clk;
 495
 496         clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
 497         if (IS_ERR(clk)) {
 498                 dev_err(dev, "cmn_refclk1 clock not found\n");
 499                 ret = PTR_ERR(clk);
 500                 return ret;
 501         }
 502         sp->cmn_refclk1 = clk;
 503
 504         ret = clk_prepare_enable(sp->clk);
 505         if (ret)
 506                 return ret;
 507
 508         /* Check that PHY is present */
 509         regmap_field_read(sp->macro_id_type, &id_value);
 510         if  (sp->init_data->id_value != id_value) {
 511                 dev_err(dev, "PHY not found 0x%x vs 0x%x\n",
 512                         sp->init_data->id_value, id_value);
 513                 ret = -EINVAL;
 514                 goto clk_disable;
 515         }
 516
 517         sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
 518
 519         ofnode_for_each_subnode(child, dev_ofnode(dev)) {
 520                 sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
 521                                                                      child);
 522                 if (IS_ERR(sp->phys[node].lnk_rst)) {
 523                         ret = PTR_ERR(sp->phys[node].lnk_rst);
 524                         dev_err(dev, "failed to get reset %s\n",
 525                                 ofnode_get_name(child));
 526                         goto put_child2;
 527                 }
 528
 529                 if (!sp->autoconf) {
 530                         ret = cdns_sierra_get_optional(&sp->phys[node], child);
 531                         if (ret) {
 532                                 dev_err(dev, "missing property in node %s\n",
 533                                         ofnode_get_name(child));
 534                                 goto put_child;
 535                         }
 536                 }
 537                 sp->num_lanes += sp->phys[node].num_lanes;
 538
 539                 node++;
 540         }
 541         sp->nsubnodes = node;
 542
 543         /* If more than one subnode, configure the PHY as multilink */
 544         if (!sp->autoconf && sp->nsubnodes > 1)
 545                 regmap_field_write(sp->phy_pll_cfg_1, 0x1);
 546
 547         reset_control_deassert(sp->phy_rst);
 548         dev_info(dev, "sierra probed\n");
 549         return 0;
 550
 551 put_child:
 552         node++;
 553 put_child2:
 554
 555 clk_disable:
 556         clk_disable_unprepare(sp->clk);
 557         return ret;
 558 }
 559
 560 static int cdns_sierra_phy_remove(struct udevice *dev)
 561 {
 562         struct cdns_sierra_phy *phy = dev_get_priv(dev);
 563         int i;
 564
 565         reset_control_assert(phy->phy_rst);
 566
 567         /*
 568          * The device level resets will be put automatically.
 569          * Need to put the subnode resets here though.
 570          */
 571         for (i = 0; i < phy->nsubnodes; i++)
 572                 reset_assert_bulk(phy->phys[i].lnk_rst);
 573
 574         return 0;
 575 }
 576
 577 /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
 578 static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
 579         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 580         {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 581         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},
 582         {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 583         {0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 584 };
 585
 586 /* refclk100MHz_32b_PCIe_ln_ext_ssc */
 587 static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {
 588         {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},
 589         {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},
 590         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},
 591         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 592         {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 593         {0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 594         {0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG}
 595 };
 596
 597 /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */
 598 static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {
 599         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
 600         {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},
 601         {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},
 602         {0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}
 603 };
 604
 605 /* refclk100MHz_20b_USB_ln_ext_ssc */
 606 static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
 607         {0xFE0A, SIERRA_DET_STANDEC_A_PREG},
 608         {0x000F, SIERRA_DET_STANDEC_B_PREG},
 609         {0x00A5, SIERRA_DET_STANDEC_C_PREG},
 610         {0x69ad, SIERRA_DET_STANDEC_D_PREG},
 611         {0x0241, SIERRA_DET_STANDEC_E_PREG},
 612         {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
 613         {0x0014, SIERRA_PSM_A0IN_TMR_PREG},
 614         {0xCF00, SIERRA_PSM_DIAG_PREG},
 615         {0x001F, SIERRA_PSC_TX_A0_PREG},
 616         {0x0007, SIERRA_PSC_TX_A1_PREG},
 617         {0x0003, SIERRA_PSC_TX_A2_PREG},
 618         {0x0003, SIERRA_PSC_TX_A3_PREG},
 619         {0x0FFF, SIERRA_PSC_RX_A0_PREG},
 620         {0x0619, SIERRA_PSC_RX_A1_PREG},
 621         {0x0003, SIERRA_PSC_RX_A2_PREG},
 622         {0x0001, SIERRA_PSC_RX_A3_PREG},
 623         {0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
 624         {0x0406, SIERRA_PLLCTRL_GEN_D_PREG},
 625         {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
 626         {0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
 627         {0x2512, SIERRA_DFE_BIASTRIM_PREG},
 628         {0x0000, SIERRA_DRVCTRL_ATTEN_PREG},
 629         {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
 630         {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
 631         {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
 632         {0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
 633         {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
 634         {0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
 635         {0x0000, SIERRA_CREQ_EQ_CTRL_PREG},
 636         {0x8000, SIERRA_CREQ_SPARE_PREG},
 637         {0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
 638         {0x8453, SIERRA_CTLELUT_CTRL_PREG},
 639         {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
 640         {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
 641         {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
 642         {0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
 643         {0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
 644         {0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
 645         {0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},
 646         {0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
 647         {0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
 648         {0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
 649         {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
 650         {0x0014, SIERRA_DEQ_GLUT0},
 651         {0x0014, SIERRA_DEQ_GLUT1},
 652         {0x0014, SIERRA_DEQ_GLUT2},
 653         {0x0014, SIERRA_DEQ_GLUT3},
 654         {0x0014, SIERRA_DEQ_GLUT4},
 655         {0x0014, SIERRA_DEQ_GLUT5},
 656         {0x0014, SIERRA_DEQ_GLUT6},
 657         {0x0014, SIERRA_DEQ_GLUT7},
 658         {0x0014, SIERRA_DEQ_GLUT8},
 659         {0x0014, SIERRA_DEQ_GLUT9},
 660         {0x0014, SIERRA_DEQ_GLUT10},
 661         {0x0014, SIERRA_DEQ_GLUT11},
 662         {0x0014, SIERRA_DEQ_GLUT12},
 663         {0x0014, SIERRA_DEQ_GLUT13},
 664         {0x0014, SIERRA_DEQ_GLUT14},
 665         {0x0014, SIERRA_DEQ_GLUT15},
 666         {0x0014, SIERRA_DEQ_GLUT16},
 667         {0x0BAE, SIERRA_DEQ_ALUT0},
 668         {0x0AEB, SIERRA_DEQ_ALUT1},
 669         {0x0A28, SIERRA_DEQ_ALUT2},
 670         {0x0965, SIERRA_DEQ_ALUT3},
 671         {0x08A2, SIERRA_DEQ_ALUT4},
 672         {0x07DF, SIERRA_DEQ_ALUT5},
 673         {0x071C, SIERRA_DEQ_ALUT6},
 674         {0x0659, SIERRA_DEQ_ALUT7},
 675         {0x0596, SIERRA_DEQ_ALUT8},
 676         {0x0514, SIERRA_DEQ_ALUT9},
 677         {0x0492, SIERRA_DEQ_ALUT10},
 678         {0x0410, SIERRA_DEQ_ALUT11},
 679         {0x038E, SIERRA_DEQ_ALUT12},
 680         {0x030C, SIERRA_DEQ_ALUT13},
 681         {0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},
 682         {0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},
 683         {0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},
 684         {0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},
 685         {0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},
 686         {0x0033, SIERRA_DEQ_PICTRL_PREG},
 687         {0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},
 688         {0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},
 689         {0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},
 690         {0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},
 691         {0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},
 692         {0x0005, SIERRA_LFPSDET_SUPPORT_PREG},
 693         {0x000F, SIERRA_LFPSFILT_NS_PREG},
 694         {0x0009, SIERRA_LFPSFILT_RD_PREG},
 695         {0x0001, SIERRA_LFPSFILT_MP_PREG},
 696         {0x8013, SIERRA_SDFILT_H2L_A_PREG},
 697         {0x8009, SIERRA_SDFILT_L2H_PREG},
 698         {0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
 699         {0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},
 700         {0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}
 701 };
 702
 703 static const struct cdns_sierra_data cdns_map_sierra = {
 704         SIERRA_MACRO_ID,
 705         0x2,
 706         0x2,
 707         ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
 708         ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
 709         ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
 710         ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
 711         cdns_pcie_cmn_regs_ext_ssc,
 712         cdns_pcie_ln_regs_ext_ssc,
 713         cdns_usb_cmn_regs_ext_ssc,
 714         cdns_usb_ln_regs_ext_ssc,
 715 };
 716
 717 static const struct cdns_sierra_data cdns_ti_map_sierra = {
 718         SIERRA_MACRO_ID,
 719         0x0,
 720         0x1,
 721         ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),
 722         ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),
 723         ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),
 724         ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),
 725         cdns_pcie_cmn_regs_ext_ssc,
 726         cdns_pcie_ln_regs_ext_ssc,
 727         cdns_usb_cmn_regs_ext_ssc,
 728         cdns_usb_ln_regs_ext_ssc,
 729 };
 730
 731 static const struct udevice_id cdns_sierra_id_table[] = {
 732         {
 733                 .compatible = "cdns,sierra-phy-t0",
 734                 .data = (ulong)&cdns_map_sierra,
 735         },
 736         {
 737                 .compatible = "ti,sierra-phy-t0",
 738                 .data = (ulong)&cdns_ti_map_sierra,
 739         },
 740         {}
 741 };
 742
 743 U_BOOT_DRIVER(sierra_phy_provider) = {
 744         .name           = "cdns,sierra",
 745         .id             = UCLASS_PHY,
 746         .of_match       = cdns_sierra_id_table,
 747         .probe          = cdns_sierra_phy_probe,
 748         .remove         = cdns_sierra_phy_remove,
 749         .ops            = &ops,
 750         .priv_auto      = sizeof(struct cdns_sierra_phy),
 751 };